URL
https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk
Subversion Repositories single-14-segment-display-driver-w-decoder
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- This comparison shows the changes necessary to convert path
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/5_1.ncd
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/5_1.pad
6,34 → 6,38
PACKAGE: CABGA381 |
Package Status: Final Version 1.36 |
|
Fri Jan 13 00:54:59 2017 |
Tue Jan 17 01:36:59 2017 |
|
Pinout by Port Name: |
+---------------+----------+--------------+-------+-----------+-------------------------------+ |
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties | |
+---------------+----------+--------------+-------+-----------+-------------------------------+ |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
+---------------+----------+--------------+-------+-----------+-------------------------------+ |
+---------------+----------+--------------+-------+-----------+---------------------------------+ |
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties | |
+---------------+----------+--------------+-------+-----------+---------------------------------+ |
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON | |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON | |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON | |
+---------------+----------+--------------+-------+-----------+---------------------------------+ |
|
Vccio by Bank: |
+------+-------+ |
| Bank | Vccio | |
+------+-------+ |
| 2 | 2.5V | |
| 3 | 2.5V | |
| 6 | 2.5V | |
| 8 | 2.5V | |
187,7 → 191,7
| K5/6 | unused, PULL:DOWN | | | PL44B | VREF1_6/LDQ41 | | |
| K18/2 | unused, PULL:DOWN | | | PR29D | RDQ29 | | |
| K19/2 | unused, PULL:DOWN | | | PR32B | PCLKC2_1/RDQ29 | | |
| K20/2 | unused, PULL:DOWN | | | PR32D | PCLKC2_0/RDQ29 | | |
| K20/2 | n_rst | LOCATED | LVCMOS25_IN | PR32D | PCLKC2_0/RDQ29 | | |
| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | | |
| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | | |
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | | |
218,8 → 222,8
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | | |
| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | | |
| P3/6 | unused, PULL:DOWN | | | PL68C | LLC_GPLL0T_IN/LDQ65 | | |
| P4/6 | unused, PULL:DOWN | | | PL68D | LLC_GPLL0C_IN/LDQ65 | | |
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | | |
275,7 → 279,7
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | | |
| T1/8 | unused, PULL:DOWN | | | PB4B | D6/IO6 | | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | | |
| T2/8 | unused, PULL:DOWN | | | PB13A | SN/CSN | | |
| T3/8 | unused, PULL:DOWN | | | PB18A | WRITEN | | |
| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | | |
325,6 → 329,8
List of All Pins' Locate Preferences Based on Final Placement After PAR |
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): |
|
LOCATE COMP "button" SITE "T1"; |
LOCATE COMP "clk" SITE "P3"; |
LOCATE COMP "disp_data[0]" SITE "M20"; |
LOCATE COMP "disp_data[10]" SITE "N18"; |
LOCATE COMP "disp_data[11]" SITE "N17"; |
341,6 → 347,7
LOCATE COMP "disp_data[8]" SITE "N16"; |
LOCATE COMP "disp_data[9]" SITE "M17"; |
LOCATE COMP "disp_sel" SITE "J1"; |
LOCATE COMP "n_rst" SITE "K20"; |
|
|
|
352,5 → 359,5
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. |
Copyright (c) 2001 Agere Systems All rights reserved. |
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. |
Fri Jan 13 00:54:59 2017 |
Tue Jan 17 01:36:59 2017 |
|
/5_1.par
1,6 → 1,6
|
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd" |
Fri Jan 13 00:54:53 2017 |
Tue Jan 17 01:36:43 2017 |
|
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3. |
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf |
24,34 → 24,39
Ignore Preference Error(s): True |
Device utilization summary: |
|
PIO (prelim) 16/245 6% used |
16/203 7% bonded |
PIO (prelim) 20/245 8% used |
20/203 9% bonded |
IOLOGIC 1/245 <1% used |
|
SLICE 0/21924 0% used |
SLICE 65/21924 <1% used |
|
GSR 1/1 100% used |
|
|
Number of Signals: 0 |
Number of Connections: 0 |
Number of Signals: 131 |
Number of Connections: 657 |
|
Pin Constraint Summary: |
16 out of 16 pins locked (100% locked). |
19 out of 19 pins locked (100% locked). |
|
The following 1 signal is selected to use the primary clock routing resources: |
clk_c (driver: clk, clk/ce/sr load #: 9/0/0) |
|
No signal is selected as Global Set/Reset. |
|
Signal n_rst_c is selected as Global Set/Reset. |
Starting Placer Phase 0. |
......... |
Finished Placer Phase 0. REAL time: 4 secs |
|
Finished Placer Phase 0. REAL time: 5 secs |
|
Starting Placer Phase 1. |
....................... |
Placer score = 63578. |
Finished Placer Phase 1. REAL time: 15 secs |
|
Placer score = 0. |
Finished Placer Phase 1. REAL time: 5 secs |
|
Starting Placer Phase 2. |
. |
Placer score = 0 |
Finished Placer Phase 2. REAL time: 5 secs |
Placer score = 63553 |
Finished Placer Phase 2. REAL time: 15 secs |
|
|
------------------ Clock Report ------------------ |
58,7 → 63,7
|
Global Clock Resources: |
CLK_PIN : 0 out of 12 (0%) |
GR_PCLK : 0 out of 12 (0%) |
GR_PCLK : 1 out of 12 (8%) |
PLL : 0 out of 4 (0%) |
DCS : 0 out of 2 (0%) |
DCC : 0 out of 60 (0%) |
73,12 → 78,14
PRIMARY : 0 out of 16 (0%) |
|
Quadrant BL Clocks: |
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 1 |
|
PRIMARY : 0 out of 16 (0%) |
PRIMARY : 1 out of 16 (6%) |
|
Quadrant BR Clocks: |
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 8 |
|
PRIMARY : 0 out of 16 (0%) |
PRIMARY : 1 out of 16 (6%) |
|
Edge Clocks: |
|
90,9 → 97,9
|
+ |
I/O Usage Summary (final): |
16 out of 245 (6.5%) PIO sites used. |
16 out of 203 (7.9%) bonded PIO sites used. |
Number of PIO comps: 16; differential: 0. |
20 out of 245 (8.2%) PIO sites used. |
20 out of 203 (9.9%) bonded PIO sites used. |
Number of PIO comps: 19; differential: 1. |
Number of Vref pins used: 0. |
|
I/O Bank Usage Summary: |
101,20 → 108,104
+----------+----------------+------------+------------+------------+ |
| 0 | 0 / 27 ( 0%) | - | - | - | |
| 1 | 0 / 33 ( 0%) | - | - | - | |
| 2 | 0 / 32 ( 0%) | - | - | - | |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - | |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - | |
| 6 | 1 / 33 ( 3%) | 2.5V | - | - | |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - | |
| 7 | 0 / 32 ( 0%) | - | - | - | |
| 8 | 1 / 13 ( 7%) | 2.5V | - | - | |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - | |
+----------+----------------+------------+------------+------------+ |
|
Total placer CPU time: 3 secs |
Total placer CPU time: 15 secs |
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd. |
|
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections. |
Timing score: 0 |
0 connections routed; 657 unrouted. |
Starting router resource preassignment |
|
Completed router resource preassignment. Real time: 23 secs |
|
Start NBR router at 01:37:06 01/17/17 |
|
***************************************************************** |
Info: NBR allows conflicts(one node used by more than one signal) |
in the earlier iterations. In each iteration, it tries to |
solve the conflicts while keeping the critical connections |
routed as short as possible. The routing process is said to |
be completed when no conflicts exist and all connections |
are routed. |
Note: NBR uses a different method to calculate timing slacks. The |
worst slack and total negative slack may not be the same as |
that in TRCE report. You should always run TRCE to verify |
your design. |
***************************************************************** |
|
Start NBR special constraint process at 01:37:06 01/17/17 |
|
Start NBR section for initial routing at 01:37:06 01/17/17 |
Level 1, iteration 1 |
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 24 secs |
Level 2, iteration 1 |
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
Level 3, iteration 1 |
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
Level 4, iteration 1 |
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
|
Info: Initial congestion level at 75% usage is 0 |
Info: Initial congestion area at 75% usage is 0 (0.00%) |
|
Start NBR section for normal routing at 01:37:07 01/17/17 |
Level 1, iteration 1 |
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
Level 2, iteration 1 |
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
Level 3, iteration 1 |
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
Level 4, iteration 1 |
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
|
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17 |
Level 4, iteration 1 |
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
|
Start NBR section for re-routing at 01:37:07 01/17/17 |
Level 4, iteration 1 |
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score; |
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs |
|
Start NBR section for post-routing at 01:37:07 01/17/17 |
|
End NBR router with 0 unrouted connection |
|
NBR Summary |
----------- |
Number of unrouted connections : 0 (0.00%) |
Number of connections with timing violations : 9 (1.37%) |
Estimated worst slack<setup> : -1.238ns |
Timing score<setup> : 7103 |
----------- |
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. |
|
|
|
Total CPU time 24 secs |
Total REAL time: 25 secs |
Completely routed. |
End of route. 657 routed (100.00%); 0 unrouted. |
|
Hold time timing score: 0, hold timing errors: 0 |
|
Timing score: 7103 |
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd. |
|
|
123,14 → 214,14
|
PAR_SUMMARY::Run status = completed |
PAR_SUMMARY::Number of unrouted conns = 0 |
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> |
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> |
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> |
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> |
PAR_SUMMARY::Worst slack<setup/<ns>> = -1.238 |
PAR_SUMMARY::Timing score<setup/<ns>> = 7.103 |
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.178 |
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 |
PAR_SUMMARY::Number of errors = 0 |
|
Total CPU time to completion: 4 secs |
Total REAL time to completion: 6 secs |
Total CPU time to completion: 25 secs |
Total REAL time to completion: 26 secs |
|
par done! |
|
/5_1_par.asd
1,4 → 1,10
[ActiveSupport PAR] |
; Global primary clocks |
GLOBAL_PRIMARY_USED = 1; |
; Global primary clock #0 |
GLOBAL_PRIMARY_0_SIGNALNAME = clk_c; |
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; |
GLOBAL_PRIMARY_0_LOADNUM = 9; |
; # of global secondary clocks |
GLOBAL_SECONDARY_USED = 0; |
; I/O Bank 0 Usage |
14,9 → 20,9
BANK_1_VREF1 = NA; |
BANK_1_VREF2 = NA; |
; I/O Bank 2 Usage |
BANK_2_USED = 0; |
BANK_2_USED = 1; |
BANK_2_AVAIL = 32; |
BANK_2_VCCIO = NA; |
BANK_2_VCCIO = 2.5V; |
BANK_2_VREF1 = NA; |
BANK_2_VREF2 = NA; |
; I/O Bank 3 Usage |
26,7 → 32,7
BANK_3_VREF1 = NA; |
BANK_3_VREF2 = NA; |
; I/O Bank 6 Usage |
BANK_6_USED = 1; |
BANK_6_USED = 3; |
BANK_6_AVAIL = 33; |
BANK_6_VCCIO = 2.5V; |
BANK_6_VREF1 = NA; |
38,7 → 44,7
BANK_7_VREF1 = NA; |
BANK_7_VREF2 = NA; |
; I/O Bank 8 Usage |
BANK_8_USED = 1; |
BANK_8_USED = 2; |
BANK_8_AVAIL = 13; |
BANK_8_VCCIO = 2.5V; |
BANK_8_VREF1 = NA; |
/DisplayDriverwDecoder_impl1.par
4,7 → 4,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. |
Copyright (c) 2001 Agere Systems All rights reserved. |
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. |
Fri Jan 13 00:54:53 2017 |
Tue Jan 17 01:36:43 2017 |
|
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t |
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir |
17,11 → 17,11
Level/ Number Worst Timing Worst Timing Run NCD |
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status |
---------- -------- ----- ------ ----------- ----------- ---- ------ |
5_1 * 0 - - - - 06 Complete |
5_1 * 0 -1.238 7103 0.178 0 26 Complete |
|
|
* : Design saved. |
|
Total (real) run time for 1-seed: 6 secs |
Total (real) run time for 1-seed: 26 secs |
|
par done! |