OpenCores
URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /single-14-segment-display-driver-w-decoder/trunk/Project
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1.ncd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1.pad
6,34 → 6,38
PACKAGE: CABGA381
Package Status: Final Version 1.36
 
Fri Jan 13 00:54:59 2017
Tue Jan 17 01:36:59 2017
 
Pinout by Port Name:
+---------------+----------+--------------+-------+-----------+-------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+-------------------------------+
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
+---------------+----------+--------------+-------+-----------+-------------------------------+
+---------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+---------------+----------+--------------+-------+-----------+---------------------------------+
 
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 2 | 2.5V |
| 3 | 2.5V |
| 6 | 2.5V |
| 8 | 2.5V |
187,7 → 191,7
| K5/6 | unused, PULL:DOWN | | | PL44B | VREF1_6/LDQ41 | |
| K18/2 | unused, PULL:DOWN | | | PR29D | RDQ29 | |
| K19/2 | unused, PULL:DOWN | | | PR32B | PCLKC2_1/RDQ29 | |
| K20/2 | unused, PULL:DOWN | | | PR32D | PCLKC2_0/RDQ29 | |
| K20/2 | n_rst | LOCATED | LVCMOS25_IN | PR32D | PCLKC2_0/RDQ29 | |
| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | |
| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | |
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | |
218,8 → 222,8
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | |
| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | |
| P3/6 | unused, PULL:DOWN | | | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | unused, PULL:DOWN | | | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
275,7 → 279,7
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | |
| T1/8 | unused, PULL:DOWN | | | PB4B | D6/IO6 | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | |
| T2/8 | unused, PULL:DOWN | | | PB13A | SN/CSN | |
| T3/8 | unused, PULL:DOWN | | | PB18A | WRITEN | |
| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | |
325,6 → 329,8
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
 
LOCATE COMP "button" SITE "T1";
LOCATE COMP "clk" SITE "P3";
LOCATE COMP "disp_data[0]" SITE "M20";
LOCATE COMP "disp_data[10]" SITE "N18";
LOCATE COMP "disp_data[11]" SITE "N17";
341,6 → 347,7
LOCATE COMP "disp_data[8]" SITE "N16";
LOCATE COMP "disp_data[9]" SITE "M17";
LOCATE COMP "disp_sel" SITE "J1";
LOCATE COMP "n_rst" SITE "K20";
 
 
 
352,5 → 359,5
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Fri Jan 13 00:54:59 2017
Tue Jan 17 01:36:59 2017
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1.par
1,6 → 1,6
 
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Fri Jan 13 00:54:53 2017
Tue Jan 17 01:36:43 2017
 
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
24,34 → 24,39
Ignore Preference Error(s): True
Device utilization summary:
 
PIO (prelim) 16/245 6% used
16/203 7% bonded
PIO (prelim) 20/245 8% used
20/203 9% bonded
IOLOGIC 1/245 <1% used
 
SLICE 0/21924 0% used
SLICE 65/21924 <1% used
 
GSR 1/1 100% used
 
 
Number of Signals: 0
Number of Connections: 0
Number of Signals: 131
Number of Connections: 657
 
Pin Constraint Summary:
16 out of 16 pins locked (100% locked).
19 out of 19 pins locked (100% locked).
 
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
 
No signal is selected as Global Set/Reset.
 
Signal n_rst_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 4 secs
 
Finished Placer Phase 0. REAL time: 5 secs
 
Starting Placer Phase 1.
.......................
Placer score = 63578.
Finished Placer Phase 1. REAL time: 15 secs
 
Placer score = 0.
Finished Placer Phase 1. REAL time: 5 secs
 
Starting Placer Phase 2.
.
Placer score = 0
Finished Placer Phase 2. REAL time: 5 secs
Placer score = 63553
Finished Placer Phase 2. REAL time: 15 secs
 
 
------------------ Clock Report ------------------
58,7 → 63,7
 
Global Clock Resources:
CLK_PIN : 0 out of 12 (0%)
GR_PCLK : 0 out of 12 (0%)
GR_PCLK : 1 out of 12 (8%)
PLL : 0 out of 4 (0%)
DCS : 0 out of 2 (0%)
DCC : 0 out of 60 (0%)
73,12 → 78,14
PRIMARY : 0 out of 16 (0%)
 
Quadrant BL Clocks:
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 1
 
PRIMARY : 0 out of 16 (0%)
PRIMARY : 1 out of 16 (6%)
 
Quadrant BR Clocks:
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 8
 
PRIMARY : 0 out of 16 (0%)
PRIMARY : 1 out of 16 (6%)
 
Edge Clocks:
 
90,9 → 97,9
 
+
I/O Usage Summary (final):
16 out of 245 (6.5%) PIO sites used.
16 out of 203 (7.9%) bonded PIO sites used.
Number of PIO comps: 16; differential: 0.
20 out of 245 (8.2%) PIO sites used.
20 out of 203 (9.9%) bonded PIO sites used.
Number of PIO comps: 19; differential: 1.
Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
101,20 → 108,104
+----------+----------------+------------+------------+------------+
| 0 | 0 / 27 ( 0%) | - | - | - |
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 0 / 32 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 1 / 33 ( 3%) | 2.5V | - | - |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 1 / 13 ( 7%) | 2.5V | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 3 secs
Total placer CPU time: 15 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
Timing score: 0
0 connections routed; 657 unrouted.
Starting router resource preassignment
 
Completed router resource preassignment. Real time: 23 secs
 
Start NBR router at 01:37:06 01/17/17
 
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
 
Start NBR special constraint process at 01:37:06 01/17/17
 
Start NBR section for initial routing at 01:37:06 01/17/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
 
Start NBR section for normal routing at 01:37:07 01/17/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for re-routing at 01:37:07 01/17/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for post-routing at 01:37:07 01/17/17
 
End NBR router with 0 unrouted connection
 
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 9 (1.37%)
Estimated worst slack<setup> : -1.238ns
Timing score<setup> : 7103
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
 
 
 
Total CPU time 24 secs
Total REAL time: 25 secs
Completely routed.
End of route. 657 routed (100.00%); 0 unrouted.
 
Hold time timing score: 0, hold timing errors: 0
 
Timing score: 7103
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
 
123,14 → 214,14
 
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Worst slack<setup/<ns>> = -1.238
PAR_SUMMARY::Timing score<setup/<ns>> = 7.103
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.178
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
 
Total CPU time to completion: 4 secs
Total REAL time to completion: 6 secs
Total CPU time to completion: 25 secs
Total REAL time to completion: 26 secs
 
par done!
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1_par.asd
1,4 → 1,10
[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 1;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = clk_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_0_LOADNUM = 9;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 0;
; I/O Bank 0 Usage
14,9 → 20,9
BANK_1_VREF1 = NA;
BANK_1_VREF2 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 0;
BANK_2_USED = 1;
BANK_2_AVAIL = 32;
BANK_2_VCCIO = NA;
BANK_2_VCCIO = 2.5V;
BANK_2_VREF1 = NA;
BANK_2_VREF2 = NA;
; I/O Bank 3 Usage
26,7 → 32,7
BANK_3_VREF1 = NA;
BANK_3_VREF2 = NA;
; I/O Bank 6 Usage
BANK_6_USED = 1;
BANK_6_USED = 3;
BANK_6_AVAIL = 33;
BANK_6_VCCIO = 2.5V;
BANK_6_VREF1 = NA;
38,7 → 44,7
BANK_7_VREF1 = NA;
BANK_7_VREF2 = NA;
; I/O Bank 8 Usage
BANK_8_USED = 1;
BANK_8_USED = 2;
BANK_8_AVAIL = 13;
BANK_8_VCCIO = 2.5V;
BANK_8_VREF1 = NA;
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/DisplayDriverwDecoder_impl1.par
4,7 → 4,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Fri Jan 13 00:54:53 2017
Tue Jan 17 01:36:43 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
17,11 → 17,11
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 06 Complete
5_1 * 0 -1.238 7103 0.178 0 26 Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 6 secs
Total (real) run time for 1-seed: 26 secs
 
par done!
/Lattice_FPGA_Build/impl1/dm/layer0.xdm
14,44 → 14,211
/>S1S<FOksC=Rb"\B:DO#O\N8Hl8FM\Ud3_cGn\M#$b#LNCH\DLE\P8s\NH30EP"E8R"N=6D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:DO#O\N8Hl8FM\Ud3_cGn\M#$b#LNCH\DLE\P8M\k#MHoCP83ER8"Nn=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d_3UG\nc#b$MLCN#\LDH\8PE\bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d_3UG\ncO_NCDsHLN\s$#0$MEHC##E\P8CD\Okb6lE3P8N"R=""UR"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
S<k1FsROCbB=":s\uFO[C0##\HDMoCc-4-o#Cl0CM-#8Hb$DN-H8sP-CsIC-8OCF8ss\uFO[C0F\1kCsO#H\7#NbD$H7sPICs7FCO8_Csa3FbP"E8R"N=gD"R=E"P8RD"O#DH0-="4b"RD0H#=4"Rj>"/
<SS1sFkObCR=:"B\Fus[0CO#H\#MCoD--4c#lCoC-M08bH#D-N$8PsHCIs--O8CFs8C\Fus[0CO\k1Fs#OC\#7Hb$DN7PsHCssWNCbbsE3P8N"R=j"4"=RD"8PEDO"RD0H#=g"R"DRbH=#0""-4/S>
<F/1kCsO#
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d_3UG\ncO_NCDsHLN\s$#0$MEHC##E\P8CD\Okb6lE3P8N"R=""UR"D=PDE8"DROH=#0""-4RHbD#"0=R/g">S
S<k1FsROCbB=":s\uFO[C0##\HDMoCc-4-o#Cl0CM-#8Hb$DN-H8sP-CsIC-8OCF8ss\uFO[C0F\1kCsO#C\7OHF8Mao_NCLD\v)m_Bq1Q7Q_C8OFC7s\H)#0F#lqO7HHC8OFC7s\H)#0F#lqO7HHC8OFC7s\H)#0F#lqO7HHC8OFCPs3ER8"Ng=""=RD"8PEDO"RD0H#=U"R"DRbH=#0"4R4"
/>S1S<FOksC=Rb"\B:DO#O\N8Hl8FM\Ud3_cGn\M#$b#LNCH\DLk\DO0CM\bCO63klP"E8R"N=4Rj"DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/
<SS1sFkObCR=:"B\Fus[0CO#H\#MCoD--4c#lCoC-M08bH#D-N$8PsHCIs--O8CFs8C\Fus[0CO\k1Fs#OC\Bq1QCQ7OCF8sE3P8N"R=4"4"=RD"8PEDO"RD0H#=g"R"DRbH=#0".R4"
/>S1S<FOksC=Rb"\B:u[sFC#O0\M#Ho-DC4#c-CColM80-HD#bN8$-sCHPs--I8FCO8\Csu[sFC\O01sFkO\C#7bH#D7N$sCHPsCI7OCF8sF_abE3P8N"R=."4"=RD"8PEDO"RD0H#=4"R4b"RD0H#=4"Rd>"/
<SS1sFkObCR=:"B\Fus[0CO#H\#MCoD--4c#lCoC-M08bH#D-N$8PsHCIs--O8CFs8C\Fus[0CO\k1Fs#OC\#7Hb$DN7PsHCssWNCbbsE3P8N"R=d"4"=RD"8PEDO"RD0H#=4"R.b"RD0H#=4"-"
/>S1</FOksC
#>
!S<-v-RFD8kCFRsF-0R-S>
<F)F0=RM"sIF H37#NbD$H7sPWCssbNbCNs3s"OE/
>
S-<!-FRv8CkDRFsF0-R-><
S)0FFR"M=I Fs3#7Hb$DN7PsHCssWNCbbss3NO/E">
 
<
S!R--vkF8D7CRCMVHHF0HM-R-><
S7RCVMI="F3s )4mv.4UXq$3#MD_LN_O L"FGR"D=PDE8"S>
SR<WNU=""DRL=j"U4L"RO4="jC"RDU="jR4"C"O=4RU"/S>
SR<qM3="CCG0sDMN"=RP"/4">S
S<MqR=F"3shHoN"lCR"P=I Fs3v)m4X.U4#q3$LM_D NO_GLF"
/>SqS<R"M=3ONsEDVHCP"R=""U/S>
SR<qM3="lkF8DHCVDRC"PU=""
/>SqS<R"M=3MDNosuNN"l#R"P=H0MHP"ND/S>
SR<qM3="bNNslba$CR#"P#="0D8_FOoH_OPC05Fs4R.(8MFI0jFR2>"/
<SSq=RM"N3DMNoushNlN#lC"=RP"HHM0DPN"
/>SuS<R"M=H0MHP"NDR"P=&FJk0j;jjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjJj&k;F0"
/>SqS<R"M=3HFsoOqsElhNCP"R=J"&k;F0#_$MLODN F_LGk&JF"0;/S>
SR<qM3="#_$Mks#CLRL"P4=""
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jj3jjjjj"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
/>SqS<R"M=#_$MLODN F_LGP"R=""4/
>
 
 
/S<7>CV
<
S!R--vkF8D7CRCMVHHF0HM-R-><
S7RCVMI="F3s 7bH#D7N$sCHPsCI7OCF8sF_abs3NORE"DP="E"8D>S
S<NWR=""gR=LD""4nR=LO"R("C"D=4Rn"C"O=dR4"/S>
SR<qM3="FosHhCNl"=RP"sIF H37#NbD$H7sPICs7FCO8_Csa3FbNEsO"
/>SqS<R"M=3ONsEDVHCP"R=""g/S>
SR<qM3="lkF8DHCVDRC"Pg=""
S7RCVMI="F3s 70H#)qFl#HOH7FCO83Cs#k0sOs0kCD"R=E"P8>D"
<SSW=RN"Rg"L"D=4R."L"O=(C"RD4=".C"RO.="6/"R>S
S<MqR=F"3shHoN"lCR"P=I Fs3#7H0l)FqH#OHO7CFs8C3s#0kkO0s/C">S
S<MqR=N"3sVOEH"DCR"P=g>"/
<SSq=RM"F3l8CkDVCHD"=RP"/g">S
S<MqR=F"3sqHoshOEN"lCR"P=&FJk00;#s0kOk&sCJ0kF;>"/
<SSq=RM"D3OCkNMb0_#C_b.0CHl"=RP"jj3jjjjj>"/
<SSq=RM"03#lH0D#H00lRC"Pj="36j4n".6/S>
SR<qMh="t77_)vB_q"1iR"P=4>"/
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
SC<)V=RM"sIF m3)vU4.X34q#_$MLODN F_LGH"R=C"ll__j4>d"
SSS<NWR=""gR=LD"".6R=LO"Rc"C"D=.R6"C"O=4R4"/S>
SqS<R"M=3M#$_Ck#s__#bNNslR#"P&="J0kF;HHM0DPNRk&JF"0;/S>
SqS<R"M=H0MHP"NDR"P=&FJk04;4jj444jjj444444444444444444444j444j444jjj444444444444444444444j44444j4444444444jj4jj4jj44j44j4j4444444444444444444444444444444Jj&k;F0"
/>S<SSq=RM"$3#M0_N0sVFl"N0R"P=&FJk0M;HHN0PD&=XJ0kF;>"/
<SS/V)C>S
S<V)CR"M=I Fs3v)m4X.U4#q3$LM_D NO_GLF"=RH"llC_4j_.
">S<SSW=RN"Rg"L"D=dR4"L"O=cC"RDd="4C"RO4="4/"R>S
SSR<qM3="#_$Mks#C_b#_NlsN#P"R=J"&k;F0H0MHPRND&FJk0/;">S
SSR<qM#="$LM_D NO_GLF"=RP"/4">S
SSR<qM#="$DM_HOL_C"DDR"P=4>"/
SSS<MqR=M"HHN0PDP"R=J"&k;F04j44444j4j4444444444444j4j4444j44444444j4j4444444444444j4j4444j4j44444j44444444444j4j4j44j44j444j4jj4jjj44444444444jj44444444444&FJk0/;">S
SSR<qM3="#_$MNV00FNsl0P"R=J"&k;F0H0MHP=NDXk&JF"0;/S>
S)</C
V>S)S<CMVR=F"Is) 3m.v4UqX43M#$_NLDOL _FRG"Hl="Cjl__"44>S
SSR<WNg=""DRL=("d"ORL=""cR=CD""d(R=CO""44R
/>S<SSq=RM"$3#M#_kC#s__sbNN"l#R"P=&FJk0M;HHN0PDJR&k;F0"
/>S<SSq=RM"M#$_NLDOL _FRG"P4=""
/>S<SSq=RM"M#$_LDH_DOCDP"R=""4/S>
SqS<R"M=H0MHP"NDR"P=&FJk04;4444j44jj4j44jj44444j44444444444444j444jj4j44jj44444j44444444444444j44444j44444444j444jj4j44j4j44444444444444444444444444j4444J4&k;F0"
/>S<SSq=RM"$3#M0_N0sVFl"N0R"P=&FJk0M;HHN0PD&=XJ0kF;>"/
<SS/V)C>S
S<V)CR"M=I Fs3v)m4X.U4#q3$LM_D NO_GLF"=RH"llC_4j_j
">S<SSW=RN"Rg"L"D=cRd"L"O=cC"RDc="dC"RO4="4/"R>S
SSR<qM3="#_$Mks#C_b#_NlsN#P"R=J"&k;F0H0MHPRND&FJk0/;">S
SSR<qM#="$LM_D NO_GLF"=RP"/4">S
SSR<qM#="$DM_HOL_C"DDR"P=4>"/
SSS<MqR=M"HHN0PDP"R=J"&k;F04444jjjj44j44444444jj4444444444444j44jjj44j44444444jj444444444444j44444444444j44j4444jj4j4jjj444jj44444j444444444444444444444j44&FJk0/;">S
SSR<qM3="#_$MNV00FNsl0P"R=J"&k;F0H0MHP=NDXk&JF"0;/S>
S)</C
V>S)S<CMVR=F"Is) 3m.v4UqX43M#$_NLDOL _FRG"Hl="Cjl__>g"
SSS<NWR=""gR=LD""cgR=LO"Rc"C"D=cRg"C"O=4Rj"/S>
SqS<R"M=3M#$_Ck#s__#bNNslR#"P&="J0kF;HHM0DPNRk&JF"0;/S>
SqS<R"M=#_$MLODN F_LGP"R=""4/S>
SqS<R"M=#_$MD_HLODCD"=RP"/4">S
SSR<qMH="MPH0NRD"P&="J0kF;444j4444444j44444444j444444j44j444444444444j44444444j444444j44jj44444jj44444444444444jj4444j4jj4jjj444jj44444444j4444j4444444444k&JF"0;/S>
SqS<R"M=3M#$_0N0VlFsNR0"P&="J0kF;HHM0DPN=JX&k;F0"
/>S/S<)>CV
<SS)RCVMI="F3s )4mv.4UXq$3#MD_LN_O L"FGR"H=l_Clj"_U>S
SSR<WNg=""DRL=6"6"ORL=""cR=CD""66R=CO""4jR
/>S<SSq=RM"$3#M#_kC#s__sbNN"l#R"P=&FJk0M;HHN0PDJR&k;F0"
/>S<SSq=RM"M#$_NLDOL _FRG"P4=""
/>S<SSq=RM"M#$_LDH_DOCDP"R=""4/S>
SqS<R"M=H0MHP"NDR"P=&FJk04;4j444j4j444444j44j4444444444444j444j4j4j444444j44j444444444444j4444444444444444444j44jj44j44j444j44j4j444444444444444444444444J4&k;F0"
/>S<SSq=RM"$3#M0_N0sVFl"N0R"P=&FJk0M;HHN0PD&=XJ0kF;>"/
<SS/V)C>S
S<V)CR"M=I Fs3v)m4X.U4#q3$LM_D NO_GLF"=RH"llC_(j_"S>
SWS<R"N=gL"RDn="4L"ROc=""DRC=4"n"ORC=j"4">R/
SSS<MqR=#"3$kM_#_Cs#N_bs#Nl"=RP"k&JFH0;MPH0N&DRJ0kF;>"/
SSS<MqR=$"#MD_LN_O L"FGR"P=4>"/
SSS<MqR=$"#MH_DLC_ODRD"P4=""
/>S<SSq=RM"HHM0DPN"=RP"k&JF40;j4j444444j44j44j44444j4j44j4j4j4444444444j44j44j44444j4j44j4jjjj44j444jjjj4jj4444jj4j4444jjj44444jj4j4jj44444444jj44j4jjjj4jj&44J0kF;>"/
SSS<MqR=#"3$NM_0F0Vs0lN"=RP"k&JFH0;MPH0NXD=&FJk0/;">S
S<C/)VS>
SC<)V=RM"sIF m3)vU4.X34q#_$MLODN F_LGH"R=C"ll__jn
">S<SSW=RN"Rg"L"D=nR("L"O=cC"RDn="(C"RO4="j/"R>S
SSR<qM3="#_$Mks#C_b#_NlsN#P"R=J"&k;F0H0MHPRND&FJk0/;">S
SSR<qM#="$LM_D NO_GLF"=RP"/4">S
SSR<qM#="$DM_HOL_C"DDR"P=4>"/
SSS<MqR=M"HHN0PDP"R=J"&k;F044j4j4444444jjj44444jj4444jj444j444444444444jjj44444jj4444jj444j444j4j4j4jjj44j444jjj4j44j4jj444444jjjjj44444444j4j44jjj4jjj44j4&FJk0/;">S
SSR<qM3="#_$MNV00FNsl0P"R=J"&k;F0H0MHP=NDXk&JF"0;/S>
S)</C
V>S)S<CMVR=F"Is) 3m.v4UqX43M#$_NLDOL _FRG"Hl="Cjl__>6"
SSS<NWR=""gR=LD""(dR=LO"Rc"C"D=(Rd"C"O=4Rj"/S>
SqS<R"M=3M#$_Ck#s__#bNNslR#"P&="J0kF;HHM0DPNRk&JF"0;/S>
SqS<R"M=#_$MLODN F_LGP"R=""4/S>
SqS<R"M=#_$MD_HLODCD"=RP"/4">S
SSR<qMH="MPH0NRD"P&="J0kF;4j444444jjj4jjjjjjjj4j4jjjj4jj4444444j44jjj4jjjjjjjj4j4jjjj4jj4j4444j44jj4jj444j44444444j44j4jj4444j4jj4444444444jjjj4jjj4jj444jk&JF"0;/S>
SqS<R"M=3M#$_0N0VlFsNR0"P&="J0kF;HHM0DPN=JX&k;F0"
/>S/S<)>CV
<SS)RCVMI="F3s )4mv.4UXq$3#MD_LN_O L"FGR"H=l_Clj"_c>S
SSR<WNg=""DRL=g"("ORL=""cR=CD""(gR=CO""4jR
/>S<SSq=RM"$3#M#_kC#s__sbNN"l#R"P=&FJk0M;HHN0PDJR&k;F0"
/>S<SSq=RM"M#$_NLDOL _FRG"P4=""
/>S<SSq=RM"M#$_LDH_DOCDP"R=""4/S>
SqS<R"M=H0MHP"NDR"P=&FJk0j;j44444j4jjj44jjjjjjjj4jjjj44jj444444j4j4jjj44jjjjjjjj4jjjj44jj4j444444jj44j444jj444444444444j44444jj4444444444j4j4jj44jj44j444Jj&k;F0"
/>S<SSq=RM"$3#M0_N0sVFl"N0R"P=&FJk0M;HHN0PD&=XJ0kF;>"/
<SS/V)C>S
S<V)CR"M=I Fs3v)m4X.U4#q3$LM_D NO_GLF"=RH"llC_dj_"S>
SWS<R"N=gL"RDU="6L"ROc=""DRC=6"U"ORC=j"4">R/
SSS<MqR=#"3$kM_#_Cs#N_bs#Nl"=RP"k&JFH0;MPH0N&DRJ0kF;>"/
SSS<MqR=$"#MD_LN_O L"FGR"P=4>"/
SSS<MqR=$"#MH_DLC_ODRD"P4=""
/>S<SSq=RM"HHM0DPN"=RP"k&JFj0;4444j4444jj44jj4444jjj444jjjjj444jj4j4444jj44jj4444jjj444jjjj44j44j444jjjjj4j44jj4444444jj4j444444j4j44j44444444jjjj44jjjjj4j&4jJ0kF;>"/
SSS<MqR=#"3$NM_0F0Vs0lN"=RP"k&JFH0;MPH0NXD=&FJk0/;">S
S<C/)VS>
SC<)V=RM"sIF m3)vU4.X34q#_$MLODN F_LGH"R=C"ll__j.
">S<SSW=RN"Rg"L"D=gR4"L"O=cC"RDg="4C"RO4="j/"R>S
SSR<qM3="#_$Mks#C_b#_NlsN#P"R=J"&k;F0H0MHPRND&FJk0/;">S
SSR<qM#="$LM_D NO_GLF"=RP"/4">S
SSR<qM#="$DM_HOL_C"DDR"P=4>"/
SSS<MqR=M"HHN0PDP"R=J"&k;F0j4444444j44jj44jj4jj4jj4jj4444jj444j4444j44jj44jj4jj4jj4jj4444jj44444j4jjjj4jj4j444444444jjjj44j4444444444444444444jjjjjjjj4jj4j&FJk0/;">S
SSR<qM3="#_$MNV00FNsl0P"R=J"&k;F0H0MHP=NDXk&JF"0;/S>
S)</C
V>S)S<CMVR=F"Is) 3m.v4UqX43M#$_NLDOL _FRG"Hl="Cjl__>4"
SSS<NWR=""gR=LD""g(R=LO"Rc"C"D=gR("C"O=4Rj"/S>
SqS<R"M=3M#$_Ck#s__#bNNslR#"P&="J0kF;HHM0DPNRk&JF"0;/S>
SqS<R"M=#_$MLODN F_LGP"R=""4/S>
SqS<R"M=#_$MD_HLODCD"=RP"/4">S
SSR<qMH="MPH0NRD"P&="J0kF;4jj44444jj44j4jjjjj444jj444jj4j4j4j44444jj44j4jjjjj444jj444jj4jj4j44j44j4j4jjjjj444444444444jj4444444j4444444444j444jjjj4j4jjjjjk&JF"0;/S>
SqS<R"M=3M#$_0N0VlFsNR0"P&="J0kF;HHM0DPN=JX&k;F0"
/>S/S<)>CV
<SS)RCVMI="F3s )4mv.4UXq$3#MD_LN_O L"FGR"H=l_Clj"_j>S
SSR<WNg=""DRL=j"4dL"ROc=""DRC=j"4dC"RO4="j/"R>S
SSR<qM3="#_$Mks#C_b#_NlsN#P"R=J"&k;F0H0MHPRND&FJk0/;">S
SSR<qM#="$LM_D NO_GLF"=RP"/4">S
SSR<qM#="$DM_HOL_C"DDR"P=4>"/
SSS<MqR=M"HHN0PDP"R=J"&k;F0j44444j44j44jjjjj4444444jjjjj4jj44jjj4j44j44jjjjj4444444jjjjjjjjj4444j4jj4jjjjj4444444444jj4j4444444jjj444444444jjjjjjjjj4jjjjj4&FJk0/;">S
SSR<qM3="#_$MNV00FNsl0P"R=J"&k;F0H0MHP=NDXk&JF"0;/S>
S)</C
V>S7</C
V>
!S<-v-RFD8kCCR7VHHM0MHFR>--
7S<CMVR=F"Isq 31QBQ7FCO83CsNEsO"=RD"8PED
">SWS<R"N=4R4"L"D=4R6"L"O=(C"RD4="6C"RO4="U/"R>S
S<MqR=F"3shHoN"lCR"P=I Fs3Bq1QCQ7OCF8ss3NO/E">S
S<MqR=N"3sVOEH"DCR"P=4/4">S
S<MqR=l"3FD8kCDVHCP"R=4"4"
/>SqS<R"M=3HFsoOqsElhNCP"R=J"&k;F0NEsO&FJk0/;">S
S<MqR=O"3DMCNk#b_0.Cb_l0HCP"R=3"jjn46./6">S
S<MqR=O"3DMCNk#b_0.Cb_l0HCP"R=3"jjjjjj/j">S
S<MqR=O"3DMCNk#b_04Cb_l0HCP"R=3"jjjjjj/j">S
S<MqR=#"30Dl0H0#0H"lCR"P=jj3jjjjj"
/>
/S<7>CV
<
S!R--vkF8D7CRCMVHHF0HM-R-><
S7RCVMI="F3s 7bH#D7N$sCHPsNWsbsbC3ONsED"R=E"P8>D"
<SSW=RN""4jR=LD""46R=LO"R("C"D=4R6"C"O=.Rn"/S>
SR<qM3="NEsOVCHD"=RP""4j/S>
SR<qM3="lkF8DHCVDRC"P4="j>"/
<SSq=RM"s3FHsoqONEhlRC"P&="J0kF;ONsEk&JF"0;/S>
SR<qM3="ONDCM_kb#b0C.H_0lRC"Pj="3jjjj"jj/S>
SR<qM3="#00lD0H#0CHl"=RP"jj3jjjjj>"/
<SSq=RM"HFsoM_H#F0_VP"R=J"&k;F07bH#D7N$sCHPsNWsbsbC&FJk0/;">S
S<MqR=F"3shHoN"lCR"P=&FJk0H;7#NbD$H7sPWCssbNbCJs&k;F0"
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
SC<)V=RM"sIF H37#F0)lOq#HCH7OCF8s03#s0kOk"sCR"H=s_Fl8FCO8oHM_L0ND>C"
SSS<NWR=4"4"DRL=6"d"ORL=("."DRC=6"d"ORC=j"6">R/
<SS/V)C><
S/V7C>S
 
<-!-R8vFkRDC7HCVMHH0F-MR-S>
<V7CR"M=I Fs3#7Hb$DN7PsHC7sIC8OFCas_FNb3s"OER"D=PDE8"S>
SR<WN4=".L"RD4="nL"RO(=""DRC=n"4"ORC=4"d">R/
<SSq=RM"s3FHNohlRC"PI="F3s 7bH#D7N$sCHPsCI7OCF8sF_abs3NO/E">S
S<MqR=N"3sVOEH"DCR"P=4/.">S
S<MqR=l"3FD8kCDVHCP"R=."4"
/>SqS<R"M=3HFsoOqsElhNCP"R=J"&k;F0NEsO&FJk0/;">S
S<MqR=O"3DMCNk#b_0.Cb_l0HCP"R=3"jjjjjj/j">S
S<MqR=#"30Dl0H0#0H"lCR"P=jj3jjjjj"
/>
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
SC<)V=RM"sIF 13qB7QQC8OFCNs3s"OER"H=NH#OHC_8OCF8sF_l8CkD"S>
SWS<R"N=4R."L"D=(Rc"L"O=dR."C"D=(Rc"C"O=cRU"/S>
S)</C
V>S7</C
V>
!S<-v-RFD8kCCR7VHHM0MHFR>--
7S<CMVR=F"Is7 3HD#bNs$7HsPCWbsNb3CsNEsO"=RD"8PED
">SWS<R"N=4Rd"L"D=4R6"L"O=(C"RD4="6C"RO.="n/"R>S
S<MqR=N"3sVOEH"DCR"P=4/d">S
S<MqR=l"3FD8kCDVHCP"R=d"4"
/>SqS<R"M=3HFsoOqsElhNCP"R=J"&k;F0NEsO&FJk0/;">S
S<MqR=O"3DMCNk#b_0.Cb_l0HCP"R=3"jjjjjj/j">S
S<MqR=O"3DMCNk#b_04Cb_l0HCP"R=3"jjjjjj/j">S
S<MqR=#"30Dl0H0#0H"lCR"P=jj3jjjjj"
/>SqS<R"M=FosH_#HM0V_F"=RP"k&JF70;HD#bNs$7HsPCWbsNb&CsJ0kF;>"/
<SSq=RM"s3FHNohlRC"P&="J0kF;#7Hb$DN7PsHCssWNCbbsk&JF"0;/
>
 
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
SC<)V=RM"sIF H37#NbD$H7sPICs7FCO8_Csa3FbNEsO"=RH"I777F_ab
">S<SSW=RN""4jR=LD""c4R=LO""4nR=CD""c4R=CO""c6R
">S<SSW=RN""4dR=LD""U6R=LO""4nR=CD""U6R=CO""c6R
/>S/S<)>CV
/S<7>CV
]</70p1s0kOk>sC
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_compiler_notes.txt
4,6 → 4,11
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
@N|Running in 64-bit mode
 
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_compiler_runstatus.xml
14,11 → 14,11
</job_status>
<job_info>
<info name="Notes">
<data>8</data>
<data>13</data>
<report_link name="more"><data>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\DisplayDriverwDecoder_impl1_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>1</data>
<data>4</data>
<report_link name="more"><data>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\DisplayDriverwDecoder_impl1_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
35,7 → 35,7
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1484261677</data>
<data type="timestamp">1484608749</data>
</info>
</job_info>
</job_run_status>
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_compiler_warnings.txt
1,2 → 1,5
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
 
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_area_report.xml
9,7 → 9,7
<title>Resource Usage</title>
</report_link>
<parameter tooltip="Total Register bits used" name="Register bits">
<data>8</data>
<data>9</data>
</parameter>
<parameter tooltip="Total I/O cells used" name="I/O cells">
<data>18</data>
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_combined_clk.rpt
5,15 → 5,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_notes.txt
1,6 → 1,7
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MT206 |Auto Constrain mode is enabled
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_resourceusage.rpt
1,17 → 1,18
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
Details:
FD1S3IX: 5
FD1S3JX: 3
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_runstatus.xml
13,7 → 13,7
</job_status>
<job_info>
<info name="Notes">
<data>10</data>
<data>11</data>
<report_link name="more">
<data>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\DisplayDriverwDecoder_impl1_fpga_mapper_notes.txt</data>
</report_link>
34,13 → 34,13
<data>0h:00m:01s</data>
</info>
<info name="Real Time">
<data>0h:00m:02s</data>
<data>0h:00m:01s</data>
</info>
<info name="Peak Memory">
<data>144MB</data>
<data>145MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1484261682</data>
<data type="timestamp">1484608753</data>
</info>
</job_info>
</job_run_status>
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_timing_report.xml
15,9 → 15,9
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>DisplayDriverWrapper|clk</data>
<data>1220.4 MHz</data>
<data>1037.3 MHz</data>
<data>-0.145</data>
<data>DisplayDriverWrapper|button</data>
<data>443.5 MHz</data>
<data>377.0 MHz</data>
<data>-0.398</data>
</row>
</report_table>
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_warnings.txt
1,9 → 15,9
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_premap_runstatus.xml
40,7 → 40,7
<data>141MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1484261679</data>
<data type="timestamp">1484608751</data>
</info>
</job_info>
</job_run_status>
/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_premap_warnings.txt
1,7 → 40,7
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
/Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_errors.txt
0,0 → 1,3
@E: CD134 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":32:33:32:35|No such identifier, rst, of proper type in current declarative region
@E: Parse errors encountered - exiting
 
Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_errors.txt Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_notes.txt =================================================================== --- Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_notes.txt (revision 5) +++ Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_notes.txt (revision 6) @@ -4,7 +4,12 @@ @N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper. @N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch. @N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch. -@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused. +@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch. +@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure. +@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box. +@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused. +@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused. +@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused. @N|Running in 64-bit mode @N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level @N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level Index: Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_runstatus.xml =================================================================== --- Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_runstatus.xml (revision 5) +++ Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_runstatus.xml (revision 6) @@ -14,11 +14,11 @@ - 10 + 15 C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\impl1_compiler_notes.txt - 2 + 1 C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\impl1_compiler_warnings.txt @@ -35,7 +35,7 @@ - - 1483829372 + 1484609376 \ No newline at end of file Index: Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_warnings.txt =================================================================== --- Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_warnings.txt (revision 5) +++ Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_warnings.txt (revision 6) @@ -1,3 +1,2 @@ -@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration. -@W: CL240 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":38:8:38:16|disp_data is not assigned a value (floating) -- simulation mismatch possible. +@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_area_report.xml
9,10 → 9,10
<title>Resource Usage</title>
</report_link>
<parameter tooltip="Total Register bits used" name="Register bits">
<data>8</data>
<data>13</data>
</parameter>
<parameter tooltip="Total I/O cells used" name="I/O cells">
<data>17</data>
<data>19</data>
</parameter>
<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
<data>0</data>
21,6 → 21,6
<data>0</data>
</parameter>
<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
<data>0</data>
<data>4</data>
</parameter>
</report_table>
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_combined_clk.rpt
5,15 → 5,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_notes.txt
2,6 → 2,7
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MT206 |Auto Constrain mode is enabled
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_resourceusage.rpt
1,17 → 1,22
Resource Usage Report
Part: lfe5u_45f-6
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 17
I/O cells: 19
 
Details:
FD1S3IX: 5
CCU2C: 5
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
OB: 15
IB: 3
IFS1P3JX: 1
INV: 2
OB: 16
ORCALUT4: 4
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_runstatus.xml
13,7 → 13,7
</job_status>
<job_info>
<info name="Notes">
<data>10</data>
<data>11</data>
<report_link name="more">
<data>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\impl1_fpga_mapper_notes.txt</data>
</report_link>
37,10 → 37,10
<data>0h:00m:01s</data>
</info>
<info name="Peak Memory">
<data>144MB</data>
<data>145MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1483829376</data>
<data type="timestamp">1484609380</data>
</info>
</job_info>
</job_run_status>
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_timing_report.xml
16,8 → 16,8
</row>
<row>
<data>DisplayDriverWrapper|clk</data>
<data>1297.0 MHz</data>
<data>1102.5 MHz</data>
<data>-0.136</data>
<data>433.9 MHz</data>
<data>368.8 MHz</data>
<data>-0.407</data>
</row>
</report_table>
/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_warnings.txt
1,8 → 16,8
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
/Lattice_FPGA_Build/impl1/synlog/report/impl1_premap_runstatus.xml
37,10 → 37,10
<data>0h:00m:00s</data>
</info>
<info name="Peak Memory">
<data>141MB</data>
<data>142MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1483829374</data>
<data type="timestamp">1484609378</data>
</info>
</job_info>
</job_run_status>
/Lattice_FPGA_Build/impl1/synlog/report/impl1_premap_warnings.txt
1,10 → 37,10
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_compiler.srr
8,27 → 8,42
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
35,7 → 50,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
@END
45,6 → 60,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.srr
30,6 → 30,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
59,12 → 60,22
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
 
3 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.64ns 1 / 9
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
 
73,15 → 84,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
91,7 → 102,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
98,21 → 109,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 13 00:54:42 2017
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1220.4 MHz
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
126,13 → 137,13
*******************
 
 
Worst slack in design: -0.145
Worst slack in design: -0.398
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
141,12 → 152,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
===========================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
160,7 → 171,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
 
 
168,37 → 179,38
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
 
 
 
207,128 → 219,179
 
 
Path information for path number 1:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
 
337,35 → 400,36
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
 
Details:
FD1S3IX: 5
FD1S3JX: 3
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:42 2017
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.srr_Min
1,12 → 1,12
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 13 00:54:42 2017
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1220.4 MHz
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
20,13 → 20,13
*******************
 
 
Worst slack in design: 0.379
Worst slack in design: 0.884
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
33,12 → 33,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.000 0.379 | No paths - | No paths - | No paths -
==========================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 0.000 0.884 | No paths - | No paths - | No paths -
================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
52,7 → 52,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
 
 
60,37 → 60,38
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.527 0.379
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.527 0.379
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.527 0.379
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.527 0.379
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.527 0.379
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.527 0.379
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.527 0.379
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.527 0.379
=============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.559 0.884
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.527 0.884
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.653 0.979
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.653 0.979
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.653 0.979
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.653 0.979
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.653 0.979
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.653 0.979
===============================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.148 0.379
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.148 0.379
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.148 0.379
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.148 0.379
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.148 0.379
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.148 0.379
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.148 0.379
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.148 0.379
==============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 0.148 0.884
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 0.148 0.884
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 0.148 0.884
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 0.148 0.979
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 0.148 0.979
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 0.148 0.979
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 0.148 0.979
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 0.148 0.979
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 0.148 0.979
=============================================================================================================================
 
 
 
99,26 → 100,29
 
 
Path information for path number 1:
Propagation time: 0.527
Propagation time: 1.032
+ Clock delay at starting point: 0.000 (ideal)
- Requested Period: 0.000
- Hold time: 0.148
- Clock delay at ending point: 0.000 (ideal)
= Slack (critical) : 0.379
= Slack (critical) : 0.884
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 1
Starting point: symbol_scan_cntr[7] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.527 0.527 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.527 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
symbol_scan_cntr[7] FD1S3DX Q Out 0.559 0.559 -
symbol_scan_cntr[7] Net - - - - 2
symbol_scan_cntr_s_0[7] CCU2C A0 In 0.000 0.559 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.473 1.032 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 1.032 -
=========================================================================================
 
 
 
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.xck
1,26 → 100,29
CKID0001:@|S:clk@|E:DDwD_Top.ascii_reg[6]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
CKID0001:@|S:button@|E:symbol_scan_cntr[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_multi_srs_gen.srr
7,6 → 7,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_premap.srr
16,10 → 16,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
33,13 → 33,13
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
55,6 → 55,6
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_premap.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synlog/impl1_compiler.srr
8,23 → 8,29
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
Options changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
@W: CL240 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":38:8:38:16|disp_data is not assigned a value (floating) -- simulation mismatch possible.
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
38,7 → 44,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
###########################################################]
@END
48,6 → 54,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.srr
30,6 → 30,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
46,7 → 47,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
59,13 → 60,21
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.62ns 7 / 13
 
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
73,15 → 82,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
91,7 → 100,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
98,21 → 107,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Sun Jan 08 00:49:36 2017
# Timing Report written on Tue Jan 17 01:29:40 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1297.0 MHz
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
126,13 → 135,13
*******************
 
 
Worst slack in design: -0.136
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
==================================================================================================================================
 
 
 
145,7 → 154,7
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.771 -0.136 | No paths - | No paths - | No paths -
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
168,37 → 177,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.853 -0.136
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.853 -0.136
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.853 -0.136
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.853 -0.136
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.853 -0.136
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.853 -0.136
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.853 -0.136
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.853 -0.136
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
===================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.717 -0.136
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.717 -0.136
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.717 -0.136
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.717 -0.136
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.717 -0.136
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.717 -0.136
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.717 -0.136
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.717 -0.136
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
================================================================================================================================
 
 
 
207,128 → 220,191
 
 
Path information for path number 1:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (critical) : -0.407
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.853 0.853 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.853 0.853 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.853 0.853 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.853 0.853 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.853 0.853 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
 
337,35 → 413,40
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5u_45f-6
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 17
I/O cells: 19
 
 
Details:
FD1S3IX: 5
CCU2C: 5
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
OB: 15
IB: 3
IFS1P3JX: 1
INV: 2
OB: 16
ORCALUT4: 4
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 08 00:49:36 2017
# Tue Jan 17 01:29:40 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.srr_Min
1,12 → 1,12
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Sun Jan 08 00:49:36 2017
# Timing Report written on Tue Jan 17 01:29:40 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1297.0 MHz
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
20,13 → 20,13
*******************
 
 
Worst slack in design: 0.559
Worst slack in design: 0.439
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
==================================================================================================================================
 
 
 
37,7 → 37,7
------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.000 0.559 | No paths - | No paths - | No paths -
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.000 0.439 | No paths - | No paths - | No paths -
==========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
60,37 → 60,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.597 0.559
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.597 0.559
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.597 0.559
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.597 0.559
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.597 0.559
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.597 0.559
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.597 0.559
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.597 0.559
=============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.587 0.439
bttn_state_fifo[2] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[2] 0.587 0.439
bttn_state_fifo_0io[0] DisplayDriverWrapper|clk IFS1P3JX Q bttn_state_fifo[0] 0.587 0.439
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[7] 0.559 0.884
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.653 0.979
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.653 0.979
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.653 0.979
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.653 0.979
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.653 0.979
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.653 0.979
======================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.038 0.559
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.038 0.559
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.038 0.559
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.038 0.559
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.038 0.559
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.038 0.559
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.038 0.559
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.038 0.559
==============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX D bttn_state_fifo[0] 0.148 0.439
bttn_state_fifo[2] DisplayDriverWrapper|clk FD1S3JX D bttn_state_fifo[1] 0.148 0.439
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX D bttn_state_fifo[2] 0.148 0.439
bttn_state DisplayDriverWrapper|clk FD1S3AX D bttn_stateand 0.148 0.679
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 0.148 0.884
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
===============================================================================================================================
 
 
 
99,26 → 103,26
 
 
Path information for path number 1:
Propagation time: 0.597
Propagation time: 0.587
+ Clock delay at starting point: 0.000 (ideal)
- Requested Period: 0.000
- Hold time: 0.038
- Hold time: 0.148
- Clock delay at ending point: 0.000 (ideal)
= Slack (critical) : 0.559
= Slack (critical) : 0.439
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
Starting point: bttn_state_fifo[1] / Q
Ending point: bttn_state_fifo[2] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.597 0.597 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.597 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
bttn_state_fifo[1] FD1S3JX Q Out 0.587 0.587 -
bttn_state_fifo[1] Net - - - - 3
bttn_state_fifo[2] FD1S3JX D In 0.000 0.587 -
====================================================================================
 
 
 
/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.xck
1,26 → 103,26
CKID0001:@|S:clk@|E:DDwD_Top.ascii_reg[6]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
CKID0001:@|S:clk@|E:bttn_state@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
/Lattice_FPGA_Build/impl1/synlog/impl1_multi_srs_gen.srr
9,6 → 9,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:34 2017
# Tue Jan 17 01:29:37 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/impl1_premap.srr
16,10 → 16,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
26,7 → 26,7
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
 
 
33,28 → 33,29
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
---------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=========================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
None
None
 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
Pre-mapping successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 08 00:49:34 2017
# Tue Jan 17 01:29:38 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/synlog/impl1_premap.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synlog/syntax_constraint_check.rpt.rptmap
1,28 → 33,29
./DisplayDriverwDecoder_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
./impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
/Lattice_FPGA_Build/impl1/syntmp/DisplayDriverwDecoder_impl1.plg
1,15 → 1,17
@P: Worst Slack : -0.145
@P: DisplayDriverWrapper|clk - Estimated Frequency : 1037.3 MHz
@P: DisplayDriverWrapper|clk - Requested Frequency : 1220.4 MHz
@P: DisplayDriverWrapper|clk - Estimated Period : 0.964
@P: DisplayDriverWrapper|clk - Requested Period : 0.819
@P: DisplayDriverWrapper|clk - Slack : -0.145
@P: Worst Slack(min analysis) : 0.379
@P: DisplayDriverWrapper|clk - Estimated Frequency(min analysis) : 1037.3 MHz
@P: DisplayDriverWrapper|clk - Requested Frequency(min analysis) : 1220.4 MHz
@P: DisplayDriverWrapper|clk - Estimated Period(min analysis) : 0.964
@P: DisplayDriverWrapper|clk - Requested Period(min analysis) : 0.819
@P: DisplayDriverWrapper|clk - Slack(min analysis) : -0.145
@P: Worst Slack : -0.398
@P: DisplayDriverWrapper|button - Estimated Frequency : 377.0 MHz
@P: DisplayDriverWrapper|button - Requested Frequency : 443.5 MHz
@P: DisplayDriverWrapper|button - Estimated Period : 2.652
@P: DisplayDriverWrapper|button - Requested Period : 2.255
@P: DisplayDriverWrapper|button - Slack : -0.398
@P: Worst Slack(min analysis) : 0.884
@P: DisplayDriverWrapper|button - Estimated Frequency(min analysis) : 377.0 MHz
@P: DisplayDriverWrapper|button - Requested Frequency(min analysis) : 443.5 MHz
@P: DisplayDriverWrapper|button - Estimated Period(min analysis) : 2.652
@P: DisplayDriverWrapper|button - Requested Period(min analysis) : 2.255
@P: DisplayDriverWrapper|button - Slack(min analysis) : -0.398
@P: Total Area : 1.0
@P: Total Area : 0.0
@P: Total Area : 0.0
@P: Total Area : 0.0
@P: CPU Time : 0h:00m:01s
/Lattice_FPGA_Build/impl1/syntmp/DisplayDriverwDecoder_impl1_srr.htm
1,45 → 1,60
<html><body><samp><pre>
<!@TC:1484261677>
<!@TC:1484608749>
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
#Implementation: impl1
 
<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484261677> | Running in 64-bit mode
@N: : <!@TM:1484608749> | Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484261677> | Running in 64-bit mode
@N: : <!@TM:1484608749> | Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484261677> | Setting time resolution to ns
@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484261677> | Top entity is set to DisplayDriverWrapper.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484608749> | Setting time resolution to ns
@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484608749> | Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484261677> | Synthesizing work.displaydriverwrapper.arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:38:11:38:16:@W:CD638:@XP_MSG">DisplayDriverWrapper.vhd(38)</a><!@TM:1484261677> | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1484261677> | Synthesizing work.displaydriverwdecoder_top.arch.
 
Compiler output is up to date. No re-compile necessary
 
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484608749> | Synthesizing work.displaydriverwrapper.arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:38:11:38:16:@W:CD638:@XP_MSG">DisplayDriverWrapper.vhd(38)</a><!@TM:1484608749> | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1484608749> | Synthesizing work.displaydriverwdecoder_top.arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:53:11:53:20:@W:CD638:@XP_MSG">DisplayDriverwDecoder_Top.vhd(53)</a><!@TM:1484608749> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:15:7:15:19:@N:CD630:@XP_MSG">ASCIIDecoder.vhd(15)</a><!@TM:1484608749> | Synthesizing work.asciidecoder.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd:12:7:12:26:@N:CD630:@XP_MSG">DistRomAsciiDecoder.vhd(12)</a><!@TM:1484608749> | Synthesizing work.distromasciidecoder.structure.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484608749> | Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:20:8:20:14:@N:CL159:@XP_MSG">DisplayDriverWrapper.vhd(20)</a><!@TM:1484261677> | Input button is unused.
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:54:4:54:6:@W:CL169:@XP_MSG">DisplayDriverWrapper.vhd(54)</a><!@TM:1484608749> | Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:54:4:54:6:@W:CL169:@XP_MSG">DisplayDriverWrapper.vhd(54)</a><!@TM:1484608749> | Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.</font>
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(17)</a><!@TM:1484608749> | Input clk is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(18)</a><!@TM:1484608749> | Input reset is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:29:8:29:13:@N:CL159:@XP_MSG">DisplayDriverwDecoder_Top.vhd(29)</a><!@TM:1484608749> | Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484261677> | Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
@N: : <!@TM:1484608749> | Running in 64-bit mode
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
46,7 → 61,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
@END
56,11 → 71,11
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484261679> | Running in 64-bit mode
@N: : <!@TM:1484608751> | Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
68,7 → 83,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Pre-mapping Report
79,11 → 94,11
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484261679> | No constraint file specified.
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484608751> | No constraint file specified.
Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt:@XP_FILE">DisplayDriverwDecoder_impl1_scck.rpt</a>
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484261679> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484261679> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484608751> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484608751> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
91,10 → 106,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
108,13 → 123,13
<a name=mapperReport6></a>Clock Summary</a>
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
 
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd:76:8:76:10:@W:MT529:@XP_MSG">displaydriverwdecoder_top.vhd(76)</a><!@TM:1484261679> | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:74:4:74:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(74)</a><!@TM:1484608751> | Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
 
Finished Pre Mapping Phase.
 
130,7 → 145,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Map & Optimize Report
141,8 → 156,8
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484261682> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484261682> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484608753> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484608753> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
163,10 → 178,11
Available hyper_sources - for debug and ip models
None Found
 
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484261682> | Auto Constrain mode is enabled
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484608753> | Auto Constrain mode is enabled
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:74:4:74:6:@N::@XP_MSG">displaydriverwrapper.vhd(74)</a><!@TM:1484608753> | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
196,12 → 212,22
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:74:4:74:6:@N:FX271:@XP_MSG">displaydriverwrapper.vhd(74)</a><!@TM:1484608753> | Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
 
3 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.64ns 1 / 9
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484261682> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484608753> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
 
210,15 → 236,15
 
<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
<a href="@|S:clk@|E:DDwD_Top.ascii_reg[6]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
<a href="@|S:button@|E:symbol_scan_cntr[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> button port 9 symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
228,34 → 254,34
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484261682> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484608753> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
L-2016.03L-1
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484261682> | Synplicity Constraint File capacitance units using default value of 1pF
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484608753> | Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484261682> | Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"</font>
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484608753> | Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"</font>
 
 
<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Fri Jan 13 00:54:42 2017
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1220.4 MHz
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484261682> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484608753> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484261682> | Clock constraints cover only FF-to-FF paths associated with the clock.
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484608753> | Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
263,13 → 289,13
*******************
 
 
Worst slack in design: -0.145
Worst slack in design: -0.398
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
278,12 → 304,12
<a name=clockRelationships11></a>Clock Relationships</a>
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
===========================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
297,7 → 323,7
 
 
====================================
<a name=clockReport13></a>Detailed Report for Clock: DisplayDriverWrapper|clk</a>
<a name=clockReport13></a>Detailed Report for Clock: DisplayDriverWrapper|button</a>
====================================
 
 
305,168 → 331,220
<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
 
 
<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
 
 
 
<a name=worstPaths16></a>Worst Path Information</a>
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srs:fp:20159:20426:@XP_NAMES_GATE">View Worst Path in Analyst</a>
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srs:fp:23288:24683:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************
 
 
Path information for path number 1:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
 
475,36 → 553,37
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
<a name=resourceUsage17></a>Resource Usage Report</a>
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
 
Details:
FD1S3IX: 5
FD1S3JX: 3
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:42 2017
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
 
###########################################################]
 
/Lattice_FPGA_Build/impl1/syntmp/DisplayDriverwDecoder_impl1_toc.htm
27,14 → 27,14
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a> </li>
<li><a href="file:///#" target="srrFrame" title="">Detailed Report for Clocks</a>
<ul >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#clockReport13" target="srrFrame" title="">Clock: DisplayDriverWrapper|clk</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#clockReport13" target="srrFrame" title="">Clock: DisplayDriverWrapper|button</a>
<ul >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (00:54 13-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (00:54 13-Jan)</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (01:19 17-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (01:19 17-Jan)</a>
<ul ></ul></li> </ul>
</li>
</ul>
/Lattice_FPGA_Build/impl1/syntmp/hdlorder.tcl
1,14 → 27,14
project -fileorder "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
project -fileorder "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
/Lattice_FPGA_Build/impl1/syntmp/impl1.plg
1,15 → 1,17
@P: Worst Slack : -0.136
@P: DisplayDriverWrapper|clk - Estimated Frequency : 1102.5 MHz
@P: DisplayDriverWrapper|clk - Requested Frequency : 1297.0 MHz
@P: DisplayDriverWrapper|clk - Estimated Period : 0.907
@P: DisplayDriverWrapper|clk - Requested Period : 0.771
@P: DisplayDriverWrapper|clk - Slack : -0.136
@P: Worst Slack(min analysis) : 0.559
@P: DisplayDriverWrapper|clk - Estimated Frequency(min analysis) : 1102.5 MHz
@P: DisplayDriverWrapper|clk - Requested Frequency(min analysis) : 1297.0 MHz
@P: DisplayDriverWrapper|clk - Estimated Period(min analysis) : 0.907
@P: DisplayDriverWrapper|clk - Requested Period(min analysis) : 0.771
@P: DisplayDriverWrapper|clk - Slack(min analysis) : -0.136
@P: Worst Slack : -0.407
@P: DisplayDriverWrapper|clk - Estimated Frequency : 368.8 MHz
@P: DisplayDriverWrapper|clk - Requested Frequency : 433.9 MHz
@P: DisplayDriverWrapper|clk - Estimated Period : 2.712
@P: DisplayDriverWrapper|clk - Requested Period : 2.305
@P: DisplayDriverWrapper|clk - Slack : -0.407
@P: Worst Slack(min analysis) : 0.439
@P: DisplayDriverWrapper|clk - Estimated Frequency(min analysis) : 368.8 MHz
@P: DisplayDriverWrapper|clk - Requested Frequency(min analysis) : 433.9 MHz
@P: DisplayDriverWrapper|clk - Estimated Period(min analysis) : 2.712
@P: DisplayDriverWrapper|clk - Requested Period(min analysis) : 2.305
@P: DisplayDriverWrapper|clk - Slack(min analysis) : -0.407
@P: Total Area : 6.0
@P: Total Area : 0.0
@P: Total Area : 0.0
@P: Total Area : 0.0
@P: CPU Time : 0h:00m:01s
/Lattice_FPGA_Build/impl1/syntmp/impl1_premap_warnings_txt_report.htm
0,0 → 1,5
<html><body><samp><pre>
<!@TC:0>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:54:4:54:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(54)</a><!@TM:0> | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
 
</pre></samp></body></html>
Lattice_FPGA_Build/impl1/syntmp/impl1_premap_warnings_txt_report.htm Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: Lattice_FPGA_Build/impl1/syntmp/impl1_srr.htm =================================================================== --- Lattice_FPGA_Build/impl1/syntmp/impl1_srr.htm (revision 5) +++ Lattice_FPGA_Build/impl1/syntmp/impl1_srr.htm (revision 6) @@ -1,48 +1,54 @@ 








    -








    +








    #Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016








    #install: C:\lscc\diamond\3.8_x64\synpbase








    #OS: Windows 8 6.2








    #Hostname: DESKTOP-1AUKF7V








    -# Sun Jan 08 00:49:32 2017








    +# Tue Jan 17 01:29:36 2017








     








     #Implementation: impl1








     








    -Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016








    -@N: :  | Running in 64-bit mode 








    +Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016








    +@N: :  | Running in 64-bit mode 








     Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.








     








    -Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016








    -@N: :  | Running in 64-bit mode 








    +Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016








    +@N: :  | Running in 64-bit mode 








     Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.








     








    -@N:CD720 : std.vhd(123) | Setting time resolution to ns








    -@N: : DisplayDriverWrapper.vhd(15) | Top entity is set to DisplayDriverWrapper.








    -File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling








    +@N:CD720 : std.vhd(123) | Setting time resolution to ns








    +@N: : DisplayDriverWrapper.vhd(15) | Top entity is set to DisplayDriverWrapper.








    +Options changed - recompiling








     VHDL syntax check successful!








    -File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling








    -@N:CD630 : DisplayDriverWrapper.vhd(15) | Synthesizing work.displaydriverwrapper.arch.








    -@W:CD638 : DisplayDriverWrapper.vhd(38) | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.








    -@N:CD630 : DisplayDriverwDecoder_Top.vhd(16) | Synthesizing work.displaydriverwdecoder_top.arch.








    +@N:CD630 : DisplayDriverWrapper.vhd(15) | Synthesizing work.displaydriverwrapper.arch.








    +@N:CD630 : DisplayDriverwDecoder_Top.vhd(16) | Synthesizing work.displaydriverwdecoder_top.arch.








    +@W:CD638 : DisplayDriverwDecoder_Top.vhd(53) | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.








    +@N:CD630 : ASCIIDecoder.vhd(15) | Synthesizing work.asciidecoder.arch.








    +@N:CD630 : DistRomAsciiDecoder.vhd(12) | Synthesizing work.distromasciidecoder.structure.








    +@N:CD630 : ecp5um.vhd(801) | Synthesizing work.rom128x1a.syn_black_box.








    +Post processing for work.rom128x1a.syn_black_box








    +Post processing for work.distromasciidecoder.structure








    +Post processing for work.asciidecoder.arch








     Post processing for work.displaydriverwdecoder_top.arch








    -@W:CL240 : DisplayDriverwDecoder_Top.vhd(38) | disp_data is not assigned a value (floating) -- simulation mismatch possible. 








     Post processing for work.displaydriverwrapper.arch








    -@N:CL159 : DisplayDriverWrapper.vhd(20) | Input button is unused.








    +@N:CL159 : ASCIIDecoder.vhd(17) | Input clk is unused.








    +@N:CL159 : ASCIIDecoder.vhd(18) | Input reset is unused.








    +@N:CL159 : DisplayDriverwDecoder_Top.vhd(29) | Input wr_en is unused.








     








    -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)








    +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)








     








     Process took 0h:00m:01s realtime, 0h:00m:01s cputime








     








     Process completed successfully.








    -# Sun Jan 08 00:49:32 2017








    +# Tue Jan 17 01:29:36 2017








     








     ###########################################################]








    -Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016








    -@N: :  | Running in 64-bit mode 








    +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016








    +@N: :  | Running in 64-bit mode 








     File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling








    -@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








    -@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








    +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








    +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








     








     At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)








     








    @@ -49,7 +55,7 @@








     Process took 0h:00m:01s realtime, 0h:00m:01s cputime








     








     Process completed successfully.








    -# Sun Jan 08 00:49:32 2017








    +# Tue Jan 17 01:29:36 2017








     








     ###########################################################]








     @END








    @@ -59,14 +65,14 @@








     Process took 0h:00m:01s realtime, 0h:00m:01s cputime








     








     Process completed successfully.








    -# Sun Jan 08 00:49:32 2017








    +# Tue Jan 17 01:29:36 2017








     








     ###########################################################]








    -Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016








    -@N: :  | Running in 64-bit mode 








    +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016








    +@N: :  | Running in 64-bit mode 








     File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling








    -@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








    -@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








    +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








    +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level








     








     At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)








     








    @@ -73,22 +79,22 @@








     Process took 0h:00m:01s realtime, 0h:00m:01s cputime








     








     Process completed successfully.








    -# Sun Jan 08 00:49:34 2017








    +# Tue Jan 17 01:29:37 2017








     








     ###########################################################]








     Pre-mapping Report








     








    -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31








    +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31








     Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.








     Product Version L-2016.03L-1








     








     Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)








     








    -@A:MF827 :  | No constraint file specified. 








    +@A:MF827 :  | No constraint file specified. 








     Linked File: impl1_scck.rpt








     Printing clock  summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file 








    -@N:MF248 :  | Running in 64-bit mode. 








    -@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 








    +@N:MF248 :  | Running in 64-bit mode. 








    +@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 








     








     Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)








     








    @@ -96,10 +102,10 @@








     Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)








     








     








    -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)








    +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)








     








     








    -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)








    +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)








     








     ICG Latch Removal Summary:








     Number of ICG latches removed:	0








    @@ -106,48 +112,49 @@








     Number of ICG latches not removed:	0








     syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper








     








    -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








    +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)








     








     








     








    -Clock Summary








    +Clock Summary








     *****************








     








    -Start                        Requested     Requested     Clock        Clock                     Clock








    -Clock                        Frequency     Period        Type         Group                     Load 








    ------------------------------------------------------------------------------------------------------








    -DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8    








    -=====================================================================================================








    +Start                                             Requested     Requested     Clock                                       Clock                     Clock








    +Clock                                             Frequency     Period        Type                                        Group                     Load 








    +---------------------------------------------------------------------------------------------------------------------------------------------------------








    +DisplayDriverWrapper|bttn_state_derived_clock     1.0 MHz       1000.000      derived (from DisplayDriverWrapper|clk)     Autoconstr_clkgroup_0     8    








    +DisplayDriverWrapper|clk                          1.0 MHz       1000.000      inferred                                    Autoconstr_clkgroup_0     5    








    +=========================================================================================================================================================








     








    -@W:MT529 : displaydriverwdecoder_top.vhd(75) | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 








    +@W:MT529 : displaydriverwrapper.vhd(57) | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 








     








     Finished Pre Mapping Phase.








     








    -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








    +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)








     








     None








     None








     








    -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








    +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)








     








     Pre-mapping successful!








     








    -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)








    +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)








     








     Process took 0h:00m:01s realtime, 0h:00m:01s cputime








    -# Sun Jan 08 00:49:34 2017








    +# Tue Jan 17 01:29:38 2017








     








     ###########################################################]








     Map & Optimize Report








     








    -Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31








    +Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31








     Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.








     Product Version L-2016.03L-1








     








     Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)








     








    -@N:MF248 :  | Running in 64-bit mode. 








    -@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 








    +@N:MF248 :  | Running in 64-bit mode. 








    +@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 








     








     Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)








     








    @@ -168,10 +175,11 @@








     Available hyper_sources - for debug and ip models








     	None Found








     








    -@N:MT206 :  | Auto Constrain mode is enabled 








    +@N:MT206 :  | Auto Constrain mode is enabled 








     








     Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








     








    +@N: : displaydriverwrapper.vhd(77) | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]








     








     Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








     








    @@ -188,7 +196,7 @@








     Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








     








     








    -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








    +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)








     








     








     Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








    @@ -201,29 +209,37 @@








     








     Pass		 CPU time		Worst Slack		Luts / Registers








     ------------------------------------------------------------








    +   1		0h:00m:00s		    -0.76ns		   6 /        13








    +   2		0h:00m:00s		    -0.76ns		   6 /        13








     








    +   3		0h:00m:00s		    -0.62ns		   7 /        13








    +








    +








    +   4		0h:00m:00s		    -0.58ns		   6 /        13








    +








     Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








     








    -@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   








    +@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   








     








    -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








    +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)








     








    +@N:MT611 :  | Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed 








     








     








     @S |Clock Optimization Summary








     








     








    -#### START OF CLOCK OPTIMIZATION REPORT #####[








    +#### START OF CLOCK OPTIMIZATION REPORT #####[








     








    -1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)








    +1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)








     0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)








    -0 instances converted, 0 sequential instances remain driven by gated/generated clocks








    +8 instances converted, 0 sequential instances remain driven by gated/generated clocks








     








    -============================== Non-Gated/Non-Generated Clocks ===============================








    -Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance      








    ----------------------------------------------------------------------------------------------








    -ClockId0001        clk                 port                   8          DDwD_Top.ascii_reg[6]








    -=============================================================================================








    +=========================== Non-Gated/Non-Generated Clocks ============================








    +Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance








    +---------------------------------------------------------------------------------------








    +ClockId0001        clk                 port                   13         bttn_state     








    +=======================================================================================








     








     








     ##### END OF CLOCK OPTIMIZATION REPORT ######]








    @@ -233,54 +249,54 @@








     








     Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm








     








    -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)








    +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)








     








     Writing EDIF Netlist and constraint files








    -@N:FX1056 :  | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi 








    +@N:FX1056 :  | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi 








     L-2016.03L-1








    -@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  








    +@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  








     








    -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)








    +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)








     








     








    -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)








    +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)








     








    -@W:MT420 :  | Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk" 








    +@W:MT420 :  | Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk" 








     








     








    -##### START OF TIMING REPORT #####[








    -# Timing Report written on Sun Jan 08 00:49:36 2017








    +##### START OF TIMING REPORT #####[








    +# Timing Report written on Tue Jan 17 01:29:40 2017








     #








     








     








     Top view:               DisplayDriverWrapper








    -Requested Frequency:    1297.0 MHz








    +Requested Frequency:    433.9 MHz








     Wire load mode:         top








     Paths requested:        5








     Constraint File(s):    








    -@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 








    +@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 








     








    -@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 








    +@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 








     








     








     








    -Performance Summary








    +Performance Summary








     *******************








     








     








    -Worst slack in design: -0.136








    +Worst slack in design: -0.407








     








    -                             Requested      Estimated      Requested     Estimated                Clock        Clock                








    -Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group                








    -------------------------------------------------------------------------------------------------------------------------------------








    -DisplayDriverWrapper|clk     1297.0 MHz     1102.5 MHz     0.771         0.907         -0.136     inferred     Autoconstr_clkgroup_0








    -====================================================================================================================================








    +                             Requested     Estimated     Requested     Estimated                Clock        Clock                








    +Starting Clock               Frequency     Frequency     Period        Period        Slack      Type         Group                








    +----------------------------------------------------------------------------------------------------------------------------------








    +DisplayDriverWrapper|clk     433.9 MHz     368.8 MHz     2.305         2.712         -0.407     inferred     Autoconstr_clkgroup_0








    +==================================================================================================================================








     








     








     








     








     








    -Clock Relationships








    +Clock Relationships








     *******************








     








     Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 








    @@ -287,7 +303,7 @@








     -------------------------------------------------------------------------------------------------------------------------------------------








     Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack








     -------------------------------------------------------------------------------------------------------------------------------------------








    -DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.771       -0.136  |  No paths    -      |  No paths    -      |  No paths    -    








    +DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  2.305       -0.407  |  No paths    -      |  No paths    -      |  No paths    -    








     ===========================================================================================================================================








      Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.








            'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.








    @@ -294,7 +310,7 @@








     








     








     








    -Interface Information 








    +Interface Information 








     *********************








     








     No IO constraint found








    @@ -302,176 +318,243 @@








     








     








     ====================================








    -Detailed Report for Clock: DisplayDriverWrapper|clk








    +Detailed Report for Clock: DisplayDriverWrapper|clk








     ====================================








     








     








     








    -Starting Points with Worst Slack








    +Starting Points with Worst Slack








     ********************************








     








    -                          Starting                                                          Arrival           








    -Instance                  Reference                    Type        Pin     Net              Time        Slack 








    -                          Clock                                                                               








    ---------------------------------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[0]     0.853       -0.136








    -DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.853       -0.136








    -DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[2]     0.853       -0.136








    -DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.853       -0.136








    -DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[4]     0.853       -0.136








    -DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.853       -0.136








    -DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.853       -0.136








    -DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.853       -0.136








    -==============================================================================================================








    +                        Starting                                                                 Arrival           








    +Instance                Reference                    Type        Pin     Net                     Time        Slack 








    +                        Clock                                                                                      








    +-------------------------------------------------------------------------------------------------------------------








    +symbol_scan_cntr[0]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[0]     0.933       -0.407








    +symbol_scan_cntr[1]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[1]     0.933       -0.348








    +symbol_scan_cntr[2]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[2]     0.933       -0.348








    +symbol_scan_cntr[3]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[3]     0.933       -0.289








    +symbol_scan_cntr[4]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[4]     0.933       -0.289








    +symbol_scan_cntr[5]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[5]     0.933       -0.230








    +symbol_scan_cntr[6]     DisplayDriverWrapper|clk     FD1P3DX     Q       symbol_scan_cntr[6]     0.933       -0.230








    +bttn_state_fifo[3]      DisplayDriverWrapper|clk     FD1S3JX     Q       bttn_state_fifo[3]      0.798       0.123 








    +bttn_state              DisplayDriverWrapper|clk     FD1S3AX     Q       bttn_state_i            0.753       0.168 








    +bttn_state_fifo[1]      DisplayDriverWrapper|clk     FD1S3JX     Q       bttn_state_fifo[1]      0.838       0.606 








    +===================================================================================================================








     








     








    -Ending Points with Worst Slack








    +Ending Points with Worst Slack








     ******************************








     








    -                          Starting                                                          Required           








    -Instance                  Reference                    Type        Pin     Net              Time         Slack 








    -                          Clock                                                                                








    ----------------------------------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.717        -0.136








    -DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.717        -0.136








    -DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.717        -0.136








    -DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[3]     0.717        -0.136








    -DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[4]     0.717        -0.136








    -DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.717        -0.136








    -DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.717        -0.136








    -DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.717        -0.136








    -===============================================================================================================








    +                        Starting                                                                             Required           








    +Instance                Reference                    Type        Pin     Net                                 Time         Slack 








    +                        Clock                                                                                                   








    +--------------------------------------------------------------------------------------------------------------------------------








    +symbol_scan_cntr[7]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[7]               2.094        -0.407








    +symbol_scan_cntr[5]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[5]               2.094        -0.348








    +symbol_scan_cntr[6]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[6]               2.094        -0.348








    +symbol_scan_cntr[3]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[3]               2.094        -0.289








    +symbol_scan_cntr[4]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[4]               2.094        -0.289








    +symbol_scan_cntr[1]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[1]               2.094        -0.230








    +symbol_scan_cntr[2]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[2]               2.094        -0.230








    +symbol_scan_cntr[0]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     2.122        0.123 








    +symbol_scan_cntr[1]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     2.122        0.123 








    +symbol_scan_cntr[2]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     2.122        0.123 








    +================================================================================================================================








     








     








     








    -Worst Path Information








    -View Worst Path in Analyst








    +Worst Path Information








    +View Worst Path in Analyst








     ***********************








     








     








     Path information for path number 1: 








    -      Requested Period:                      0.771








    -    - Setup time:                            0.054








    +      Requested Period:                      2.305








    +    - Setup time:                            0.211








         + Clock delay at ending point:           0.000 (ideal)








    -    = Required time:                         0.717








    +    = Required time:                         2.094








     








    -    - Propagation time:                      0.853








    +    - Propagation time:                      2.501








         - Clock delay at starting point:         0.000 (ideal)








    -    = Slack (critical) :                     -0.136








    +    = Slack (critical) :                     -0.407








     








    -    Number of logic level(s):                0








    -    Starting point:                          DDwD_Top.ascii_reg[0] / Q








    -    Ending point:                            DDwD_Top.ascii_reg[0] / D








    +    Number of logic level(s):                5








    +    Starting point:                          symbol_scan_cntr[0] / Q








    +    Ending point:                            symbol_scan_cntr[7] / D








         The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








         The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








     








    -Instance / Net                        Pin      Pin               Arrival     No. of    








    -Name                      Type        Name     Dir     Delay     Time        Fan Out(s)








    ----------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.853     0.853       -         








    -ascii_reg[0]              Net         -        -       -         -           1         








    -DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.853       -         








    -=======================================================================================








    +Instance / Net                            Pin      Pin               Arrival     No. of    








    +Name                          Type        Name     Dir     Delay     Time        Fan Out(s)








    +-------------------------------------------------------------------------------------------








    +symbol_scan_cntr[0]           FD1P3DX     Q        Out     0.933     0.933       -         








    +symbol_scan_cntr[0]           Net         -        -       -         -           15        








    +symbol_scan_cntr_cry_0[0]     CCU2C       A1       In      0.000     0.933       -         








    +symbol_scan_cntr_cry_0[0]     CCU2C       COUT     Out     0.784     1.717       -         








    +symbol_scan_cntr_cry[0]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[1]     CCU2C       CIN      In      0.000     1.717       -         








    +symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.059     1.776       -         








    +symbol_scan_cntr_cry[2]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.776       -         








    +symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.835       -         








    +symbol_scan_cntr_cry[4]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.835       -         








    +symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.894       -         








    +symbol_scan_cntr_cry[6]       Net         -        -       -         -           1         








    +symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.894       -         








    +symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.501       -         








    +symbol_scan_cntr_s[7]         Net         -        -       -         -           1         








    +symbol_scan_cntr[7]           FD1P3DX     D        In      0.000     2.501       -         








    +===========================================================================================








     








     








     Path information for path number 2: 








    -      Requested Period:                      0.771








    -    - Setup time:                            0.054








    +      Requested Period:                      2.305








    +    - Setup time:                            0.211








         + Clock delay at ending point:           0.000 (ideal)








    -    = Required time:                         0.717








    +    = Required time:                         2.094








     








    -    - Propagation time:                      0.853








    +    - Propagation time:                      2.442








         - Clock delay at starting point:         0.000 (ideal)








    -    = Slack (critical) :                     -0.136








    +    = Slack (non-critical) :                 -0.348








     








    -    Number of logic level(s):                0








    -    Starting point:                          DDwD_Top.ascii_reg[1] / Q








    -    Ending point:                            DDwD_Top.ascii_reg[1] / D








    +    Number of logic level(s):                4








    +    Starting point:                          symbol_scan_cntr[1] / Q








    +    Ending point:                            symbol_scan_cntr[7] / D








         The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








         The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








     








    -Instance / Net                        Pin      Pin               Arrival     No. of    








    -Name                      Type        Name     Dir     Delay     Time        Fan Out(s)








    ----------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[1]     FD1S3JX     Q        Out     0.853     0.853       -         








    -ascii_reg[1]              Net         -        -       -         -           1         








    -DDwD_Top.ascii_reg[1]     FD1S3JX     D        In      0.000     0.853       -         








    -=======================================================================================








    +Instance / Net                            Pin      Pin               Arrival     No. of    








    +Name                          Type        Name     Dir     Delay     Time        Fan Out(s)








    +-------------------------------------------------------------------------------------------








    +symbol_scan_cntr[1]           FD1P3DX     Q        Out     0.933     0.933       -         








    +symbol_scan_cntr[1]           Net         -        -       -         -           15        








    +symbol_scan_cntr_cry_0[1]     CCU2C       A0       In      0.000     0.933       -         








    +symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -         








    +symbol_scan_cntr_cry[2]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -         








    +symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -         








    +symbol_scan_cntr_cry[4]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -         








    +symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.835       -         








    +symbol_scan_cntr_cry[6]       Net         -        -       -         -           1         








    +symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.835       -         








    +symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.442       -         








    +symbol_scan_cntr_s[7]         Net         -        -       -         -           1         








    +symbol_scan_cntr[7]           FD1P3DX     D        In      0.000     2.442       -         








    +===========================================================================================








     








     








     Path information for path number 3: 








    -      Requested Period:                      0.771








    -    - Setup time:                            0.054








    +      Requested Period:                      2.305








    +    - Setup time:                            0.211








         + Clock delay at ending point:           0.000 (ideal)








    -    = Required time:                         0.717








    +    = Required time:                         2.094








     








    -    - Propagation time:                      0.853








    +    - Propagation time:                      2.442








         - Clock delay at starting point:         0.000 (ideal)








    -    = Slack (critical) :                     -0.136








    +    = Slack (non-critical) :                 -0.348








     








    -    Number of logic level(s):                0








    -    Starting point:                          DDwD_Top.ascii_reg[2] / Q








    -    Ending point:                            DDwD_Top.ascii_reg[2] / D








    +    Number of logic level(s):                4








    +    Starting point:                          symbol_scan_cntr[2] / Q








    +    Ending point:                            symbol_scan_cntr[7] / D








         The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








         The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








     








    -Instance / Net                        Pin      Pin               Arrival     No. of    








    -Name                      Type        Name     Dir     Delay     Time        Fan Out(s)








    ----------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[2]     FD1S3IX     Q        Out     0.853     0.853       -         








    -ascii_reg[2]              Net         -        -       -         -           1         








    -DDwD_Top.ascii_reg[2]     FD1S3IX     D        In      0.000     0.853       -         








    -=======================================================================================








    +Instance / Net                            Pin      Pin               Arrival     No. of    








    +Name                          Type        Name     Dir     Delay     Time        Fan Out(s)








    +-------------------------------------------------------------------------------------------








    +symbol_scan_cntr[2]           FD1P3DX     Q        Out     0.933     0.933       -         








    +symbol_scan_cntr[2]           Net         -        -       -         -           15        








    +symbol_scan_cntr_cry_0[1]     CCU2C       A1       In      0.000     0.933       -         








    +symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -         








    +symbol_scan_cntr_cry[2]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -         








    +symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -         








    +symbol_scan_cntr_cry[4]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -         








    +symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.835       -         








    +symbol_scan_cntr_cry[6]       Net         -        -       -         -           1         








    +symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.835       -         








    +symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.442       -         








    +symbol_scan_cntr_s[7]         Net         -        -       -         -           1         








    +symbol_scan_cntr[7]           FD1P3DX     D        In      0.000     2.442       -         








    +===========================================================================================








     








     








     Path information for path number 4: 








    -      Requested Period:                      0.771








    -    - Setup time:                            0.054








    +      Requested Period:                      2.305








    +    - Setup time:                            0.211








         + Clock delay at ending point:           0.000 (ideal)








    -    = Required time:                         0.717








    +    = Required time:                         2.094








     








    -    - Propagation time:                      0.853








    +    - Propagation time:                      2.442








         - Clock delay at starting point:         0.000 (ideal)








    -    = Slack (critical) :                     -0.136








    +    = Slack (non-critical) :                 -0.348








     








    -    Number of logic level(s):                0








    -    Starting point:                          DDwD_Top.ascii_reg[3] / Q








    -    Ending point:                            DDwD_Top.ascii_reg[3] / D








    +    Number of logic level(s):                4








    +    Starting point:                          symbol_scan_cntr[0] / Q








    +    Ending point:                            symbol_scan_cntr[5] / D








         The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








         The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








     








    -Instance / Net                        Pin      Pin               Arrival     No. of    








    -Name                      Type        Name     Dir     Delay     Time        Fan Out(s)








    ----------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[3]     FD1S3IX     Q        Out     0.853     0.853       -         








    -ascii_reg[3]              Net         -        -       -         -           1         








    -DDwD_Top.ascii_reg[3]     FD1S3IX     D        In      0.000     0.853       -         








    -=======================================================================================








    +Instance / Net                            Pin      Pin               Arrival     No. of    








    +Name                          Type        Name     Dir     Delay     Time        Fan Out(s)








    +-------------------------------------------------------------------------------------------








    +symbol_scan_cntr[0]           FD1P3DX     Q        Out     0.933     0.933       -         








    +symbol_scan_cntr[0]           Net         -        -       -         -           15        








    +symbol_scan_cntr_cry_0[0]     CCU2C       A1       In      0.000     0.933       -         








    +symbol_scan_cntr_cry_0[0]     CCU2C       COUT     Out     0.784     1.717       -         








    +symbol_scan_cntr_cry[0]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[1]     CCU2C       CIN      In      0.000     1.717       -         








    +symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.059     1.776       -         








    +symbol_scan_cntr_cry[2]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.776       -         








    +symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.835       -         








    +symbol_scan_cntr_cry[4]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.835       -         








    +symbol_scan_cntr_cry_0[5]     CCU2C       S0       Out     0.607     2.442       -         








    +symbol_scan_cntr_s[5]         Net         -        -       -         -           1         








    +symbol_scan_cntr[5]           FD1P3DX     D        In      0.000     2.442       -         








    +===========================================================================================








     








     








     Path information for path number 5: 








    -      Requested Period:                      0.771








    -    - Setup time:                            0.054








    +      Requested Period:                      2.305








    +    - Setup time:                            0.211








         + Clock delay at ending point:           0.000 (ideal)








    -    = Required time:                         0.717








    +    = Required time:                         2.094








     








    -    - Propagation time:                      0.853








    +    - Propagation time:                      2.442








         - Clock delay at starting point:         0.000 (ideal)








    -    = Slack (critical) :                     -0.136








    +    = Slack (non-critical) :                 -0.348








     








    -    Number of logic level(s):                0








    -    Starting point:                          DDwD_Top.ascii_reg[4] / Q








    -    Ending point:                            DDwD_Top.ascii_reg[4] / D








    +    Number of logic level(s):                4








    +    Starting point:                          symbol_scan_cntr[0] / Q








    +    Ending point:                            symbol_scan_cntr[6] / D








         The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








         The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK








     








    -Instance / Net                        Pin      Pin               Arrival     No. of    








    -Name                      Type        Name     Dir     Delay     Time        Fan Out(s)








    ----------------------------------------------------------------------------------------








    -DDwD_Top.ascii_reg[4]     FD1S3JX     Q        Out     0.853     0.853       -         








    -ascii_reg[4]              Net         -        -       -         -           1         








    -DDwD_Top.ascii_reg[4]     FD1S3JX     D        In      0.000     0.853       -         








    -=======================================================================================








    +Instance / Net                            Pin      Pin               Arrival     No. of    








    +Name                          Type        Name     Dir     Delay     Time        Fan Out(s)








    +-------------------------------------------------------------------------------------------








    +symbol_scan_cntr[0]           FD1P3DX     Q        Out     0.933     0.933       -         








    +symbol_scan_cntr[0]           Net         -        -       -         -           15        








    +symbol_scan_cntr_cry_0[0]     CCU2C       A1       In      0.000     0.933       -         








    +symbol_scan_cntr_cry_0[0]     CCU2C       COUT     Out     0.784     1.717       -         








    +symbol_scan_cntr_cry[0]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[1]     CCU2C       CIN      In      0.000     1.717       -         








    +symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.059     1.776       -         








    +symbol_scan_cntr_cry[2]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.776       -         








    +symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.835       -         








    +symbol_scan_cntr_cry[4]       Net         -        -       -         -           1         








    +symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.835       -         








    +symbol_scan_cntr_cry_0[5]     CCU2C       S1       Out     0.607     2.442       -         








    +symbol_scan_cntr_s[6]         Net         -        -       -         -           1         








    +symbol_scan_cntr[6]           FD1P3DX     D        In      0.000     2.442       -         








    +===========================================================================================








     








     








     








    @@ -480,36 +563,41 @@








     Constraints that could not be applied








     None








     








    -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)








    +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)








     








     








    -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)








    +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)








     








     ---------------------------------------








    -Resource Usage Report








    -Part: lfe5u_45f-6








    +Resource Usage Report








    +Part: lfe5um5g_45f-8








     








    -Register bits: 8 of 43848 (0%)








    +Register bits: 13 of 43848 (0%)








     PIC Latch:       0








    -I/O cells:       17








    +I/O cells:       19








     








     








     Details:








    -FD1S3IX:        5








    +CCU2C:          5








    +FD1P3DX:        8








    +FD1S3AX:        1








     FD1S3JX:        3








     GSR:            1








    -IB:             2








    -OB:             15








    +IB:             3








    +IFS1P3JX:       1








    +INV:            2








    +OB:             16








    +ORCALUT4:       4








     PUR:            1








    -VHI:            2








    +ROM128X1A:      14








    +VHI:            1








     VLO:            1








    -false:          1








     Mapper successful!








     








    -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)








    +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)








     








     Process took 0h:00m:01s realtime, 0h:00m:01s cputime








    -# Sun Jan 08 00:49:36 2017








    +# Tue Jan 17 01:29:40 2017








     








     ###########################################################]
/Lattice_FPGA_Build/impl1/syntmp/impl1_toc.htm
12,29 → 12,29
 
<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
<ul rel="open">
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#compilerReport14" target="srrFrame" title="">Compiler Report</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#compilerReport16" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#mapperReport18" target="srrFrame" title="">Pre-mapping Report</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#compilerReport9" target="srrFrame" title="">Compiler Report</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#compilerReport11" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#mapperReport13" target="srrFrame" title="">Pre-mapping Report</a>
<ul rel="open" >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#mapperReport19" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#mapperReport20" target="srrFrame" title="">Mapper Report</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#mapperReport14" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#mapperReport15" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#clockReport21" target="srrFrame" title="">Clock Conversion</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#timingReport22" target="srrFrame" title="">Timing Report</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#clockReport16" target="srrFrame" title="">Clock Conversion</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#timingReport17" target="srrFrame" title="">Timing Report</a>
<ul rel="open" >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#performanceSummary23" target="srrFrame" title="">Performance Summary</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#clockRelationships24" target="srrFrame" title="">Clock Relationships</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#interfaceInfo25" target="srrFrame" title="">Interface Information</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#performanceSummary18" target="srrFrame" title="">Performance Summary</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#clockRelationships19" target="srrFrame" title="">Clock Relationships</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#interfaceInfo20" target="srrFrame" title="">Interface Information</a> </li>
<li><a href="file:///#" target="srrFrame" title="">Detailed Report for Clocks</a>
<ul >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#clockReport26" target="srrFrame" title="">Clock: DisplayDriverWrapper|clk</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#clockReport21" target="srrFrame" title="">Clock: DisplayDriverWrapper|clk</a>
<ul >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#startingSlack27" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#endingSlack28" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#worstPaths29" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#resourceUsage30" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (00:49 08-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (00:48 08-Jan)</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#startingSlack22" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#endingSlack23" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#worstPaths24" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#resourceUsage25" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (01:29 17-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (01:28 17-Jan)</a>
<ul ></ul></li> </ul>
</li>
</ul>
/Lattice_FPGA_Build/impl1/syntmp/run_option.xml
6,13 → 6,13
 
-->
<project_attribute_list name="Project Settings">
<option name="project_name" display_name="Project Name">proj_1</option>
<option name="project_name" display_name="Project Name">impl1_syn</option>
<option name="impl_name" display_name="Implementation Name">impl1</option>
<option name="top_module" display_name="Top Module">DisplayDriverWrapper</option>
<option name="top_module" display_name="Top Module"></option>
<option name="pipe" display_name="Pipelining">1</option>
<option name="retiming" display_name="Retiming">0</option>
<option name="resource_sharing" display_name="Resource Sharing">1</option>
<option name="maxfan" display_name="Fanout Guide">1000</option>
<option name="maxfan" display_name="Fanout Guide">100</option>
<option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option>
<option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
<option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
/Lattice_FPGA_Build/impl1/syntmp/statusReport.html
9,11 → 9,11
<table style="border:none;" width="100%" ><tr> <td class="outline">
<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> proj_1</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> impl1</td> </tr>
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> impl1_syn</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> impl1</td> </tr>
</thead>
<tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> DisplayDriverWrapper</td> <td class="optionTitle" align="left"> Pipelining</td> <td> 1</td> </tr>
<tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> [auto]</td> <td class="optionTitle" align="left"> Pipelining</td> <td> 1</td> </tr>
<tr> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 1000</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> </tr>
<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 100</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> </tr>
<tr> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> </tr>
</tbody>
33,13 → 33,13
</tr>
<tr>
<td class="optionTitle"> (compiler)</td><td>Complete</td>
<td>8</td>
<td>15</td>
<td>1</td>
<td>0</td>
<td>-</td>
<td>0m:00s</td>
<td>-</td>
<td><font size="-1">13-Jan-17</font><br/><font size="-2">00:54:37</font></td>
<td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:36</font></td>
</tr>
 
<tr>
49,24 → 49,24
<td>0</td>
<td>0m:00s</td>
<td>0m:00s</td>
<td>141MB</td>
<td><font size="-1">13-Jan-17</font><br/><font size="-2">00:54:39</font></td>
<td>142MB</td>
<td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:38</font></td>
</tr>
 
<tr>
<td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
<td>10</td>
<td>11</td>
<td>1</td>
<td>0</td>
<td>0m:01s</td>
<td>0m:02s</td>
<td>144MB</td>
<td><font size="-1">13-Jan-17</font><br/><font size="-2">00:54:42</font></td>
<td>0m:01s</td>
<td>145MB</td>
<td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:40</font></td>
</tr>
 
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">13-Jan-17</font><br/><font size="-2">00:54:39</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:37</font></td> </tbody>
</table>
<br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0">
74,8 → 74,8
<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
</tfoot>
<tbody> <tr>
<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>8</td>
<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>18</td>
<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>13</td>
<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>19</td>
</tr>
<tr>
<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
85,7 → 85,7
</tr>
<tr>
<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
(total_luts)</td> <td>0</td>
(total_luts)</td> <td>4</td>
<td class="optionTitle"></td><td></td></tr>
</tbody>
</table><br>
95,7 → 95,7
</tfoot>
<tbody>
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
<tr> <td align="left">DisplayDriverWrapper|clk</td><td align="left">1220.4 MHz</td><td align="left">1037.3 MHz</td><td align="left">-0.145</td></tr>
<tr> <td align="left">DisplayDriverWrapper|clk</td><td align="left">433.9 MHz</td><td align="left">368.8 MHz</td><td align="left">-0.407</td></tr>
</tbody>
</table>
<br>
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_m_srm/1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_mult_srs/1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_mult_srs/skeleton.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_m_srm/1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_mult_srs/1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_mult_srs/skeleton.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/.cckTransfer Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/.complist
0,0 → 1,2
 
: 0 work.DisplayDriverWrapper "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" 15 7 work.DisplayDriverwDecoder_Top
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_comp.fdep
1,4 → 1,4
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
10,21 → 10,34
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484261649
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484258882
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\lucent\\ecp5um.vhd":1467795226
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484608465
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
#Dependency Lists(Uses List)
0 -1
1 -1
1 0
2 1
3 2
4 3
#Dependency Lists(Users Of)
0 -1
0 1
1 2
2 -1
2 3
3 4
4 -1
#Design Unit to File Association
module work displaydriverwrapper 2
arch work displaydriverwrapper arch 2
module work displaydriverwdecoder_top 1
arch work displaydriverwdecoder_top arch 1
module work displaydriverwrapper 4
arch work displaydriverwrapper arch 4
module work displaydriverwdecoder_top 3
arch work displaydriverwdecoder_top arch 3
module work asciidecoder 2
arch work asciidecoder arch 2
module work distromasciidecoder 1
arch work distromasciidecoder structure 1
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_comp.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_hdl_.fdeporig
1,5 → 1,5
#defaultlanguage:vhdl
#OPTIONS:"|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-fileorder|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\syntmp\\hdlorder.tcl"
#OPTIONS:"|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-fileorder|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\syntmp\\hdlorder.tcl"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
11,21 → 11,29
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484261649
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484258882
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609246
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
 
# Dependency Lists (Uses list)
0 -1
1 -1
1 3
2 1
3 4
4 0
 
# Dependency Lists (Users Of)
0 -1
0 4
1 2
2 -1
3 1
4 3
 
# Design Unit to File Association
arch work displaydriverwdecoder_top arch 1
32,3 → 40,7
module work displaydriverwdecoder_top 1
arch work displaydriverwrapper arch 2
module work displaydriverwrapper 2
arch work asciidecoder arch 3
module work asciidecoder 3
arch work distromasciidecoder structure 4
module work distromasciidecoder 4
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_m.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_mult.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_prem.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_comp.fdep
1,4 → 1,4
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\impl1_comp.srs|-autotop|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\impl1_comp.srs|-autotop|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
9,21 → 9,34
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\arith.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5u.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1483829366
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1483829076
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5u.vhd" vhdl
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\lucent\\ecp5um.vhd":1467795226
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609359
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
#Dependency Lists(Uses List)
0 -1
1 -1
1 3
2 1
3 4
4 0
#Dependency Lists(Users Of)
0 -1
0 4
1 2
2 -1
3 1
4 3
#Design Unit to File Association
module work distromasciidecoder 4
arch work distromasciidecoder structure 4
module work asciidecoder 3
arch work asciidecoder arch 3
module work displaydriverwrapper 2
arch work displaydriverwrapper arch 2
module work displaydriverwdecoder_top 1
/Lattice_FPGA_Build/impl1/synwork/impl1_comp.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_m.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_mult.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/impl1_prem.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/layer0.fdep
1,5 → 1,5
#defaultlanguage:vhdl
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\impl1_comp.srs|-autotop|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
11,21 → 11,30
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484261649
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484258882
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\lucent\\ecp5um.vhd":1467795226
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609359
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
 
# Dependency Lists (Uses list)
0 -1
1 -1
1 3
2 1
3 4
4 0
 
# Dependency Lists (Users Of)
0 -1
0 4
1 2
2 -1
3 1
4 3
 
# Design Unit to File Association
arch work displaydriverwdecoder_top arch 1
32,6 → 41,10
module work displaydriverwdecoder_top 1
arch work displaydriverwrapper arch 2
module work displaydriverwrapper 2
arch work asciidecoder arch 3
module work asciidecoder 3
arch work distromasciidecoder structure 4
module work distromasciidecoder 4
 
 
# Configuration files used
/Lattice_FPGA_Build/impl1/synwork/layer0.fdeporig
1,5 → 1,5
#defaultlanguage:vhdl
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\impl1_comp.srs|-autotop|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
11,21 → 11,29
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484261649
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484258882
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609359
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
 
# Dependency Lists (Uses list)
0 -1
1 -1
1 3
2 1
3 4
4 0
 
# Dependency Lists (Users Of)
0 -1
0 4
1 2
2 -1
3 1
4 3
 
# Design Unit to File Association
arch work displaydriverwdecoder_top arch 1
32,3 → 40,7
module work displaydriverwdecoder_top 1
arch work displaydriverwrapper arch 2
module work displaydriverwrapper 2
arch work asciidecoder arch 3
module work asciidecoder 3
arch work distromasciidecoder structure 4
module work distromasciidecoder 4
/Lattice_FPGA_Build/impl1/synwork/layer0.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/synwork/layer0.tlg
1,6 → 1,14
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
/Lattice_FPGA_Build/impl1/.build_status
6,38 → 6,38
<Task name="IBIS_AMI" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1484261708"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1484609837"/>
<Task name="Promgen" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1484261689">
<Task name="Map" build_result="2" update_result="0" update_time="1484261689"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1484261692"/>
<Milestone name="Map" build_result="2" build_time="1484609799">
<Task name="Map" build_result="2" update_result="0" update_time="1484609799"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1484609802"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1484261699">
<Task name="PAR" build_result="2" update_result="0" update_time="1484261699"/>
<Milestone name="PAR" build_result="2" build_time="1484609829">
<Task name="PAR" build_result="2" update_result="0" update_time="1484609829"/>
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1484261687">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1484261687"/>
<Milestone name="Synthesis" build_result="2" build_time="1484609379">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1484609379"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="2" update_time="1484257142"/>
<Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Translate" build_result="2" build_time="1484261688">
<Task name="Translate" build_result="2" update_result="0" update_time="1484261688"/>
<Milestone name="Translate" build_result="2" build_time="1484609390">
<Task name="Translate" build_result="2" update_result="0" update_time="1484609390"/>
</Milestone>
<Report name="DisplayDriverwDecoder_impl1.bgn" last_build_time="1484261708" last_build_size="4540"/>
<Report name="DisplayDriverwDecoder_impl1.bit" last_build_time="1484261708" last_build_size="1032647"/>
<Report name="DisplayDriverwDecoder_impl1.edi" last_build_time="1484261681" last_build_size="13174"/>
<Report name="DisplayDriverwDecoder_impl1.bgn" last_build_time="1484609837" last_build_size="4457"/>
<Report name="DisplayDriverwDecoder_impl1.bit" last_build_time="1484609837" last_build_size="1032647"/>
<Report name="DisplayDriverwDecoder_impl1.edi" last_build_time="1484609379" last_build_size="51257"/>
<Report name="DisplayDriverwDecoder_impl1.lsedata" last_build_time="1483827599" last_build_size="1943"/>
<Report name="DisplayDriverwDecoder_impl1.ncd" last_build_time="1484261699" last_build_size="9754"/>
<Report name="DisplayDriverwDecoder_impl1.ngd" last_build_time="1484261687" last_build_size="14765"/>
<Report name="DisplayDriverwDecoder_impl1.tw1" last_build_time="1484261692" last_build_size="3316"/>
<Report name="DisplayDriverwDecoder_impl1_map.ncd" last_build_time="1484261689" last_build_size="9754"/>
<Report name="DisplayDriverwDecoder_impl1.ncd" last_build_time="1484609829" last_build_size="132097"/>
<Report name="DisplayDriverwDecoder_impl1.ngd" last_build_time="1484609390" last_build_size="42226"/>
<Report name="DisplayDriverwDecoder_impl1.tw1" last_build_time="1484609802" last_build_size="8444"/>
<Report name="DisplayDriverwDecoder_impl1_map.ncd" last_build_time="1484609799" last_build_size="90131"/>
</Strategy>
</BuildStatus>
/Lattice_FPGA_Build/impl1/AutoConstraint_DisplayDriverWrapper.sdc
1,4 → 1,4
 
#Begin clock constraint
define_clock -name {DisplayDriverWrapper|clk} {p:DisplayDriverWrapper|clk} -period 0.819 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 0.410 -route 0.000
define_clock -name {DisplayDriverWrapper|clk} {p:DisplayDriverWrapper|clk} -period 2.305 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.152 -route 0.000
#End clock constraint
/Lattice_FPGA_Build/impl1/AutoConstraint_DisplayDriverwDecoder_Top.sdc --- Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.alt (revision 5) +++ Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.alt (revision 6) @@ -1,10 +1,11 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Fri Jan 13 00:55:08 2017 * +NOTE DATE CREATED: Tue Jan 17 01:37:17 2017 * NOTE DESIGN NAME: DisplayDriverWrapper * NOTE DEVICE NAME: LFE5UM5G-45F-8CABGA381 * NOTE PIN ASSIGNMENTS * NOTE PINS disp_data[0] : M20 : out * +NOTE PINS clk : P3 : in * NOTE PINS disp_sel : J1 : out * NOTE PINS disp_data[14] : U1 : out * NOTE PINS disp_data[13] : R16 : out * @@ -20,5 +21,7 @@ NOTE PINS disp_data[3] : L16 : out * NOTE PINS disp_data[2] : M19 : out * NOTE PINS disp_data[1] : L18 : out * +NOTE PINS button : T1 : in * +NOTE PINS n_rst : K20 : in * NOTE CONFIGURATION MODE: JTAG * NOTE COMPRESSION: off *
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.areasrr
1,30 → 1,57
----------------------------------------------------------------------
Report for cell DisplayDriverWrapper.arch
 
Register bits: 8 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
I/O cells: 19
Cell usage:
cell count Res Usage(%)
FD1S3IX 5 100.0
CCU2C 5 100.0
FD1P3DX 8 100.0
FD1S3AX 1 100.0
FD1S3JX 3 100.0
GSR 1 100.0
IB 2 100.0
IB 3 100.0
IFS1P3JX 1 100.0
INV 2 100.0
OB 16 100.0
ORCALUT4 4 100.0
PUR 1 100.0
VHI 2 100.0
ROM128X1A 14 100.0
VHI 1 100.0
VLO 1 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DisplayDriverwDecoder_Top 1 100.0
DistRomAsciiDecoder 1 100.0
TOTAL 32
TOTAL 64
----------------------------------------------------------------------
Report for cell DisplayDriverwDecoder_Top.netlist
Instance path: DDwD_Top
Cell usage:
cell count Res Usage(%)
FD1S3IX 5 100.0
FD1S3JX 3 100.0
VHI 1 50.0
ROM128X1A 14 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DistRomAsciiDecoder 1 100.0
TOTAL 9
TOTAL 16
----------------------------------------------------------------------
Report for cell ASCIIDecoder.netlist
Instance path: DDwD_Top.ascii_decoder_module
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
SUB MODULES
DistRomAsciiDecoder 1 100.0
TOTAL 15
----------------------------------------------------------------------
Report for cell DistRomAsciiDecoder.netlist
Instance path: DDwD_Top.ascii_decoder_module.rom_decoding_table
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
TOTAL 14
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bgn
19,8 → 19,7
Performance Hardware Data Status: Final Version 50.1.
 
Running DRC.
WARNING - netcheck: Design is completely unrouted. 0 warnings not reported below.
DRC detected 0 errors and 1 warnings.
DRC detected 0 errors and 0 warnings.
Reading Preference File from DisplayDriverwDecoder_impl1.prf.
 
Preference Summary:
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.drc
1,2 → 1,7
WARNING - netcheck: Design is completely unrouted. 0 warnings not reported below.
DRC detected 0 errors and 1 warnings.
DRC detected 0 errors and 0 warnings.
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.edi
4,7 → 4,7
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2017 1 13 0 54 41)
(timeStamp 2017 1 17 1 29 39)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "L-2016.03L-1, mapper maplat, Build 1498R"))
)
12,6 → 12,42
(library LUCENT
(edifLevel 0)
(technology (numberDefinition ))
(cell ROM128X1A (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port AD0 (direction INPUT))
(port AD1 (direction INPUT))
(port AD2 (direction INPUT))
(port AD3 (direction INPUT))
(port AD4 (direction INPUT))
(port AD5 (direction INPUT))
(port AD6 (direction INPUT))
(port DO0 (direction OUTPUT))
)
)
)
(cell CCU2C (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port A0 (direction INPUT))
(port B0 (direction INPUT))
(port C0 (direction INPUT))
(port D0 (direction INPUT))
(port A1 (direction INPUT))
(port B1 (direction INPUT))
(port C1 (direction INPUT))
(port D1 (direction INPUT))
(port CIN (direction INPUT))
(port COUT (direction OUTPUT))
(port S0 (direction OUTPUT))
(port S1 (direction OUTPUT))
)
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0000"))
(property INIT0 (string "0000"))
)
)
(cell OB (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
38,16 → 74,48
)
)
)
(cell FD1S3IX (cellType GENERIC)
(cell FD1S3AX (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port D (direction INPUT))
(port CK (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell IFS1P3JX (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port D (direction INPUT))
(port SP (direction INPUT))
(port SCLK (direction INPUT))
(port PD (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FD1P3DX (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port D (direction INPUT))
(port SP (direction INPUT))
(port CK (direction INPUT))
(port CD (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell ORCALUT4 (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port C (direction INPUT))
(port D (direction INPUT))
(port Z (direction OUTPUT))
)
)
)
(cell GSR (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
55,6 → 123,14
)
)
)
(cell INV (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port A (direction INPUT))
(port Z (direction OUTPUT))
)
)
)
(cell VHI (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
73,85 → 149,426
(library work
(edifLevel 0)
(technology (numberDefinition ))
(cell DisplayDriverwDecoder_Top (cellType GENERIC)
(cell DistRomAsciiDecoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port clk_c (direction INPUT))
(port rst_c (direction INPUT))
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance (rename ascii_reg_0 "ascii_reg[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_13 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xDA3FFFFFBA3FFFFFB7FE6997BFFFFFFE"))
)
(instance (rename ascii_reg_1 "ascii_reg[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
(instance mem_0_12 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xEDEFFDEBFDEFFDEB7BFFB3E718FFD7FF"))
)
(instance (rename ascii_reg_2 "ascii_reg[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_11 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xF679B7FFEE79B7FFEFDFFA97BFFFFFDF"))
)
(instance (rename ascii_reg_3 "ascii_reg[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_10 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xF0BFD7FFB8BFD7FFEFFE7A176DFFFFFE"))
)
(instance (rename ascii_reg_4 "ascii_reg[4]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
(instance mem_0_9 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xEFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF"))
)
(instance (rename ascii_reg_5 "ascii_reg[5]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_8 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xDCFF9FFEECFF9FFFBFFFF9976DFFFFFF"))
)
(instance (rename ascii_reg_6 "ascii_reg[6]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
(instance mem_0_7 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x9FF2FE59FFF2FE585CA3D3C7D0FFB0A3"))
)
(instance (rename ascii_reg_7 "ascii_reg[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_6 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xB7F2F69DFFF2F69DDC8B93C7D0FF388B"))
)
(instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
(net (rename ascii_reg_0 "ascii_reg[0]") (joined
(portRef Q (instanceRef ascii_reg_0))
(portRef D (instanceRef ascii_reg_0))
(instance mem_0_5 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7F100615F7100614FC8EFFC3E3FF288E"))
)
(instance mem_0_4 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x3F180215F7180214FEBABFF7EBFF2ABA"))
)
(instance mem_0_3 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7BD56B4353D56B42DC92BFA7DAFF8492"))
)
(instance mem_0_2 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7F551A69DF551A69FC24FF85FFFFD024"))
)
(instance mem_0_1 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x3F581AE99F581AE87C60FFF5F7FFD060"))
)
(instance mem_0_0 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7BE07F0193E07F007C12FFA7F2FF0012"))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
(portRef AD0 (instanceRef mem_0_0))
(portRef AD0 (instanceRef mem_0_1))
(portRef AD0 (instanceRef mem_0_2))
(portRef AD0 (instanceRef mem_0_3))
(portRef AD0 (instanceRef mem_0_4))
(portRef AD0 (instanceRef mem_0_5))
(portRef AD0 (instanceRef mem_0_6))
(portRef AD0 (instanceRef mem_0_7))
(portRef AD0 (instanceRef mem_0_8))
(portRef AD0 (instanceRef mem_0_9))
(portRef AD0 (instanceRef mem_0_10))
(portRef AD0 (instanceRef mem_0_11))
(portRef AD0 (instanceRef mem_0_12))
(portRef AD0 (instanceRef mem_0_13))
))
(net clk_c (joined
(portRef clk_c)
(portRef CK (instanceRef ascii_reg_7))
(portRef CK (instanceRef ascii_reg_6))
(portRef CK (instanceRef ascii_reg_5))
(portRef CK (instanceRef ascii_reg_4))
(portRef CK (instanceRef ascii_reg_3))
(portRef CK (instanceRef ascii_reg_2))
(portRef CK (instanceRef ascii_reg_1))
(portRef CK (instanceRef ascii_reg_0))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef (member symbol_scan_cntr 5))
(portRef AD1 (instanceRef mem_0_0))
(portRef AD1 (instanceRef mem_0_1))
(portRef AD1 (instanceRef mem_0_2))
(portRef AD1 (instanceRef mem_0_3))
(portRef AD1 (instanceRef mem_0_4))
(portRef AD1 (instanceRef mem_0_5))
(portRef AD1 (instanceRef mem_0_6))
(portRef AD1 (instanceRef mem_0_7))
(portRef AD1 (instanceRef mem_0_8))
(portRef AD1 (instanceRef mem_0_9))
(portRef AD1 (instanceRef mem_0_10))
(portRef AD1 (instanceRef mem_0_11))
(portRef AD1 (instanceRef mem_0_12))
(portRef AD1 (instanceRef mem_0_13))
))
(net rst_c (joined
(portRef rst_c)
(portRef CD (instanceRef ascii_reg_7))
(portRef PD (instanceRef ascii_reg_6))
(portRef CD (instanceRef ascii_reg_5))
(portRef PD (instanceRef ascii_reg_4))
(portRef CD (instanceRef ascii_reg_3))
(portRef CD (instanceRef ascii_reg_2))
(portRef PD (instanceRef ascii_reg_1))
(portRef CD (instanceRef ascii_reg_0))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef (member symbol_scan_cntr 4))
(portRef AD2 (instanceRef mem_0_0))
(portRef AD2 (instanceRef mem_0_1))
(portRef AD2 (instanceRef mem_0_2))
(portRef AD2 (instanceRef mem_0_3))
(portRef AD2 (instanceRef mem_0_4))
(portRef AD2 (instanceRef mem_0_5))
(portRef AD2 (instanceRef mem_0_6))
(portRef AD2 (instanceRef mem_0_7))
(portRef AD2 (instanceRef mem_0_8))
(portRef AD2 (instanceRef mem_0_9))
(portRef AD2 (instanceRef mem_0_10))
(portRef AD2 (instanceRef mem_0_11))
(portRef AD2 (instanceRef mem_0_12))
(portRef AD2 (instanceRef mem_0_13))
))
(net (rename ascii_reg_1 "ascii_reg[1]") (joined
(portRef Q (instanceRef ascii_reg_1))
(portRef D (instanceRef ascii_reg_1))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef (member symbol_scan_cntr 3))
(portRef AD3 (instanceRef mem_0_0))
(portRef AD3 (instanceRef mem_0_1))
(portRef AD3 (instanceRef mem_0_2))
(portRef AD3 (instanceRef mem_0_3))
(portRef AD3 (instanceRef mem_0_4))
(portRef AD3 (instanceRef mem_0_5))
(portRef AD3 (instanceRef mem_0_6))
(portRef AD3 (instanceRef mem_0_7))
(portRef AD3 (instanceRef mem_0_8))
(portRef AD3 (instanceRef mem_0_9))
(portRef AD3 (instanceRef mem_0_10))
(portRef AD3 (instanceRef mem_0_11))
(portRef AD3 (instanceRef mem_0_12))
(portRef AD3 (instanceRef mem_0_13))
))
(net (rename ascii_reg_2 "ascii_reg[2]") (joined
(portRef Q (instanceRef ascii_reg_2))
(portRef D (instanceRef ascii_reg_2))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef (member symbol_scan_cntr 2))
(portRef AD4 (instanceRef mem_0_0))
(portRef AD4 (instanceRef mem_0_1))
(portRef AD4 (instanceRef mem_0_2))
(portRef AD4 (instanceRef mem_0_3))
(portRef AD4 (instanceRef mem_0_4))
(portRef AD4 (instanceRef mem_0_5))
(portRef AD4 (instanceRef mem_0_6))
(portRef AD4 (instanceRef mem_0_7))
(portRef AD4 (instanceRef mem_0_8))
(portRef AD4 (instanceRef mem_0_9))
(portRef AD4 (instanceRef mem_0_10))
(portRef AD4 (instanceRef mem_0_11))
(portRef AD4 (instanceRef mem_0_12))
(portRef AD4 (instanceRef mem_0_13))
))
(net (rename ascii_reg_3 "ascii_reg[3]") (joined
(portRef Q (instanceRef ascii_reg_3))
(portRef D (instanceRef ascii_reg_3))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef (member symbol_scan_cntr 1))
(portRef AD5 (instanceRef mem_0_0))
(portRef AD5 (instanceRef mem_0_1))
(portRef AD5 (instanceRef mem_0_2))
(portRef AD5 (instanceRef mem_0_3))
(portRef AD5 (instanceRef mem_0_4))
(portRef AD5 (instanceRef mem_0_5))
(portRef AD5 (instanceRef mem_0_6))
(portRef AD5 (instanceRef mem_0_7))
(portRef AD5 (instanceRef mem_0_8))
(portRef AD5 (instanceRef mem_0_9))
(portRef AD5 (instanceRef mem_0_10))
(portRef AD5 (instanceRef mem_0_11))
(portRef AD5 (instanceRef mem_0_12))
(portRef AD5 (instanceRef mem_0_13))
))
(net (rename ascii_reg_4 "ascii_reg[4]") (joined
(portRef Q (instanceRef ascii_reg_4))
(portRef D (instanceRef ascii_reg_4))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef (member symbol_scan_cntr 0))
(portRef AD6 (instanceRef mem_0_0))
(portRef AD6 (instanceRef mem_0_1))
(portRef AD6 (instanceRef mem_0_2))
(portRef AD6 (instanceRef mem_0_3))
(portRef AD6 (instanceRef mem_0_4))
(portRef AD6 (instanceRef mem_0_5))
(portRef AD6 (instanceRef mem_0_6))
(portRef AD6 (instanceRef mem_0_7))
(portRef AD6 (instanceRef mem_0_8))
(portRef AD6 (instanceRef mem_0_9))
(portRef AD6 (instanceRef mem_0_10))
(portRef AD6 (instanceRef mem_0_11))
(portRef AD6 (instanceRef mem_0_12))
(portRef AD6 (instanceRef mem_0_13))
))
(net (rename ascii_reg_5 "ascii_reg[5]") (joined
(portRef Q (instanceRef ascii_reg_5))
(portRef D (instanceRef ascii_reg_5))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef DO0 (instanceRef mem_0_13))
(portRef (member disp_data_c 0))
))
(net (rename ascii_reg_6 "ascii_reg[6]") (joined
(portRef Q (instanceRef ascii_reg_6))
(portRef D (instanceRef ascii_reg_6))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef DO0 (instanceRef mem_0_12))
(portRef (member disp_data_c 1))
))
(net (rename ascii_reg_7 "ascii_reg[7]") (joined
(portRef Q (instanceRef ascii_reg_7))
(portRef D (instanceRef ascii_reg_7))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef DO0 (instanceRef mem_0_11))
(portRef (member disp_data_c 2))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef DO0 (instanceRef mem_0_10))
(portRef (member disp_data_c 3))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef DO0 (instanceRef mem_0_9))
(portRef (member disp_data_c 4))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef DO0 (instanceRef mem_0_8))
(portRef (member disp_data_c 5))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef DO0 (instanceRef mem_0_7))
(portRef (member disp_data_c 6))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef DO0 (instanceRef mem_0_6))
(portRef (member disp_data_c 7))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef DO0 (instanceRef mem_0_5))
(portRef (member disp_data_c 8))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef DO0 (instanceRef mem_0_4))
(portRef (member disp_data_c 9))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef DO0 (instanceRef mem_0_3))
(portRef (member disp_data_c 10))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef DO0 (instanceRef mem_0_2))
(portRef (member disp_data_c 11))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef DO0 (instanceRef mem_0_1))
(portRef (member disp_data_c 12))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef DO0 (instanceRef mem_0_0))
(portRef (member disp_data_c 13))
))
)
(property NGD_DRC_MASK (integer 1))
(property orig_inst_of (string "DistRomAsciiDecoder"))
)
)
(cell ASCIIDecoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance rom_decoding_table (viewRef netlist (cellRef DistRomAsciiDecoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
(portRef (member symbol_scan_cntr 6) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef (member symbol_scan_cntr 5))
(portRef (member symbol_scan_cntr 5) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef (member symbol_scan_cntr 4))
(portRef (member symbol_scan_cntr 4) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef (member symbol_scan_cntr 3))
(portRef (member symbol_scan_cntr 3) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef (member symbol_scan_cntr 2))
(portRef (member symbol_scan_cntr 2) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef (member symbol_scan_cntr 1))
(portRef (member symbol_scan_cntr 1) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef (member symbol_scan_cntr 0))
(portRef (member symbol_scan_cntr 0) (instanceRef rom_decoding_table))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 13))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 12))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 11))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 10))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 9))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 8))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 7))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 6))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 5))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 4))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 3))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 2))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 1))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 0))
))
)
(property orig_inst_of (string "ASCIIDecoder"))
)
)
(cell DisplayDriverwDecoder_Top (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance ascii_decoder_module (viewRef netlist (cellRef ASCIIDecoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
(portRef (member symbol_scan_cntr 6) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef (member symbol_scan_cntr 5))
(portRef (member symbol_scan_cntr 5) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef (member symbol_scan_cntr 4))
(portRef (member symbol_scan_cntr 4) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef (member symbol_scan_cntr 3))
(portRef (member symbol_scan_cntr 3) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef (member symbol_scan_cntr 2))
(portRef (member symbol_scan_cntr 2) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef (member symbol_scan_cntr 1))
(portRef (member symbol_scan_cntr 1) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef (member symbol_scan_cntr 0))
(portRef (member symbol_scan_cntr 0) (instanceRef ascii_decoder_module))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 13))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 12))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 11))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 10))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 9))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 8))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 7))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 6))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 5))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 4))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 3))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 2))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 1))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 0))
))
)
(property orig_inst_of (string "DisplayDriverwDecoder_Top"))
)
)
159,16 → 576,45
(view arch (viewType NETLIST)
(interface
(port clk (direction INPUT))
(port rst (direction INPUT))
(port n_rst (direction INPUT))
(port button (direction INPUT))
(port (array (rename disp_data "disp_data(14:0)") 15) (direction OUTPUT))
(port disp_sel (direction OUTPUT))
)
(contents
(instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
(instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
(instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
(instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
)
(instance (rename disp_data_pad_RNO_14 "disp_data_pad_RNO[14]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance n_rst_pad_RNIQVTF (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance (rename bttn_state_fifo_0io_0 "bttn_state_fifo_0io[0]") (viewRef PRIM (cellRef IFS1P3JX (libraryRef LUCENT)))
(property IOB (string "FALSE"))
)
(instance (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_7 "symbol_scan_cntr[7]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename bttn_state_fifo_1 "bttn_state_fifo[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
)
(instance (rename bttn_state_fifo_2 "bttn_state_fifo[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
)
(instance (rename bttn_state_fifo_3 "bttn_state_fifo[3]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
)
(instance bttn_state (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
)
(instance disp_sel_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_14 "disp_data_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_13 "disp_data_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
185,105 → 631,388
(instance (rename disp_data_pad_2 "disp_data_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_1 "disp_data_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_0 "disp_data_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance rst_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance button_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance n_rst_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
)
(instance bttn_stateand (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (!C (!B !A)))"))
)
(instance bttn_stateand_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B !A)"))
)
(instance bttn_state_RNIO8V61 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(C (!B !A))"))
)
(instance (rename bttn_state_fifo_0io_RNIB9K02_0 "bttn_state_fifo_0io_RNIB9K02[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C (!B A)))"))
)
(instance (rename symbol_scan_cntr_cry_0_0 "symbol_scan_cntr_cry_0[0]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0x500c"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_cry_0_1 "symbol_scan_cntr_cry_0[1]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa003"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_cry_0_3 "symbol_scan_cntr_cry_0[3]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa003"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_cry_0_5 "symbol_scan_cntr_cry_0[5]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa003"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_s_0_7 "symbol_scan_cntr_s_0[7]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa00a"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0x5003"))
)
(instance DDwD_Top (viewRef netlist (cellRef DisplayDriverwDecoder_Top))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef Q (instanceRef symbol_scan_cntr_0))
(portRef (member symbol_scan_cntr 6) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_0))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef Q (instanceRef symbol_scan_cntr_1))
(portRef (member symbol_scan_cntr 5) (instanceRef DDwD_Top))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef Q (instanceRef symbol_scan_cntr_2))
(portRef (member symbol_scan_cntr 4) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef Q (instanceRef symbol_scan_cntr_3))
(portRef (member symbol_scan_cntr 3) (instanceRef DDwD_Top))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef Q (instanceRef symbol_scan_cntr_4))
(portRef (member symbol_scan_cntr 2) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef Q (instanceRef symbol_scan_cntr_5))
(portRef (member symbol_scan_cntr 1) (instanceRef DDwD_Top))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef Q (instanceRef symbol_scan_cntr_6))
(portRef (member symbol_scan_cntr 0) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_7 "symbol_scan_cntr[7]") (joined
(portRef Q (instanceRef symbol_scan_cntr_7))
(portRef A0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef A (instanceRef disp_data_pad_RNO_14))
))
(net (rename bttn_state_fifo_0 "bttn_state_fifo[0]") (joined
(portRef Q (instanceRef bttn_state_fifo_0io_0))
(portRef B (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef A (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state_fifo_1))
))
(net (rename bttn_state_fifo_1 "bttn_state_fifo[1]") (joined
(portRef Q (instanceRef bttn_state_fifo_1))
(portRef C (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef B (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state_fifo_2))
))
(net (rename bttn_state_fifo_2 "bttn_state_fifo[2]") (joined
(portRef Q (instanceRef bttn_state_fifo_2))
(portRef D (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef C (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state_fifo_3))
))
(net (rename bttn_state_fifo_3 "bttn_state_fifo[3]") (joined
(portRef Q (instanceRef bttn_state_fifo_3))
(portRef A (instanceRef bttn_state_RNIO8V61))
(portRef A (instanceRef bttn_stateand_2_0))
))
(net bttn_state_i (joined
(portRef Q (instanceRef bttn_state))
(portRef B (instanceRef bttn_state_RNIO8V61))
))
(net bttn_stateand (joined
(portRef Z (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state))
))
(net (rename bttn_state_fifo_0io_RNIB9K02_0 "bttn_state_fifo_0io_RNIB9K02[0]") (joined
(portRef Z (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef SP (instanceRef symbol_scan_cntr_7))
(portRef SP (instanceRef symbol_scan_cntr_6))
(portRef SP (instanceRef symbol_scan_cntr_5))
(portRef SP (instanceRef symbol_scan_cntr_4))
(portRef SP (instanceRef symbol_scan_cntr_3))
(portRef SP (instanceRef symbol_scan_cntr_2))
(portRef SP (instanceRef symbol_scan_cntr_1))
(portRef SP (instanceRef symbol_scan_cntr_0))
))
(net (rename symbol_scan_cntr_cry_0 "symbol_scan_cntr_cry[0]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_0))
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_s_0 "symbol_scan_cntr_s[0]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef D (instanceRef symbol_scan_cntr_0))
))
(net (rename symbol_scan_cntr_s_1 "symbol_scan_cntr_s[1]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D (instanceRef symbol_scan_cntr_1))
))
(net (rename symbol_scan_cntr_cry_2 "symbol_scan_cntr_cry[2]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_1))
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_s_2 "symbol_scan_cntr_s[2]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D (instanceRef symbol_scan_cntr_2))
))
(net (rename symbol_scan_cntr_s_3 "symbol_scan_cntr_s[3]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D (instanceRef symbol_scan_cntr_3))
))
(net (rename symbol_scan_cntr_cry_4 "symbol_scan_cntr_cry[4]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_3))
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_s_4 "symbol_scan_cntr_s[4]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D (instanceRef symbol_scan_cntr_4))
))
(net (rename symbol_scan_cntr_s_5 "symbol_scan_cntr_s[5]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D (instanceRef symbol_scan_cntr_5))
))
(net (rename symbol_scan_cntr_cry_6 "symbol_scan_cntr_cry[6]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_5))
(portRef CIN (instanceRef symbol_scan_cntr_s_0_7))
))
(net (rename symbol_scan_cntr_s_6 "symbol_scan_cntr_s[6]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D (instanceRef symbol_scan_cntr_6))
))
(net (rename symbol_scan_cntr_s_7 "symbol_scan_cntr_s[7]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef D (instanceRef symbol_scan_cntr_7))
))
(net bttn_stateand_2_0 (joined
(portRef Z (instanceRef bttn_stateand_2_0))
(portRef D (instanceRef bttn_stateand))
))
(net (rename symbol_scan_cntr_cry_0_S0_0 "symbol_scan_cntr_cry_0_S0[0]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_0))
))
(net (rename symbol_scan_cntr_s_0_S1_7 "symbol_scan_cntr_s_0_S1[7]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_s_0_7))
))
(net (rename symbol_scan_cntr_s_0_COUT_7 "symbol_scan_cntr_s_0_COUT[7]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_s_0_7))
))
(net G_15_1 (joined
(portRef Z (instanceRef bttn_state_RNIO8V61))
(portRef A (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
))
(net VCC (joined
(portRef Z (instanceRef VCC))
(portRef I (instanceRef disp_data_pad_4))
(portRef I (instanceRef disp_data_pad_5))
(portRef I (instanceRef disp_data_pad_6))
(portRef I (instanceRef disp_data_pad_8))
(portRef I (instanceRef disp_data_pad_10))
(portRef I (instanceRef disp_data_pad_11))
(portRef I (instanceRef disp_data_pad_13))
(portRef D1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef C1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef B1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef A1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef D0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef C0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef B0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef SP (instanceRef bttn_state_fifo_0io_0))
(portRef GSR (instanceRef GSR_INST))
))
(net GND (joined
(portRef Z (instanceRef GND))
(portRef I (instanceRef disp_data_pad_0))
(portRef I (instanceRef disp_data_pad_1))
(portRef I (instanceRef disp_data_pad_2))
(portRef I (instanceRef disp_data_pad_3))
(portRef I (instanceRef disp_data_pad_7))
(portRef I (instanceRef disp_data_pad_9))
(portRef I (instanceRef disp_data_pad_12))
(portRef I (instanceRef disp_data_pad_14))
(portRef I (instanceRef disp_sel_pad))
))
(net clk_c (joined
(portRef O (instanceRef clk_pad))
(portRef clk_c (instanceRef DDwD_Top))
(portRef CK (instanceRef bttn_state))
(portRef CK (instanceRef bttn_state_fifo_3))
(portRef CK (instanceRef bttn_state_fifo_2))
(portRef CK (instanceRef bttn_state_fifo_1))
(portRef CK (instanceRef symbol_scan_cntr_7))
(portRef CK (instanceRef symbol_scan_cntr_6))
(portRef CK (instanceRef symbol_scan_cntr_5))
(portRef CK (instanceRef symbol_scan_cntr_4))
(portRef CK (instanceRef symbol_scan_cntr_3))
(portRef CK (instanceRef symbol_scan_cntr_2))
(portRef CK (instanceRef symbol_scan_cntr_1))
(portRef CK (instanceRef symbol_scan_cntr_0))
(portRef SCLK (instanceRef bttn_state_fifo_0io_0))
))
(net clk (joined
(portRef clk)
(portRef I (instanceRef clk_pad))
))
(net rst_c (joined
(portRef O (instanceRef rst_pad))
(portRef rst_c (instanceRef DDwD_Top))
(net n_rst_c (joined
(portRef O (instanceRef n_rst_pad))
(portRef C (instanceRef bttn_state_RNIO8V61))
(portRef B (instanceRef bttn_stateand_2_0))
(portRef A (instanceRef n_rst_pad_RNIQVTF))
))
(net rst (joined
(portRef rst)
(portRef I (instanceRef rst_pad))
(net n_rst (joined
(portRef n_rst)
(portRef I (instanceRef n_rst_pad))
))
(net button_c (joined
(portRef O (instanceRef button_pad))
(portRef D (instanceRef bttn_state_fifo_0io_0))
))
(net button (joined
(portRef button)
(portRef I (instanceRef button_pad))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_0))
))
(net (rename disp_data_0 "disp_data[0]") (joined
(portRef O (instanceRef disp_data_pad_0))
(portRef (member disp_data 14))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_1))
))
(net (rename disp_data_1 "disp_data[1]") (joined
(portRef O (instanceRef disp_data_pad_1))
(portRef (member disp_data 13))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_2))
))
(net (rename disp_data_2 "disp_data[2]") (joined
(portRef O (instanceRef disp_data_pad_2))
(portRef (member disp_data 12))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_3))
))
(net (rename disp_data_3 "disp_data[3]") (joined
(portRef O (instanceRef disp_data_pad_3))
(portRef (member disp_data 11))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_4))
))
(net (rename disp_data_4 "disp_data[4]") (joined
(portRef O (instanceRef disp_data_pad_4))
(portRef (member disp_data 10))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_5))
))
(net (rename disp_data_5 "disp_data[5]") (joined
(portRef O (instanceRef disp_data_pad_5))
(portRef (member disp_data 9))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_6))
))
(net (rename disp_data_6 "disp_data[6]") (joined
(portRef O (instanceRef disp_data_pad_6))
(portRef (member disp_data 8))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_7))
))
(net (rename disp_data_7 "disp_data[7]") (joined
(portRef O (instanceRef disp_data_pad_7))
(portRef (member disp_data 7))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_8))
))
(net (rename disp_data_8 "disp_data[8]") (joined
(portRef O (instanceRef disp_data_pad_8))
(portRef (member disp_data 6))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_9))
))
(net (rename disp_data_9 "disp_data[9]") (joined
(portRef O (instanceRef disp_data_pad_9))
(portRef (member disp_data 5))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_10))
))
(net (rename disp_data_10 "disp_data[10]") (joined
(portRef O (instanceRef disp_data_pad_10))
(portRef (member disp_data 4))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_11))
))
(net (rename disp_data_11 "disp_data[11]") (joined
(portRef O (instanceRef disp_data_pad_11))
(portRef (member disp_data 3))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_12))
))
(net (rename disp_data_12 "disp_data[12]") (joined
(portRef O (instanceRef disp_data_pad_12))
(portRef (member disp_data 2))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_13))
))
(net (rename disp_data_13 "disp_data[13]") (joined
(portRef O (instanceRef disp_data_pad_13))
(portRef (member disp_data 1))
296,6 → 1025,28
(portRef O (instanceRef disp_sel_pad))
(portRef disp_sel)
))
(net n_rst_c_i (joined
(portRef Z (instanceRef n_rst_pad_RNIQVTF))
(portRef PD (instanceRef bttn_state_fifo_3))
(portRef PD (instanceRef bttn_state_fifo_2))
(portRef PD (instanceRef bttn_state_fifo_1))
(portRef CD (instanceRef symbol_scan_cntr_7))
(portRef CD (instanceRef symbol_scan_cntr_6))
(portRef CD (instanceRef symbol_scan_cntr_5))
(portRef CD (instanceRef symbol_scan_cntr_4))
(portRef CD (instanceRef symbol_scan_cntr_3))
(portRef CD (instanceRef symbol_scan_cntr_2))
(portRef CD (instanceRef symbol_scan_cntr_1))
(portRef CD (instanceRef symbol_scan_cntr_0))
(portRef PD (instanceRef bttn_state_fifo_0io_0))
))
(net (rename symbol_scan_cntr_i_7 "symbol_scan_cntr_i[7]") (joined
(portRef Z (instanceRef disp_data_pad_RNO_14))
(portRef I (instanceRef disp_data_pad_14))
))
(net N_1 (joined
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_0))
))
)
(property orig_inst_of (string "DisplayDriverWrapper"))
)
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.mrp
17,26 → 17,29
Target Device: LFE5UM5G-45FCABGA381
Target Performance: 8
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
Mapped on: 01/13/17 00:54:48
Mapped on: 01/17/17 01:36:37
 
Design Summary
--------------
 
Number of registers: 0 out of 44457 (0%)
PFU registers: 0 out of 43848 (0%)
PIO registers: 0 out of 609 (0%)
Number of SLICEs: 0 out of 21924 (0%)
SLICEs as Logic/ROM: 0 out of 21924 (0%)
Number of registers: 13 out of 44457 (0%)
PFU registers: 12 out of 43848 (0%)
PIO registers: 1 out of 609 (0%)
Number of SLICEs: 65 out of 21924 (0%)
SLICEs as Logic/ROM: 65 out of 21924 (0%)
SLICEs as RAM: 0 out of 16443 (0%)
SLICEs as Carry: 0 out of 21924 (0%)
Number of LUT4s: 0 out of 43848 (0%)
Number used as logic LUTs: 0
SLICEs as Carry: 5 out of 21924 (0%)
Number of LUT4s: 127 out of 43848 (0%)
Number used as logic LUTs: 117
Number used as distributed RAM: 0
Number used as ripple logic: 0
Number used as ripple logic: 10
Number used as shift registers: 0
Number of PIO sites used: 16 out of 203 (8%)
Number of PIO sites used: 20 out of 203 (10%)
Number of PIO sites used for single ended IOs: 18
Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
comps in NCD)
Number of block RAMs: 0 out of 108 (0%)
Number of GSRs: 0 out of 1 (0%)
Number of GSRs: 1 out of 1 (100%)
JTAG used : No
Readback used : No
Oscillator used : No
57,19 → 60,19
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
 
 
Page 1
 
 
 
 
Design: DisplayDriverWrapper Date: 01/13/17 00:54:48
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
 
Design Summary (cont)
---------------------
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
 
Number Of Mapped DSP Components:
--------------------------------
MULT18X18D 0
82,16 → 85,30
Number of Used DSP MULT Sites: 0 out of 144 (0 %)
Number of Used DSP ALU Sites: 0 out of 72 (0 %)
Number of Used DSP PRADD Sites: 0 out of 144 (0 %)
Number of clocks: 0
Number of Clock Enables: 0
Number of LSRs: 0
Number of clocks: 1
Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )
Number of Clock Enables: 1
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads, 5 LSLICEs
Number of local set/reset loads for net n_rst_c merged into GSR: 8
Number of LSRs: 1
Net n_rst_c: 3 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net symbol_scan_cntr[1]: 107 loads
Net symbol_scan_cntr[2]: 107 loads
Net symbol_scan_cntr[3]: 107 loads
Net symbol_scan_cntr[5]: 86 loads
Net symbol_scan_cntr[6]: 57 loads
Net symbol_scan_cntr[4]: 29 loads
Net symbol_scan_cntr[0]: 15 loads
Net n_rst_c: 6 loads
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads
Net bttn_state_fifo[0]: 3 loads
 
 
 
 
Number of warnings: 1
Number of warnings: 4
Number of errors: 0
 
98,9 → 115,25
Design Errors/Warnings
----------------------
 
WARNING - map: IO buffer missing for top level port button...logic will be
discarded.
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE
ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
preference has been disabled.
WARNING - map: Preference parsing results: 1 semantic error detected.
WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.
WARNING - map: There are semantic errors in the preference file C:/Projects/sing
le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr
iverwDecoder.lpf.
 
 
 
Page 2
 
 
 
 
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
 
IO (PIO) Attributes
-------------------
 
110,6 → 143,8
+---------------------+-----------+-----------+------------+
| disp_data[0] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| clk | INPUT | LVDS | |
+---------------------+-----------+-----------+------------+
| disp_sel | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[14] | OUTPUT | LVCMOS25 | |
126,16 → 161,6
+---------------------+-----------+-----------+------------+
| disp_data[8] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
 
Page 2
 
 
 
 
Design: DisplayDriverWrapper Date: 01/13/17 00:54:48
 
IO (PIO) Attributes (cont)
--------------------------
| disp_data[7] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[6] | OUTPUT | LVCMOS25 | |
150,36 → 175,35
+---------------------+-----------+-----------+------------+
| disp_data[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| button | INPUT | LVCMOS25 | IN |
+---------------------+-----------+-----------+------------+
| n_rst | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
 
Removed logic
-------------
 
Block GSR_INST undriven or does not drive anything - clipped.
Block rst_pad undriven or does not drive anything - clipped.
Block DDwD_Top/VCC undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
Block clk_pad undriven or does not drive anything - clipped.
Signal n_rst_c_i was merged into signal n_rst_c
Signal GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal rst undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
Signal rst_c undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
Signal clk_c undriven or does not drive anything - clipped.
Signal clk undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
clipped.
Signal N_1 undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
 
Page 3
 
 
 
 
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
 
Removed logic (cont)
--------------------
clipped.
Block n_rst_pad_RNIQVTF was optimized away.
Block GND was optimized away.
Block VCC was optimized away.
 
189,23 → 213,42
 
 
GSR Usage
---------
 
GSR Component:
The local reset signal 'n_rst_c' of the design has been inferred as Global
Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.
 
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
 
Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------
 
Page 3
These components have the GSR property set to DISABLED and are on the
inferred reset domain. The components will respond to the reset signal
'n_rst_c' via the local reset on the component and not the GSR component.
 
Type and number of components of the type:
Register = 4
 
Type and instance name of component:
Register : bttn_state_fifo[3]
Register : bttn_state_fifo_0io[0]
Register : bttn_state_fifo[1]
Register : bttn_state_fifo[2]
 
 
Design: DisplayDriverWrapper Date: 01/13/17 00:54:48
 
Run Time and Memory Usage
-------------------------
 
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 60 MB
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Peak Memory Usage: 152 MB
 
 
216,49 → 259,6
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Page 4
 
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.ncd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.ngd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.ngo Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.pad
6,34 → 6,38
PACKAGE: CABGA381
Package Status: Final Version 1.36
 
Fri Jan 13 00:54:59 2017
Tue Jan 17 01:36:59 2017
 
Pinout by Port Name:
+---------------+----------+--------------+-------+-----------+-------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+-------------------------------+
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
+---------------+----------+--------------+-------+-----------+-------------------------------+
+---------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+---------------+----------+--------------+-------+-----------+---------------------------------+
 
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 2 | 2.5V |
| 3 | 2.5V |
| 6 | 2.5V |
| 8 | 2.5V |
187,7 → 191,7
| K5/6 | unused, PULL:DOWN | | | PL44B | VREF1_6/LDQ41 | |
| K18/2 | unused, PULL:DOWN | | | PR29D | RDQ29 | |
| K19/2 | unused, PULL:DOWN | | | PR32B | PCLKC2_1/RDQ29 | |
| K20/2 | unused, PULL:DOWN | | | PR32D | PCLKC2_0/RDQ29 | |
| K20/2 | n_rst | LOCATED | LVCMOS25_IN | PR32D | PCLKC2_0/RDQ29 | |
| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | |
| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | |
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | |
218,8 → 222,8
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | |
| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | |
| P3/6 | unused, PULL:DOWN | | | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | unused, PULL:DOWN | | | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
275,7 → 279,7
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | |
| T1/8 | unused, PULL:DOWN | | | PB4B | D6/IO6 | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | |
| T2/8 | unused, PULL:DOWN | | | PB13A | SN/CSN | |
| T3/8 | unused, PULL:DOWN | | | PB18A | WRITEN | |
| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | |
325,6 → 329,8
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
 
LOCATE COMP "button" SITE "T1";
LOCATE COMP "clk" SITE "P3";
LOCATE COMP "disp_data[0]" SITE "M20";
LOCATE COMP "disp_data[10]" SITE "N18";
LOCATE COMP "disp_data[11]" SITE "N17";
341,6 → 347,7
LOCATE COMP "disp_data[8]" SITE "N16";
LOCATE COMP "disp_data[9]" SITE "M17";
LOCATE COMP "disp_sel" SITE "J1";
LOCATE COMP "n_rst" SITE "K20";
 
 
 
352,5 → 359,5
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Fri Jan 13 00:54:59 2017
Tue Jan 17 01:36:59 2017
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.par
4,7 → 4,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Fri Jan 13 00:54:53 2017
Tue Jan 17 01:36:43 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
17,17 → 17,17
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 06 Complete
5_1 * 0 -1.238 7103 0.178 0 26 Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 6 secs
Total (real) run time for 1-seed: 26 secs
 
par done!
 
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Fri Jan 13 00:54:53 2017
Tue Jan 17 01:36:43 2017
 
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
51,34 → 51,39
Ignore Preference Error(s): True
Device utilization summary:
 
PIO (prelim) 16/245 6% used
16/203 7% bonded
PIO (prelim) 20/245 8% used
20/203 9% bonded
IOLOGIC 1/245 <1% used
 
SLICE 0/21924 0% used
SLICE 65/21924 <1% used
 
GSR 1/1 100% used
 
 
Number of Signals: 0
Number of Connections: 0
Number of Signals: 131
Number of Connections: 657
 
Pin Constraint Summary:
16 out of 16 pins locked (100% locked).
19 out of 19 pins locked (100% locked).
 
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
 
No signal is selected as Global Set/Reset.
 
Signal n_rst_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 4 secs
 
Finished Placer Phase 0. REAL time: 5 secs
 
Starting Placer Phase 1.
.......................
Placer score = 63578.
Finished Placer Phase 1. REAL time: 15 secs
 
Placer score = 0.
Finished Placer Phase 1. REAL time: 5 secs
 
Starting Placer Phase 2.
.
Placer score = 0
Finished Placer Phase 2. REAL time: 5 secs
Placer score = 63553
Finished Placer Phase 2. REAL time: 15 secs
 
 
------------------ Clock Report ------------------
85,7 → 90,7
 
Global Clock Resources:
CLK_PIN : 0 out of 12 (0%)
GR_PCLK : 0 out of 12 (0%)
GR_PCLK : 1 out of 12 (8%)
PLL : 0 out of 4 (0%)
DCS : 0 out of 2 (0%)
DCC : 0 out of 60 (0%)
100,12 → 105,14
PRIMARY : 0 out of 16 (0%)
 
Quadrant BL Clocks:
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 1
 
PRIMARY : 0 out of 16 (0%)
PRIMARY : 1 out of 16 (6%)
 
Quadrant BR Clocks:
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 8
 
PRIMARY : 0 out of 16 (0%)
PRIMARY : 1 out of 16 (6%)
 
Edge Clocks:
 
117,9 → 124,9
 
+
I/O Usage Summary (final):
16 out of 245 (6.5%) PIO sites used.
16 out of 203 (7.9%) bonded PIO sites used.
Number of PIO comps: 16; differential: 0.
20 out of 245 (8.2%) PIO sites used.
20 out of 203 (9.9%) bonded PIO sites used.
Number of PIO comps: 19; differential: 1.
Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
128,20 → 135,104
+----------+----------------+------------+------------+------------+
| 0 | 0 / 27 ( 0%) | - | - | - |
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 0 / 32 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 1 / 33 ( 3%) | 2.5V | - | - |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 1 / 13 ( 7%) | 2.5V | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 3 secs
Total placer CPU time: 15 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
Timing score: 0
0 connections routed; 657 unrouted.
Starting router resource preassignment
 
Completed router resource preassignment. Real time: 23 secs
 
Start NBR router at 01:37:06 01/17/17
 
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
 
Start NBR special constraint process at 01:37:06 01/17/17
 
Start NBR section for initial routing at 01:37:06 01/17/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
 
Start NBR section for normal routing at 01:37:07 01/17/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for re-routing at 01:37:07 01/17/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for post-routing at 01:37:07 01/17/17
 
End NBR router with 0 unrouted connection
 
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 9 (1.37%)
Estimated worst slack<setup> : -1.238ns
Timing score<setup> : 7103
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
 
 
 
Total CPU time 24 secs
Total REAL time: 25 secs
Completely routed.
End of route. 657 routed (100.00%); 0 unrouted.
 
Hold time timing score: 0, hold timing errors: 0
 
Timing score: 7103
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
 
150,14 → 241,14
 
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Worst slack<setup/<ns>> = -1.238
PAR_SUMMARY::Timing score<setup/<ns>> = 7.103
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.178
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
 
Total CPU time to completion: 4 secs
Total REAL time to completion: 6 secs
Total CPU time to completion: 25 secs
Total REAL time to completion: 26 secs
 
par done!
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.prf
1,8 → 1,9
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Fri Jan 13 00:54:49 2017
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Tue Jan 17 01:36:39 2017
 
SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ;
LOCATE COMP "disp_data[0]" SITE "M20" ;
LOCATE COMP "clk" SITE "P3" ;
LOCATE COMP "disp_sel" SITE "J1" ;
LOCATE COMP "disp_data[14]" SITE "U1" ;
LOCATE COMP "disp_data[13]" SITE "R16" ;
18,7 → 19,14
LOCATE COMP "disp_data[3]" SITE "L16" ;
LOCATE COMP "disp_data[2]" SITE "M19" ;
LOCATE COMP "disp_data[1]" SITE "L18" ;
LOCATE COMP "button" SITE "T1" ;
LOCATE COMP "n_rst" SITE "K20" ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
COMMERCIAL ;
 
// No timing preferences found. TRCE invokes auto-generation of timing preferences
// Section Autogen
FREQUENCY NET "clk_c" 369.959 MHz ;
// End Section Autogen
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srf
3,7 → 3,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
#Implementation: impl1
 
17,27 → 17,42
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
44,7 → 59,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
@END
54,7 → 69,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
66,7 → 81,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Pre-mapping Report
89,10 → 104,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
106,13 → 121,13
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
128,7 → 143,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Map & Optimize Report
165,6 → 180,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
194,12 → 210,22
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
 
3 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.64ns 1 / 9
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
 
208,15 → 234,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
226,7 → 252,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
233,21 → 259,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 13 00:54:42 2017
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1220.4 MHz
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
261,13 → 287,13
*******************
 
 
Worst slack in design: -0.145
Worst slack in design: -0.398
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
276,12 → 302,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
===========================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
295,7 → 321,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
 
 
303,37 → 329,38
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
 
 
 
342,128 → 369,179
 
 
Path information for path number 1:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
 
472,35 → 550,36
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
 
Details:
FD1S3IX: 5
FD1S3JX: 3
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:42 2017
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srr
3,7 → 3,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
#Implementation: impl1
 
17,27 → 17,42
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
44,7 → 59,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
@END
54,7 → 69,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
66,7 → 81,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Pre-mapping Report
89,10 → 104,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
106,13 → 121,13
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
128,7 → 143,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Map & Optimize Report
165,6 → 180,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
194,12 → 210,22
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
 
3 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.64ns 1 / 9
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
 
208,15 → 234,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
226,7 → 252,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
233,21 → 259,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 13 00:54:42 2017
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1220.4 MHz
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
261,13 → 287,13
*******************
 
 
Worst slack in design: -0.145
Worst slack in design: -0.398
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
276,12 → 302,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
===========================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
295,7 → 321,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
 
 
303,37 → 329,38
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
 
 
 
342,128 → 369,179
 
 
Path information for path number 1:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
 
472,35 → 550,36
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
 
Details:
FD1S3IX: 5
FD1S3JX: 3
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:42 2017
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.tw1
13,7 → 13,7
 
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3
Fri Jan 13 00:54:52 2017
Tue Jan 17 01:36:41 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
30,6 → 30,7
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
 
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
37,16 → 38,52
 
 
================================================================================
Preference: Default path enumeration
0 items scored, 0 timing errors detected.
Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
================================================================================
Preference: Default net enumeration
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.001ns
The internal maximum frequency of the following component is 370.096 MHz
 
Logical Details: Cell type Pin name Component name
 
Destination: SIOLOGIC CLK button_MGIOL
 
Delay: 2.702ns -- based on Minimum Pulse Width
 
 
Passed: The following path meets requirements by 1.063ns
 
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
 
Source: FF Q bttn_state (from clk_c +)
Destination: FF Data in symbol_scan_cntr[7] (to clk_c +)
 
Delay: 1.749ns (43.2% logic, 56.8% route), 3 logic levels.
 
Constraint Details:
 
1.749ns physical path delay SLICE_7 to SLICE_0 meets
2.703ns delay constraint less
-0.109ns CE_SET requirement (totaling 2.812ns) by 1.063ns
 
Physical Path Details:
 
Data path SLICE_7 to SLICE_0:
 
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.395 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from clk_c)
ROUTE 1 e 0.419 SLICE_7.Q0 to SLICE_64.B1 bttn_state_i
CTOF_DEL --- 0.180 SLICE_64.B1 to SLICE_64.F1 SLICE_64
ROUTE 1 e 0.156 SLICE_64.F1 to SLICE_64.A0 G_15_1
CTOF_DEL --- 0.180 SLICE_64.A0 to SLICE_64.F0 SLICE_64
ROUTE 5 e 0.419 SLICE_64.F0 to SLICE_0.CE bttn_state_fifo_0io_RNIB9K02[0] (to clk_c)
--------
1.749 (43.2% logic, 56.8% route), 3 logic levels.
 
Report: 370.096MHz is the maximum frequency for this preference.
 
Report Summary
--------------
----------------------------------------------------------------------------
53,10 → 90,8
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
Default path enumeration | -| -| 0
FREQUENCY NET "clk_c" 369.959000 MHz ; | 369.959 MHz| 370.096 MHz| 0
| | |
Default net enumeration | -| -| 0
| | |
----------------------------------------------------------------------------
 
 
66,9 → 101,12
Clock Domains Analysis
------------------------
 
Found 0 clocks:
Found 1 clocks:
 
Clock Domain: clk_c Source: clk.PAD Loads: 9
Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
 
 
Timing summary (Setup):
---------------
 
75,7 → 113,104
Timing errors: 0 Score: 0
Cumulative negative slack: 0
 
Constraints cover 0 paths, 0 nets, and 0 connections (100.00% coverage)
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
 
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3
Tue Jan 17 01:36:42 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
 
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
Design file: displaydriverwdecoder_impl1_map.ncd
Preference file: displaydriverwdecoder_impl1.prf
Device,speed: LFE5UM5G-45F,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
 
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
 
 
 
================================================================================
Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
Passed: The following path meets requirements by 0.104ns
 
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
 
Source: FF Q bttn_state_fifo[1] (from clk_c +)
Destination: FF Data in bttn_state_fifo[2] (to clk_c +)
 
Delay: 0.222ns (73.9% logic, 26.1% route), 1 logic levels.
 
Constraint Details:
 
0.222ns physical path delay SLICE_5 to SLICE_5 meets
0.118ns M_HLD and
0.000ns delay constraint requirement (totaling 0.118ns) by 0.104ns
 
Physical Path Details:
 
Data path SLICE_5 to SLICE_5:
 
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.164 SLICE_5.CLK to SLICE_5.Q0 SLICE_5 (from clk_c)
ROUTE 3 e 0.058 SLICE_5.Q0 to SLICE_5.M1 bttn_state_fifo[1] (to clk_c)
--------
0.222 (73.9% logic, 26.1% route), 1 logic levels.
 
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_c" 369.959000 MHz ; | 0.000 ns| 0.104 ns| 1
| | |
----------------------------------------------------------------------------
 
 
All preferences were met.
 
 
Clock Domains Analysis
------------------------
 
Found 1 clocks:
 
Clock Domain: clk_c Source: clk.PAD Loads: 9
Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
 
 
Timing summary (Hold):
---------------
 
Timing errors: 0 Score: 0
Cumulative negative slack: 0
 
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
 
 
 
Timing summary (Setup and Hold):
---------------
 
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_bgn.html
111,8 → 111,7
Performance Hardware Data Status: Final Version 50.1.
 
Running DRC.
WARNING - netcheck: Design is completely unrouted. 0 warnings not reported below.
DRC detected 0 errors and 1 warnings.
DRC detected 0 errors and 0 warnings.
Reading Preference File from DisplayDriverwDecoder_impl1.prf.
 
<A name="bgn_ps"></A>
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_cck.rpt
1,7 → 1,7
# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Fri Jan 13 00:54:39 2017
# Written on Tue Jan 17 01:19:11 2017
 
 
##### DESIGN INFO #######################################################
24,9 → 24,10
Clock Relationships
*******************
 
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------
===================================================================================================================================
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 1.088 | No paths | No paths | No paths
===========================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
34,7 → 35,7
Unconstrained Start/End Points
******************************
 
p:button
p:clk
p:disp_data[0]
p:disp_data[1]
p:disp_data[2]
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.asd
3,12 → 3,14
Package = CABGA381;
Performance = 8;
LUTS_avail = 43848;
LUTS_used = 0;
LUTS_used = 127;
FF_avail = 44051;
FF_used = 0;
FF_used = 13;
INPUT_LVCMOS25 = 2;
INPUT_LVDS = 1;
OUTPUT_LVCMOS25 = 16;
IO_avail = 203;
IO_used = 16;
IO_used = 20;
EBR_avail = 108;
EBR_used = 0;
;
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.cam
1,27 → 1,21
[ START MERGED ]
n_rst_c_i n_rst_c
[ END MERGED ]
[ START CLIPPED ]
GND
VCC
rst
DDwD_Top/ascii_reg[5]
DDwD_Top/ascii_reg[4]
DDwD_Top/ascii_reg[3]
DDwD_Top/ascii_reg[2]
DDwD_Top/ascii_reg[1]
DDwD_Top/ascii_reg[0]
DDwD_Top/ascii_reg[7]
rst_c
DDwD_Top/ascii_reg[6]
clk_c
clk
symbol_scan_cntr_cry_0_S0[0]
N_1
symbol_scan_cntr_s_0_S1[7]
symbol_scan_cntr_s_0_COUT[7]
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Fri Jan 13 00:54:49 2017
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Tue Jan 17 01:36:39 2017
 
SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ;
LOCATE COMP "disp_data[0]" SITE "M20" ;
LOCATE COMP "clk" SITE "P3" ;
LOCATE COMP "disp_sel" SITE "J1" ;
LOCATE COMP "disp_data[14]" SITE "U1" ;
LOCATE COMP "disp_data[13]" SITE "R16" ;
37,5 → 31,7
LOCATE COMP "disp_data[3]" SITE "L16" ;
LOCATE COMP "disp_data[2]" SITE "M19" ;
LOCATE COMP "disp_data[1]" SITE "L18" ;
LOCATE COMP "button" SITE "T1" ;
LOCATE COMP "n_rst" SITE "K20" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.hrr
3,12 → 3,40
Instance path: DisplayDriverWrapper
Cell usage:
cell count Res Usage(%)
IOBUF 16 100.0
SLIC 65.00 100.0
IOLGC 1.00 100.0
LUT4 117.00 100.0
IOREG 1 100.0
IOBUF 19 100.0
PFUREG 12 100.0
RIPPLE 5 100.0
SUB MODULES
cell count SLC Usage(%)
DisplayDriverwDecoder_Top 1 -1.$
DisplayDriverwDecoder_Top 1 86.2
---------------------------------------------------
Report for cell DisplayDriverwDecoder_Top
Instance path: DisplayDriverWrapper/DDwD_Top
Cell usage:
cell count Res Usage(%)
SLIC 56.00 86.2
LUT4 112.00 95.7
SUB MODULES
cell count SLC Usage(%)
ASCIIDecoder 1 86.2
---------------------------------------------------
Report for cell ASCIIDecoder
Instance path: DisplayDriverWrapper/DDwD_Top/ascii_decoder_module
Cell usage:
cell count Res Usage(%)
SLIC 56.00 86.2
LUT4 112.00 95.7
SUB MODULES
cell count SLC Usage(%)
DistRomAsciiDecoder 1 86.2
---------------------------------------------------
Report for cell DistRomAsciiDecoder
Instance path: DisplayDriverWrapper/DDwD_Top/ascii_decoder_module/rom_decoding_table
Cell usage:
cell count Res Usage(%)
SLIC 56.00 86.2
LUT4 112.00 95.7
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.ncd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_mrp.html
109,25 → 109,28
Target Device: LFE5UM5G-45FCABGA381
Target Performance: 8
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
Mapped on: 01/13/17 00:54:48
Mapped on: 01/17/17 01:36:37
 
 
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 0 out of 44457 (0%)
PFU registers: 0 out of 43848 (0%)
PIO registers: 0 out of 609 (0%)
Number of SLICEs: 0 out of 21924 (0%)
SLICEs as Logic/ROM: 0 out of 21924 (0%)
Number of registers: 13 out of 44457 (0%)
PFU registers: 12 out of 43848 (0%)
PIO registers: 1 out of 609 (0%)
Number of SLICEs: 65 out of 21924 (0%)
SLICEs as Logic/ROM: 65 out of 21924 (0%)
SLICEs as RAM: 0 out of 16443 (0%)
SLICEs as Carry: 0 out of 21924 (0%)
Number of LUT4s: 0 out of 43848 (0%)
Number used as logic LUTs: 0
SLICEs as Carry: 5 out of 21924 (0%)
Number of LUT4s: 127 out of 43848 (0%)
Number used as logic LUTs: 117
Number used as distributed RAM: 0
Number used as ripple logic: 0
Number used as ripple logic: 10
Number used as shift registers: 0
Number of PIO sites used: 16 out of 203 (8%)
Number of PIO sites used: 20 out of 203 (10%)
Number of PIO sites used for single ended IOs: 18
Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
comps in NCD)
Number of block RAMs: 0 out of 108 (0%)
Number of GSRs: 0 out of 1 (0%)
Number of GSRs: 1 out of 1 (100%)
JTAG used : No
Readback used : No
Oscillator used : No
148,10 → 151,10
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
 
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
 
 
Number Of Mapped DSP Components:
--------------------------------
MULT18X18D 0
164,16 → 167,30
Number of Used DSP MULT Sites: 0 out of 144 (0 %)
Number of Used DSP ALU Sites: 0 out of 72 (0 %)
Number of Used DSP PRADD Sites: 0 out of 144 (0 %)
Number of clocks: 0
Number of Clock Enables: 0
Number of LSRs: 0
Number of clocks: 1
Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )
Number of Clock Enables: 1
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads, 5 LSLICEs
Number of local set/reset loads for net n_rst_c merged into GSR: 8
Number of LSRs: 1
Net n_rst_c: 3 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net symbol_scan_cntr[1]: 107 loads
Net symbol_scan_cntr[2]: 107 loads
Net symbol_scan_cntr[3]: 107 loads
Net symbol_scan_cntr[5]: 86 loads
Net symbol_scan_cntr[6]: 57 loads
Net symbol_scan_cntr[4]: 29 loads
Net symbol_scan_cntr[0]: 15 loads
Net n_rst_c: 6 loads
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads
Net bttn_state_fifo[0]: 3 loads
 
 
 
 
Number of warnings: 1
Number of warnings: 4
Number of errors: 0
 
182,11 → 199,20
 
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
 
WARNING - map: IO buffer missing for top level port button...logic will be
discarded.
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE
ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
preference has been disabled.
WARNING - map: Preference parsing results: 1 semantic error detected.
WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.
WARNING - map: There are semantic errors in the preference file C:/Projects/sing
le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr
iverwDecoder.lpf.
 
 
 
 
 
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
 
+---------------------+-----------+-----------+------------+
195,6 → 221,8
+---------------------+-----------+-----------+------------+
| disp_data[0] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| clk | INPUT | LVDS | |
+---------------------+-----------+-----------+------------+
| disp_sel | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[14] | OUTPUT | LVCMOS25 | |
211,7 → 239,6
+---------------------+-----------+-----------+------------+
| disp_data[8] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
 
| disp_data[7] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[6] | OUTPUT | LVCMOS25 | |
226,37 → 253,27
+---------------------+-----------+-----------+------------+
| disp_data[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| button | INPUT | LVCMOS25 | IN |
+---------------------+-----------+-----------+------------+
| n_rst | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
 
 
 
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
 
Block GSR_INST undriven or does not drive anything - clipped.
Block rst_pad undriven or does not drive anything - clipped.
Block DDwD_Top/VCC undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
Block clk_pad undriven or does not drive anything - clipped.
Signal n_rst_c_i was merged into signal n_rst_c
Signal GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal rst undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
Signal rst_c undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
Signal clk_c undriven or does not drive anything - clipped.
Signal clk undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
clipped.
Signal N_1 undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
 
clipped.
Block n_rst_pad_RNIQVTF was optimized away.
Block GND was optimized away.
Block VCC was optimized away.
 
269,25 → 286,45
 
 
 
<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>
---------
 
GSR Component:
The local reset signal 'n_rst_c' of the design has been inferred as Global
Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.
 
 
 
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
 
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 60 MB
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
 
Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------
 
These components have the GSR property set to DISABLED and are on the
inferred reset domain. The components will respond to the reset signal
'n_rst_c' via the local reset on the component and not the GSR component.
 
Type and number of components of the type:
Register = 4
 
Type and instance name of component:
Register : bttn_state_fifo[3]
Register : bttn_state_fifo_0io[0]
Register : bttn_state_fifo[1]
Register : bttn_state_fifo[2]
 
 
 
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
 
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Peak Memory Usage: 152 MB
 
 
 
299,41 → 336,6
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_pad.html
98,34 → 98,38
PACKAGE: CABGA381
Package Status: Final Version 1.36
 
Fri Jan 13 00:54:59 2017
Tue Jan 17 01:36:59 2017
 
Pinout by Port Name:
+---------------+----------+--------------+-------+-----------+-------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+-------------------------------+
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
+---------------+----------+--------------+-------+-----------+-------------------------------+
+---------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+---------------+----------+--------------+-------+-----------+---------------------------------+
 
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 2 | 2.5V |
| 3 | 2.5V |
| 6 | 2.5V |
| 8 | 2.5V |
280,7 → 284,7
| K5/6 | unused, PULL:DOWN | | | PL44B | VREF1_6/LDQ41 | |
| K18/2 | unused, PULL:DOWN | | | PR29D | RDQ29 | |
| K19/2 | unused, PULL:DOWN | | | PR32B | PCLKC2_1/RDQ29 | |
| K20/2 | unused, PULL:DOWN | | | PR32D | PCLKC2_0/RDQ29 | |
| K20/2 | n_rst | LOCATED | LVCMOS25_IN | PR32D | PCLKC2_0/RDQ29 | |
| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | |
| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | |
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | |
311,8 → 315,8
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | |
| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | |
| P3/6 | unused, PULL:DOWN | | | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | unused, PULL:DOWN | | | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
368,7 → 372,7
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | |
| T1/8 | unused, PULL:DOWN | | | PB4B | D6/IO6 | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | |
| T2/8 | unused, PULL:DOWN | | | PB13A | SN/CSN | |
| T3/8 | unused, PULL:DOWN | | | PB18A | WRITEN | |
| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | |
418,6 → 422,8
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
 
LOCATE COMP "button" SITE "T1";
LOCATE COMP "clk" SITE "P3";
LOCATE COMP "disp_data[0]" SITE "M20";
LOCATE COMP "disp_data[10]" SITE "N18";
LOCATE COMP "disp_data[11]" SITE "N17";
434,6 → 440,7
LOCATE COMP "disp_data[8]" SITE "N16";
LOCATE COMP "disp_data[9]" SITE "M17";
LOCATE COMP "disp_sel" SITE "J1";
LOCATE COMP "n_rst" SITE "K20";
 
 
 
445,7 → 452,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Fri Jan 13 00:54:59 2017
Tue Jan 17 01:36:59 2017
 
 
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_par.html
96,7 → 96,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Fri Jan 13 00:54:53 2017
Tue Jan 17 01:36:43 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
110,17 → 110,17
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 06 Complete
5_1 * 0 -1.238 7103 0.178 0 26 Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 6 secs
Total (real) run time for 1-seed: 26 secs
 
par done!
 
Lattice Place and Route Report for Design &quot;DisplayDriverwDecoder_impl1_map.ncd&quot;
Fri Jan 13 00:54:53 2017
Tue Jan 17 01:36:43 2017
 
 
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
147,34 → 147,39
 
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
 
PIO (prelim) 16/245 6% used
16/203 7% bonded
PIO (prelim) 20/245 8% used
20/203 9% bonded
IOLOGIC 1/245 &lt;1% used
 
SLICE 0/21924 0% used
SLICE 65/21924 &lt;1% used
 
GSR 1/1 100% used
 
 
Number of Signals: 0
Number of Connections: 0
Number of Signals: 131
Number of Connections: 657
 
Pin Constraint Summary:
16 out of 16 pins locked (100% locked).
19 out of 19 pins locked (100% locked).
 
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
 
No signal is selected as Global Set/Reset.
 
Signal n_rst_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 4 secs
 
Finished Placer Phase 0. REAL time: 5 secs
 
Starting Placer Phase 1.
.......................
Placer score = 63578.
Finished Placer Phase 1. REAL time: 15 secs
 
Placer score = 0.
Finished Placer Phase 1. REAL time: 5 secs
 
Starting Placer Phase 2.
.
Placer score = 0
Finished Placer Phase 2. REAL time: 5 secs
Placer score = 63553
Finished Placer Phase 2. REAL time: 15 secs
 
 
 
182,7 → 187,7
 
Global Clock Resources:
CLK_PIN : 0 out of 12 (0%)
GR_PCLK : 0 out of 12 (0%)
GR_PCLK : 1 out of 12 (8%)
PLL : 0 out of 4 (0%)
DCS : 0 out of 2 (0%)
DCC : 0 out of 60 (0%)
197,12 → 202,14
PRIMARY : 0 out of 16 (0%)
 
Quadrant BL Clocks:
PRIMARY &quot;clk_c&quot; from comp &quot;clk&quot; on PIO site &quot;P3 (PL68C)&quot;, CLK/CE/SR load = 1
 
PRIMARY : 0 out of 16 (0%)
PRIMARY : 1 out of 16 (6%)
 
Quadrant BR Clocks:
PRIMARY &quot;clk_c&quot; from comp &quot;clk&quot; on PIO site &quot;P3 (PL68C)&quot;, CLK/CE/SR load = 8
 
PRIMARY : 0 out of 16 (0%)
PRIMARY : 1 out of 16 (6%)
 
Edge Clocks:
 
214,9 → 221,9
 
+
I/O Usage Summary (final):
16 out of 245 (6.5%) PIO sites used.
16 out of 203 (7.9%) bonded PIO sites used.
Number of PIO comps: 16; differential: 0.
20 out of 245 (8.2%) PIO sites used.
20 out of 203 (9.9%) bonded PIO sites used.
Number of PIO comps: 19; differential: 1.
Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
225,20 → 232,104
+----------+----------------+------------+------------+------------+
| 0 | 0 / 27 ( 0%) | - | - | - |
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 0 / 32 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 1 / 33 ( 3%) | 2.5V | - | - |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 1 / 13 ( 7%) | 2.5V | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 3 secs
Total placer CPU time: 15 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
Timing score: 0
0 connections routed; 657 unrouted.
Starting router resource preassignment
 
Completed router resource preassignment. Real time: 23 secs
 
Start NBR router at 01:37:06 01/17/17
 
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
 
Start NBR special constraint process at 01:37:06 01/17/17
 
Start NBR section for initial routing at 01:37:06 01/17/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.227ns/-8.380ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
 
Start NBR section for normal routing at 01:37:07 01/17/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for re-routing at 01:37:07 01/17/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for post-routing at 01:37:07 01/17/17
 
End NBR router with 0 unrouted connection
 
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 9 (1.37%)
Estimated worst slack&lt;setup&gt; : -1.238ns
Timing score&lt;setup&gt; : 7103
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
 
 
 
Total CPU time 24 secs
Total REAL time: 25 secs
Completely routed.
End of route. 657 routed (100.00%); 0 unrouted.
 
Hold time timing score: 0, hold timing errors: 0
 
Timing score: 7103
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
 
247,14 → 338,14
 
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = -1.238
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 7.103
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.178
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
 
Total CPU time to completion: 4 secs
Total REAL time to completion: 6 secs
Total CPU time to completion: 25 secs
Total REAL time to completion: 26 secs
 
par done!
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_scck.rpt
1,7 → 1,7
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Fri Jan 13 00:54:39 2017
# Written on Tue Jan 17 01:19:11 2017
 
 
##### DESIGN INFO #######################################################
21,8 → 21,8
Clock Summary
*************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_summary.html
146,7 → 146,7
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2017/01/13 00:56:27</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2017/01/17 01:51:23</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_synplify.html
96,7 → 96,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
#Implementation: impl1
 
110,27 → 110,42
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
137,7 → 152,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
@END
147,7 → 162,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:37 2017
# Tue Jan 17 01:19:09 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
159,7 → 174,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Pre-mapping Report
182,10 → 197,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
199,13 → 214,13
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
221,7 → 236,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:39 2017
# Tue Jan 17 01:19:11 2017
 
###########################################################]
Map & Optimize Report
258,6 → 273,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
287,12 → 303,22
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
 
3 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.64ns 1 / 9
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
 
301,15 → 327,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
319,7 → 345,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
326,21 → 352,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 13 00:54:42 2017
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1220.4 MHz
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
354,13 → 380,13
*******************
 
 
Worst slack in design: -0.145
Worst slack in design: -0.398
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
369,12 → 395,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
===========================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
388,7 → 414,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
 
 
396,37 → 422,38
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
 
 
 
435,128 → 462,179
 
 
Path information for path number 1:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (critical) : -0.398
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.819
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.608
= Required time: 2.044
 
- Propagation time: 0.753
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.145
= Slack (non-critical) : -0.339
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
===========================================================================================
 
 
 
565,36 → 643,37
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
 
Details:
FD1S3IX: 5
FD1S3JX: 3
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:42 2017
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
 
###########################################################]
 
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_synplify.lpf
3,7 → 3,7
#
 
# Period Constraints
#FREQUENCY PORT "clk" 1220.4 MHz;
#FREQUENCY PORT "button" 443.5 MHz;
 
 
# Output Constraints
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_synplify.tcl
46,6 → 46,8
add_file -vhdl {C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd}
 
#-- top module name
set_option -top_module DisplayDriverWrapper
/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_tw1.html
106,7 → 106,7
 
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3</big></U></B>
Fri Jan 13 00:54:52 2017
Tue Jan 17 01:36:41 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
125,10 → 125,10
 
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
 
<LI><A href='#map_twr_pref_0_0' Target='right'>Default path enumeration(0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY NET "clk_c" 369.959000 MHz (0 errors)</A></LI> 68 items scored, 0 timing errors detected.
Report: 370.096MHz is the maximum frequency for this preference.
 
<LI><A href='#map_twr_pref_0_1' Target='right'>Default net enumeration(0 errors)</A></LI> 0 items scored, 0 timing errors detected.
 
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
136,16 → 136,52
 
 
================================================================================
<A name="map_twr_pref_0_0"></A>Preference: Default path enumeration
0 items scored, 0 timing errors detected.
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
================================================================================
<A name="map_twr_pref_0_1"></A>Preference: Default net enumeration
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.001ns
The internal maximum frequency of the following component is 370.096 MHz
 
Logical Details: Cell type Pin name Component name
 
Destination: SIOLOGIC CLK button_MGIOL
 
Delay: 2.702ns -- based on Minimum Pulse Width
 
 
Passed: The following path meets requirements by 1.063ns
 
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
 
Source: FF Q bttn_state (from clk_c +)
Destination: FF Data in symbol_scan_cntr[7] (to clk_c +)
 
Delay: 1.749ns (43.2% logic, 56.8% route), 3 logic levels.
 
Constraint Details:
 
1.749ns physical path delay SLICE_7 to SLICE_0 meets
2.703ns delay constraint less
-0.109ns CE_SET requirement (totaling 2.812ns) by 1.063ns
 
Physical Path Details:
 
Data path SLICE_7 to SLICE_0:
 
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.395 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from clk_c)
ROUTE 1 e 0.419 SLICE_7.Q0 to SLICE_64.B1 bttn_state_i
CTOF_DEL --- 0.180 SLICE_64.B1 to SLICE_64.F1 SLICE_64
ROUTE 1 e 0.156 SLICE_64.F1 to SLICE_64.A0 G_15_1
CTOF_DEL --- 0.180 SLICE_64.A0 to SLICE_64.F0 SLICE_64
ROUTE 5 e 0.419 SLICE_64.F0 to SLICE_0.CE bttn_state_fifo_0io_RNIB9K02[0] (to clk_c)
--------
1.749 (43.2% logic, 56.8% route), 3 logic levels.
 
Report: 370.096MHz is the maximum frequency for this preference.
 
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
152,10 → 188,8
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
Default path enumeration | -| -| 0
FREQUENCY NET "clk_c" 369.959000 MHz ; | 369.959 MHz| 370.096 MHz| 0
| | |
Default net enumeration | -| -| 0
| | |
----------------------------------------------------------------------------
 
 
165,9 → 199,12
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
 
Found 0 clocks:
Found 1 clocks:
 
Clock Domain: clk_c Source: clk.PAD Loads: 9
Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
 
 
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
 
174,13 → 211,114
Timing errors: 0 Score: 0
Cumulative negative slack: 0
 
Constraints cover 0 paths, 0 nets, and 0 connections (100.00% coverage)
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
 
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3</big></U></B>
Tue Jan 17 01:36:42 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
 
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
Design file: displaydriverwdecoder_impl1_map.ncd
Preference file: displaydriverwdecoder_impl1.prf
Device,speed: LFE5UM5G-45F,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
 
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
 
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "clk_c" 369.959000 MHz (0 errors)</A></LI> 68 items scored, 0 timing errors detected.
 
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
 
 
 
================================================================================
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
Passed: The following path meets requirements by 0.104ns
 
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
 
Source: FF Q bttn_state_fifo[1] (from clk_c +)
Destination: FF Data in bttn_state_fifo[2] (to clk_c +)
 
Delay: 0.222ns (73.9% logic, 26.1% route), 1 logic levels.
 
Constraint Details:
 
0.222ns physical path delay SLICE_5 to SLICE_5 meets
0.118ns M_HLD and
0.000ns delay constraint requirement (totaling 0.118ns) by 0.104ns
 
Physical Path Details:
 
Data path SLICE_5 to SLICE_5:
 
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.164 SLICE_5.CLK to SLICE_5.Q0 SLICE_5 (from clk_c)
ROUTE 3 e 0.058 SLICE_5.Q0 to SLICE_5.M1 bttn_state_fifo[1] (to clk_c)
--------
0.222 (73.9% logic, 26.1% route), 1 logic levels.
 
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_c" 369.959000 MHz ; | 0.000 ns| 0.104 ns| 1
| | |
----------------------------------------------------------------------------
 
 
All preferences were met.
 
 
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
 
Found 1 clocks:
 
Clock Domain: clk_c Source: clk.PAD Loads: 9
Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
 
 
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
 
Timing errors: 0 Score: 0
Cumulative negative slack: 0
 
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
 
 
 
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
 
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
 
 
<BR>
<BR>
<BR>
/Lattice_FPGA_Build/impl1/hdla_gen_hierarchy.html
43,14 → 43,92
INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.vhd
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(12,8-12,27) (VHDL-1012) analyzing entity distromasciidecoder
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(18,14-18,23) (VHDL-1010) analyzing architecture structure
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd(15,8-15,20) (VHDL-1012) analyzing entity asciidecoder
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd(28,14-28,18) (VHDL-1010) analyzing architecture arch
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(16,8-16,33) (VHDL-1012) analyzing entity displaydriverwdecoder_top
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(50,14-50,18) (VHDL-1010) analyzing architecture arch
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(51,14-51,18) (VHDL-1010) analyzing architecture arch
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(15,8-15,28) (VHDL-1012) analyzing entity displaydriverwrapper
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(37,14-37,18) (VHDL-1010) analyzing architecture arch
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(15,8-15,28) (VHDL-1067) elaborating DisplayDriverWrapper(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(16,8-16,33) (VHDL-1067) elaborating DisplayDriverwDecoder_Top_uniq_0(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd(15,8-15,20) (VHDL-1067) elaborating ASCIIDecoder_uniq_0(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(12,8-12,27) (VHDL-1067) elaborating DistRomAsciiDecoder_uniq_0(Structure)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(25,5-29,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_1
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_1'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(25,5-29,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(31,5-35,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_2
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_2'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(31,5-35,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(37,5-41,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_3
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_3'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(37,5-41,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(43,5-47,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_4
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_4'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(43,5-47,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(49,5-53,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_5
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_5'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(49,5-53,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(55,5-59,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_6
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_6'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(55,5-59,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(61,5-65,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_7
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_7'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(61,5-65,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(67,5-71,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_8
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_8'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(67,5-71,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(73,5-77,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_9
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_9'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(73,5-77,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(79,5-83,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_10
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_10'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(79,5-83,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(85,5-89,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_11
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_11'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(85,5-89,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(91,5-95,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_12
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_12'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(91,5-95,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(97,5-101,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_13
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_13'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(97,5-101,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(103,5-107,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_14
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_14'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(103,5-107,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_1'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_2'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_3'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_4'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_5'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_6'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_7'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_8'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_9'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_10'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_11'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_12'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_13'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_14'
Done: design load finished with (0) errors, and (0) warnings
 
</PRE></BODY></HTML>
/Lattice_FPGA_Build/impl1/impl1.areasrr
1,30 → 1,57
----------------------------------------------------------------------
Report for cell DisplayDriverWrapper.arch
 
Register bits: 8 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 17
I/O cells: 19
Cell usage:
cell count Res Usage(%)
FD1S3IX 5 100.0
CCU2C 5 100.0
FD1P3DX 8 100.0
FD1S3AX 1 100.0
FD1S3JX 3 100.0
GSR 1 100.0
IB 2 100.0
OB 15 100.0
IB 3 100.0
IFS1P3JX 1 100.0
INV 2 100.0
OB 16 100.0
ORCALUT4 4 100.0
PUR 1 100.0
VHI 2 100.0
ROM128X1A 14 100.0
VHI 1 100.0
VLO 1 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DisplayDriverwDecoder_Top 1 100.0
DistRomAsciiDecoder 1 100.0
TOTAL 31
TOTAL 64
----------------------------------------------------------------------
Report for cell DisplayDriverwDecoder_Top.netlist
Instance path: DDwD_Top
Cell usage:
cell count Res Usage(%)
FD1S3IX 5 100.0
FD1S3JX 3 100.0
VHI 1 50.0
ROM128X1A 14 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DistRomAsciiDecoder 1 100.0
TOTAL 9
TOTAL 16
----------------------------------------------------------------------
Report for cell ASCIIDecoder.netlist
Instance path: DDwD_Top.ascii_decoder_module
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
SUB MODULES
DistRomAsciiDecoder 1 100.0
TOTAL 15
----------------------------------------------------------------------
Report for cell DistRomAsciiDecoder.netlist
Instance path: DDwD_Top.ascii_decoder_module.rom_decoding_table
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
TOTAL 14
/Lattice_FPGA_Build/impl1/impl1.edi
4,7 → 4,7
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2017 1 8 0 49 36)
(timeStamp 2017 1 17 1 29 39)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "L-2016.03L-1, mapper maplat, Build 1498R"))
)
12,6 → 12,42
(library LUCENT
(edifLevel 0)
(technology (numberDefinition ))
(cell ROM128X1A (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port AD0 (direction INPUT))
(port AD1 (direction INPUT))
(port AD2 (direction INPUT))
(port AD3 (direction INPUT))
(port AD4 (direction INPUT))
(port AD5 (direction INPUT))
(port AD6 (direction INPUT))
(port DO0 (direction OUTPUT))
)
)
)
(cell CCU2C (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port A0 (direction INPUT))
(port B0 (direction INPUT))
(port C0 (direction INPUT))
(port D0 (direction INPUT))
(port A1 (direction INPUT))
(port B1 (direction INPUT))
(port C1 (direction INPUT))
(port D1 (direction INPUT))
(port CIN (direction INPUT))
(port COUT (direction OUTPUT))
(port S0 (direction OUTPUT))
(port S1 (direction OUTPUT))
)
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0000"))
(property INIT0 (string "0000"))
)
)
(cell OB (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
38,16 → 74,48
)
)
)
(cell FD1S3IX (cellType GENERIC)
(cell FD1S3AX (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port D (direction INPUT))
(port CK (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell IFS1P3JX (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port D (direction INPUT))
(port SP (direction INPUT))
(port SCLK (direction INPUT))
(port PD (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FD1P3DX (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port D (direction INPUT))
(port SP (direction INPUT))
(port CK (direction INPUT))
(port CD (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell ORCALUT4 (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port C (direction INPUT))
(port D (direction INPUT))
(port Z (direction OUTPUT))
)
)
)
(cell GSR (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
55,6 → 123,14
)
)
)
(cell INV (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port A (direction INPUT))
(port Z (direction OUTPUT))
)
)
)
(cell VHI (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
73,85 → 149,426
(library work
(edifLevel 0)
(technology (numberDefinition ))
(cell DisplayDriverwDecoder_Top (cellType GENERIC)
(cell DistRomAsciiDecoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port clk_c (direction INPUT))
(port rst_c (direction INPUT))
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance (rename ascii_reg_0 "ascii_reg[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_13 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xDA3FFFFFBA3FFFFFB7FE6997BFFFFFFE"))
)
(instance (rename ascii_reg_1 "ascii_reg[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
(instance mem_0_12 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xEDEFFDEBFDEFFDEB7BFFB3E718FFD7FF"))
)
(instance (rename ascii_reg_2 "ascii_reg[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_11 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xF679B7FFEE79B7FFEFDFFA97BFFFFFDF"))
)
(instance (rename ascii_reg_3 "ascii_reg[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_10 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xF0BFD7FFB8BFD7FFEFFE7A176DFFFFFE"))
)
(instance (rename ascii_reg_4 "ascii_reg[4]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
(instance mem_0_9 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xEFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF"))
)
(instance (rename ascii_reg_5 "ascii_reg[5]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_8 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xDCFF9FFEECFF9FFFBFFFF9976DFFFFFF"))
)
(instance (rename ascii_reg_6 "ascii_reg[6]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
(instance mem_0_7 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x9FF2FE59FFF2FE585CA3D3C7D0FFB0A3"))
)
(instance (rename ascii_reg_7 "ascii_reg[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
(instance mem_0_6 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0xB7F2F69DFFF2F69DDC8B93C7D0FF388B"))
)
(instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
(net (rename ascii_reg_0 "ascii_reg[0]") (joined
(portRef Q (instanceRef ascii_reg_0))
(portRef D (instanceRef ascii_reg_0))
(instance mem_0_5 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7F100615F7100614FC8EFFC3E3FF288E"))
)
(instance mem_0_4 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x3F180215F7180214FEBABFF7EBFF2ABA"))
)
(instance mem_0_3 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7BD56B4353D56B42DC92BFA7DAFF8492"))
)
(instance mem_0_2 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7F551A69DF551A69FC24FF85FFFFD024"))
)
(instance mem_0_1 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x3F581AE99F581AE87C60FFF5F7FFD060"))
)
(instance mem_0_0 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
(property initval (string "0x7BE07F0193E07F007C12FFA7F2FF0012"))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
(portRef AD0 (instanceRef mem_0_0))
(portRef AD0 (instanceRef mem_0_1))
(portRef AD0 (instanceRef mem_0_2))
(portRef AD0 (instanceRef mem_0_3))
(portRef AD0 (instanceRef mem_0_4))
(portRef AD0 (instanceRef mem_0_5))
(portRef AD0 (instanceRef mem_0_6))
(portRef AD0 (instanceRef mem_0_7))
(portRef AD0 (instanceRef mem_0_8))
(portRef AD0 (instanceRef mem_0_9))
(portRef AD0 (instanceRef mem_0_10))
(portRef AD0 (instanceRef mem_0_11))
(portRef AD0 (instanceRef mem_0_12))
(portRef AD0 (instanceRef mem_0_13))
))
(net clk_c (joined
(portRef clk_c)
(portRef CK (instanceRef ascii_reg_7))
(portRef CK (instanceRef ascii_reg_6))
(portRef CK (instanceRef ascii_reg_5))
(portRef CK (instanceRef ascii_reg_4))
(portRef CK (instanceRef ascii_reg_3))
(portRef CK (instanceRef ascii_reg_2))
(portRef CK (instanceRef ascii_reg_1))
(portRef CK (instanceRef ascii_reg_0))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef (member symbol_scan_cntr 5))
(portRef AD1 (instanceRef mem_0_0))
(portRef AD1 (instanceRef mem_0_1))
(portRef AD1 (instanceRef mem_0_2))
(portRef AD1 (instanceRef mem_0_3))
(portRef AD1 (instanceRef mem_0_4))
(portRef AD1 (instanceRef mem_0_5))
(portRef AD1 (instanceRef mem_0_6))
(portRef AD1 (instanceRef mem_0_7))
(portRef AD1 (instanceRef mem_0_8))
(portRef AD1 (instanceRef mem_0_9))
(portRef AD1 (instanceRef mem_0_10))
(portRef AD1 (instanceRef mem_0_11))
(portRef AD1 (instanceRef mem_0_12))
(portRef AD1 (instanceRef mem_0_13))
))
(net rst_c (joined
(portRef rst_c)
(portRef CD (instanceRef ascii_reg_7))
(portRef PD (instanceRef ascii_reg_6))
(portRef CD (instanceRef ascii_reg_5))
(portRef PD (instanceRef ascii_reg_4))
(portRef CD (instanceRef ascii_reg_3))
(portRef CD (instanceRef ascii_reg_2))
(portRef PD (instanceRef ascii_reg_1))
(portRef CD (instanceRef ascii_reg_0))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef (member symbol_scan_cntr 4))
(portRef AD2 (instanceRef mem_0_0))
(portRef AD2 (instanceRef mem_0_1))
(portRef AD2 (instanceRef mem_0_2))
(portRef AD2 (instanceRef mem_0_3))
(portRef AD2 (instanceRef mem_0_4))
(portRef AD2 (instanceRef mem_0_5))
(portRef AD2 (instanceRef mem_0_6))
(portRef AD2 (instanceRef mem_0_7))
(portRef AD2 (instanceRef mem_0_8))
(portRef AD2 (instanceRef mem_0_9))
(portRef AD2 (instanceRef mem_0_10))
(portRef AD2 (instanceRef mem_0_11))
(portRef AD2 (instanceRef mem_0_12))
(portRef AD2 (instanceRef mem_0_13))
))
(net (rename ascii_reg_1 "ascii_reg[1]") (joined
(portRef Q (instanceRef ascii_reg_1))
(portRef D (instanceRef ascii_reg_1))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef (member symbol_scan_cntr 3))
(portRef AD3 (instanceRef mem_0_0))
(portRef AD3 (instanceRef mem_0_1))
(portRef AD3 (instanceRef mem_0_2))
(portRef AD3 (instanceRef mem_0_3))
(portRef AD3 (instanceRef mem_0_4))
(portRef AD3 (instanceRef mem_0_5))
(portRef AD3 (instanceRef mem_0_6))
(portRef AD3 (instanceRef mem_0_7))
(portRef AD3 (instanceRef mem_0_8))
(portRef AD3 (instanceRef mem_0_9))
(portRef AD3 (instanceRef mem_0_10))
(portRef AD3 (instanceRef mem_0_11))
(portRef AD3 (instanceRef mem_0_12))
(portRef AD3 (instanceRef mem_0_13))
))
(net (rename ascii_reg_2 "ascii_reg[2]") (joined
(portRef Q (instanceRef ascii_reg_2))
(portRef D (instanceRef ascii_reg_2))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef (member symbol_scan_cntr 2))
(portRef AD4 (instanceRef mem_0_0))
(portRef AD4 (instanceRef mem_0_1))
(portRef AD4 (instanceRef mem_0_2))
(portRef AD4 (instanceRef mem_0_3))
(portRef AD4 (instanceRef mem_0_4))
(portRef AD4 (instanceRef mem_0_5))
(portRef AD4 (instanceRef mem_0_6))
(portRef AD4 (instanceRef mem_0_7))
(portRef AD4 (instanceRef mem_0_8))
(portRef AD4 (instanceRef mem_0_9))
(portRef AD4 (instanceRef mem_0_10))
(portRef AD4 (instanceRef mem_0_11))
(portRef AD4 (instanceRef mem_0_12))
(portRef AD4 (instanceRef mem_0_13))
))
(net (rename ascii_reg_3 "ascii_reg[3]") (joined
(portRef Q (instanceRef ascii_reg_3))
(portRef D (instanceRef ascii_reg_3))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef (member symbol_scan_cntr 1))
(portRef AD5 (instanceRef mem_0_0))
(portRef AD5 (instanceRef mem_0_1))
(portRef AD5 (instanceRef mem_0_2))
(portRef AD5 (instanceRef mem_0_3))
(portRef AD5 (instanceRef mem_0_4))
(portRef AD5 (instanceRef mem_0_5))
(portRef AD5 (instanceRef mem_0_6))
(portRef AD5 (instanceRef mem_0_7))
(portRef AD5 (instanceRef mem_0_8))
(portRef AD5 (instanceRef mem_0_9))
(portRef AD5 (instanceRef mem_0_10))
(portRef AD5 (instanceRef mem_0_11))
(portRef AD5 (instanceRef mem_0_12))
(portRef AD5 (instanceRef mem_0_13))
))
(net (rename ascii_reg_4 "ascii_reg[4]") (joined
(portRef Q (instanceRef ascii_reg_4))
(portRef D (instanceRef ascii_reg_4))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef (member symbol_scan_cntr 0))
(portRef AD6 (instanceRef mem_0_0))
(portRef AD6 (instanceRef mem_0_1))
(portRef AD6 (instanceRef mem_0_2))
(portRef AD6 (instanceRef mem_0_3))
(portRef AD6 (instanceRef mem_0_4))
(portRef AD6 (instanceRef mem_0_5))
(portRef AD6 (instanceRef mem_0_6))
(portRef AD6 (instanceRef mem_0_7))
(portRef AD6 (instanceRef mem_0_8))
(portRef AD6 (instanceRef mem_0_9))
(portRef AD6 (instanceRef mem_0_10))
(portRef AD6 (instanceRef mem_0_11))
(portRef AD6 (instanceRef mem_0_12))
(portRef AD6 (instanceRef mem_0_13))
))
(net (rename ascii_reg_5 "ascii_reg[5]") (joined
(portRef Q (instanceRef ascii_reg_5))
(portRef D (instanceRef ascii_reg_5))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef DO0 (instanceRef mem_0_13))
(portRef (member disp_data_c 0))
))
(net (rename ascii_reg_6 "ascii_reg[6]") (joined
(portRef Q (instanceRef ascii_reg_6))
(portRef D (instanceRef ascii_reg_6))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef DO0 (instanceRef mem_0_12))
(portRef (member disp_data_c 1))
))
(net (rename ascii_reg_7 "ascii_reg[7]") (joined
(portRef Q (instanceRef ascii_reg_7))
(portRef D (instanceRef ascii_reg_7))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef DO0 (instanceRef mem_0_11))
(portRef (member disp_data_c 2))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef DO0 (instanceRef mem_0_10))
(portRef (member disp_data_c 3))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef DO0 (instanceRef mem_0_9))
(portRef (member disp_data_c 4))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef DO0 (instanceRef mem_0_8))
(portRef (member disp_data_c 5))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef DO0 (instanceRef mem_0_7))
(portRef (member disp_data_c 6))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef DO0 (instanceRef mem_0_6))
(portRef (member disp_data_c 7))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef DO0 (instanceRef mem_0_5))
(portRef (member disp_data_c 8))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef DO0 (instanceRef mem_0_4))
(portRef (member disp_data_c 9))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef DO0 (instanceRef mem_0_3))
(portRef (member disp_data_c 10))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef DO0 (instanceRef mem_0_2))
(portRef (member disp_data_c 11))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef DO0 (instanceRef mem_0_1))
(portRef (member disp_data_c 12))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef DO0 (instanceRef mem_0_0))
(portRef (member disp_data_c 13))
))
)
(property NGD_DRC_MASK (integer 1))
(property orig_inst_of (string "DistRomAsciiDecoder"))
)
)
(cell ASCIIDecoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance rom_decoding_table (viewRef netlist (cellRef DistRomAsciiDecoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
(portRef (member symbol_scan_cntr 6) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef (member symbol_scan_cntr 5))
(portRef (member symbol_scan_cntr 5) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef (member symbol_scan_cntr 4))
(portRef (member symbol_scan_cntr 4) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef (member symbol_scan_cntr 3))
(portRef (member symbol_scan_cntr 3) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef (member symbol_scan_cntr 2))
(portRef (member symbol_scan_cntr 2) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef (member symbol_scan_cntr 1))
(portRef (member symbol_scan_cntr 1) (instanceRef rom_decoding_table))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef (member symbol_scan_cntr 0))
(portRef (member symbol_scan_cntr 0) (instanceRef rom_decoding_table))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 13))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 12))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 11))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 10))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 9))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 8))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 7))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 6))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 5))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 4))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 3))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 2))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 1))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 0))
))
)
(property orig_inst_of (string "ASCIIDecoder"))
)
)
(cell DisplayDriverwDecoder_Top (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance ascii_decoder_module (viewRef netlist (cellRef ASCIIDecoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
(portRef (member symbol_scan_cntr 6) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef (member symbol_scan_cntr 5))
(portRef (member symbol_scan_cntr 5) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef (member symbol_scan_cntr 4))
(portRef (member symbol_scan_cntr 4) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef (member symbol_scan_cntr 3))
(portRef (member symbol_scan_cntr 3) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef (member symbol_scan_cntr 2))
(portRef (member symbol_scan_cntr 2) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef (member symbol_scan_cntr 1))
(portRef (member symbol_scan_cntr 1) (instanceRef ascii_decoder_module))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef (member symbol_scan_cntr 0))
(portRef (member symbol_scan_cntr 0) (instanceRef ascii_decoder_module))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 13))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 12))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 11))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 10))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 9))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 8))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 7))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 6))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 5))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 4))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 3))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 2))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 1))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 0))
))
)
(property orig_inst_of (string "DisplayDriverwDecoder_Top"))
)
)
159,17 → 576,47
(view arch (viewType NETLIST)
(interface
(port clk (direction INPUT))
(port rst (direction INPUT))
(port n_rst (direction INPUT))
(port button (direction INPUT))
(port (array (rename disp_data "disp_data(13:0)") 14) (direction OUTPUT))
(port (array (rename disp_data "disp_data(14:0)") 15) (direction OUTPUT))
(port disp_sel (direction OUTPUT))
)
(contents
(instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
(instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
(instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
(instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
)
(instance (rename disp_data_pad_RNO_14 "disp_data_pad_RNO[14]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance n_rst_pad_RNIQVTF (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance (rename bttn_state_fifo_0io_0 "bttn_state_fifo_0io[0]") (viewRef PRIM (cellRef IFS1P3JX (libraryRef LUCENT)))
(property IOB (string "FALSE"))
)
(instance (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename symbol_scan_cntr_7 "symbol_scan_cntr[7]") (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
)
(instance (rename bttn_state_fifo_1 "bttn_state_fifo[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
)
(instance (rename bttn_state_fifo_2 "bttn_state_fifo[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
)
(instance (rename bttn_state_fifo_3 "bttn_state_fifo[3]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
)
(instance bttn_state (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
)
(instance disp_sel_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_14 "disp_data_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_13 "disp_data_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_12 "disp_data_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_11 "disp_data_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
184,106 → 631,394
(instance (rename disp_data_pad_2 "disp_data_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_1 "disp_data_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_0 "disp_data_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance rst_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance button_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance n_rst_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
)
(instance bttn_stateand (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (!C (!B !A)))"))
)
(instance bttn_stateand_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B !A)"))
)
(instance bttn_state_RNIO8V61 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(C (!B !A))"))
)
(instance (rename bttn_state_fifo_0io_RNIB9K02_0 "bttn_state_fifo_0io_RNIB9K02[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C (!B A)))"))
)
(instance (rename symbol_scan_cntr_cry_0_0 "symbol_scan_cntr_cry_0[0]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0x500c"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_cry_0_1 "symbol_scan_cntr_cry_0[1]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa003"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_cry_0_3 "symbol_scan_cntr_cry_0[3]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa003"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_cry_0_5 "symbol_scan_cntr_cry_0[5]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa003"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0xa003"))
)
(instance (rename symbol_scan_cntr_s_0_7 "symbol_scan_cntr_s_0[7]") (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
(property INIT0 (string "0xa00a"))
(property INJECT1_1 (string "NO"))
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0x5003"))
)
(instance DDwD_Top (viewRef netlist (cellRef DisplayDriverwDecoder_Top))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef Q (instanceRef symbol_scan_cntr_0))
(portRef (member symbol_scan_cntr 6) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_0))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef Q (instanceRef symbol_scan_cntr_1))
(portRef (member symbol_scan_cntr 5) (instanceRef DDwD_Top))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef Q (instanceRef symbol_scan_cntr_2))
(portRef (member symbol_scan_cntr 4) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef Q (instanceRef symbol_scan_cntr_3))
(portRef (member symbol_scan_cntr 3) (instanceRef DDwD_Top))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef Q (instanceRef symbol_scan_cntr_4))
(portRef (member symbol_scan_cntr 2) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef Q (instanceRef symbol_scan_cntr_5))
(portRef (member symbol_scan_cntr 1) (instanceRef DDwD_Top))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef Q (instanceRef symbol_scan_cntr_6))
(portRef (member symbol_scan_cntr 0) (instanceRef DDwD_Top))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_7 "symbol_scan_cntr[7]") (joined
(portRef Q (instanceRef symbol_scan_cntr_7))
(portRef A0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef A (instanceRef disp_data_pad_RNO_14))
))
(net (rename bttn_state_fifo_0 "bttn_state_fifo[0]") (joined
(portRef Q (instanceRef bttn_state_fifo_0io_0))
(portRef B (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef A (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state_fifo_1))
))
(net (rename bttn_state_fifo_1 "bttn_state_fifo[1]") (joined
(portRef Q (instanceRef bttn_state_fifo_1))
(portRef C (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef B (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state_fifo_2))
))
(net (rename bttn_state_fifo_2 "bttn_state_fifo[2]") (joined
(portRef Q (instanceRef bttn_state_fifo_2))
(portRef D (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef C (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state_fifo_3))
))
(net (rename bttn_state_fifo_3 "bttn_state_fifo[3]") (joined
(portRef Q (instanceRef bttn_state_fifo_3))
(portRef A (instanceRef bttn_state_RNIO8V61))
(portRef A (instanceRef bttn_stateand_2_0))
))
(net bttn_state_i (joined
(portRef Q (instanceRef bttn_state))
(portRef B (instanceRef bttn_state_RNIO8V61))
))
(net bttn_stateand (joined
(portRef Z (instanceRef bttn_stateand))
(portRef D (instanceRef bttn_state))
))
(net (rename bttn_state_fifo_0io_RNIB9K02_0 "bttn_state_fifo_0io_RNIB9K02[0]") (joined
(portRef Z (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
(portRef SP (instanceRef symbol_scan_cntr_7))
(portRef SP (instanceRef symbol_scan_cntr_6))
(portRef SP (instanceRef symbol_scan_cntr_5))
(portRef SP (instanceRef symbol_scan_cntr_4))
(portRef SP (instanceRef symbol_scan_cntr_3))
(portRef SP (instanceRef symbol_scan_cntr_2))
(portRef SP (instanceRef symbol_scan_cntr_1))
(portRef SP (instanceRef symbol_scan_cntr_0))
))
(net (rename symbol_scan_cntr_cry_0 "symbol_scan_cntr_cry[0]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_0))
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_s_0 "symbol_scan_cntr_s[0]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef D (instanceRef symbol_scan_cntr_0))
))
(net (rename symbol_scan_cntr_s_1 "symbol_scan_cntr_s[1]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D (instanceRef symbol_scan_cntr_1))
))
(net (rename symbol_scan_cntr_cry_2 "symbol_scan_cntr_cry[2]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_1))
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_s_2 "symbol_scan_cntr_s[2]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D (instanceRef symbol_scan_cntr_2))
))
(net (rename symbol_scan_cntr_s_3 "symbol_scan_cntr_s[3]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D (instanceRef symbol_scan_cntr_3))
))
(net (rename symbol_scan_cntr_cry_4 "symbol_scan_cntr_cry[4]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_3))
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_s_4 "symbol_scan_cntr_s[4]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D (instanceRef symbol_scan_cntr_4))
))
(net (rename symbol_scan_cntr_s_5 "symbol_scan_cntr_s[5]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D (instanceRef symbol_scan_cntr_5))
))
(net (rename symbol_scan_cntr_cry_6 "symbol_scan_cntr_cry[6]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_cry_0_5))
(portRef CIN (instanceRef symbol_scan_cntr_s_0_7))
))
(net (rename symbol_scan_cntr_s_6 "symbol_scan_cntr_s[6]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D (instanceRef symbol_scan_cntr_6))
))
(net (rename symbol_scan_cntr_s_7 "symbol_scan_cntr_s[7]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef D (instanceRef symbol_scan_cntr_7))
))
(net bttn_stateand_2_0 (joined
(portRef Z (instanceRef bttn_stateand_2_0))
(portRef D (instanceRef bttn_stateand))
))
(net (rename symbol_scan_cntr_cry_0_S0_0 "symbol_scan_cntr_cry_0_S0[0]") (joined
(portRef S0 (instanceRef symbol_scan_cntr_cry_0_0))
))
(net (rename symbol_scan_cntr_s_0_S1_7 "symbol_scan_cntr_s_0_S1[7]") (joined
(portRef S1 (instanceRef symbol_scan_cntr_s_0_7))
))
(net (rename symbol_scan_cntr_s_0_COUT_7 "symbol_scan_cntr_s_0_COUT[7]") (joined
(portRef COUT (instanceRef symbol_scan_cntr_s_0_7))
))
(net G_15_1 (joined
(portRef Z (instanceRef bttn_state_RNIO8V61))
(portRef A (instanceRef bttn_state_fifo_0io_RNIB9K02_0))
))
(net VCC (joined
(portRef Z (instanceRef VCC))
(portRef D1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef C1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef B1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef A1 (instanceRef symbol_scan_cntr_s_0_7))
(portRef D0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef C0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef B0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_5))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_3))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_1))
(portRef D1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef C1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef B1 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef D0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef C0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef B0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_0))
(portRef SP (instanceRef bttn_state_fifo_0io_0))
(portRef GSR (instanceRef GSR_INST))
))
(net GND (joined
(portRef Z (instanceRef GND))
(portRef I (instanceRef disp_data_pad_0))
(portRef I (instanceRef disp_data_pad_1))
(portRef I (instanceRef disp_data_pad_2))
(portRef I (instanceRef disp_data_pad_3))
(portRef I (instanceRef disp_data_pad_4))
(portRef I (instanceRef disp_data_pad_5))
(portRef I (instanceRef disp_data_pad_6))
(portRef I (instanceRef disp_data_pad_7))
(portRef I (instanceRef disp_data_pad_8))
(portRef I (instanceRef disp_data_pad_9))
(portRef I (instanceRef disp_data_pad_10))
(portRef I (instanceRef disp_data_pad_11))
(portRef I (instanceRef disp_data_pad_12))
(portRef I (instanceRef disp_data_pad_13))
(portRef I (instanceRef disp_sel_pad))
))
(net clk_c (joined
(portRef O (instanceRef clk_pad))
(portRef clk_c (instanceRef DDwD_Top))
(portRef CK (instanceRef bttn_state))
(portRef CK (instanceRef bttn_state_fifo_3))
(portRef CK (instanceRef bttn_state_fifo_2))
(portRef CK (instanceRef bttn_state_fifo_1))
(portRef CK (instanceRef symbol_scan_cntr_7))
(portRef CK (instanceRef symbol_scan_cntr_6))
(portRef CK (instanceRef symbol_scan_cntr_5))
(portRef CK (instanceRef symbol_scan_cntr_4))
(portRef CK (instanceRef symbol_scan_cntr_3))
(portRef CK (instanceRef symbol_scan_cntr_2))
(portRef CK (instanceRef symbol_scan_cntr_1))
(portRef CK (instanceRef symbol_scan_cntr_0))
(portRef SCLK (instanceRef bttn_state_fifo_0io_0))
))
(net clk (joined
(portRef clk)
(portRef I (instanceRef clk_pad))
))
(net rst_c (joined
(portRef O (instanceRef rst_pad))
(portRef rst_c (instanceRef DDwD_Top))
(net n_rst_c (joined
(portRef O (instanceRef n_rst_pad))
(portRef C (instanceRef bttn_state_RNIO8V61))
(portRef B (instanceRef bttn_stateand_2_0))
(portRef A (instanceRef n_rst_pad_RNIQVTF))
))
(net rst (joined
(portRef rst)
(portRef I (instanceRef rst_pad))
(net n_rst (joined
(portRef n_rst)
(portRef I (instanceRef n_rst_pad))
))
(net button_c (joined
(portRef O (instanceRef button_pad))
(portRef D (instanceRef bttn_state_fifo_0io_0))
))
(net button (joined
(portRef button)
(portRef I (instanceRef button_pad))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_0))
))
(net (rename disp_data_0 "disp_data[0]") (joined
(portRef O (instanceRef disp_data_pad_0))
(portRef (member disp_data 13))
(portRef (member disp_data 14))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_1))
))
(net (rename disp_data_1 "disp_data[1]") (joined
(portRef O (instanceRef disp_data_pad_1))
(portRef (member disp_data 12))
(portRef (member disp_data 13))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_2))
))
(net (rename disp_data_2 "disp_data[2]") (joined
(portRef O (instanceRef disp_data_pad_2))
(portRef (member disp_data 11))
(portRef (member disp_data 12))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_3))
))
(net (rename disp_data_3 "disp_data[3]") (joined
(portRef O (instanceRef disp_data_pad_3))
(portRef (member disp_data 10))
(portRef (member disp_data 11))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_4))
))
(net (rename disp_data_4 "disp_data[4]") (joined
(portRef O (instanceRef disp_data_pad_4))
(portRef (member disp_data 9))
(portRef (member disp_data 10))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_5))
))
(net (rename disp_data_5 "disp_data[5]") (joined
(portRef O (instanceRef disp_data_pad_5))
(portRef (member disp_data 8))
(portRef (member disp_data 9))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_6))
))
(net (rename disp_data_6 "disp_data[6]") (joined
(portRef O (instanceRef disp_data_pad_6))
(portRef (member disp_data 7))
(portRef (member disp_data 8))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_7))
))
(net (rename disp_data_7 "disp_data[7]") (joined
(portRef O (instanceRef disp_data_pad_7))
(portRef (member disp_data 6))
(portRef (member disp_data 7))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_8))
))
(net (rename disp_data_8 "disp_data[8]") (joined
(portRef O (instanceRef disp_data_pad_8))
(portRef (member disp_data 5))
(portRef (member disp_data 6))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_9))
))
(net (rename disp_data_9 "disp_data[9]") (joined
(portRef O (instanceRef disp_data_pad_9))
(portRef (member disp_data 4))
(portRef (member disp_data 5))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_10))
))
(net (rename disp_data_10 "disp_data[10]") (joined
(portRef O (instanceRef disp_data_pad_10))
(portRef (member disp_data 3))
(portRef (member disp_data 4))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_11))
))
(net (rename disp_data_11 "disp_data[11]") (joined
(portRef O (instanceRef disp_data_pad_11))
(portRef (member disp_data 2))
(portRef (member disp_data 3))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_12))
))
(net (rename disp_data_12 "disp_data[12]") (joined
(portRef O (instanceRef disp_data_pad_12))
(portRef (member disp_data 1))
(portRef (member disp_data 2))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_13))
))
(net (rename disp_data_13 "disp_data[13]") (joined
(portRef O (instanceRef disp_data_pad_13))
(portRef (member disp_data 1))
))
(net (rename disp_data_14 "disp_data[14]") (joined
(portRef O (instanceRef disp_data_pad_14))
(portRef (member disp_data 0))
))
(net disp_sel (joined
290,6 → 1025,28
(portRef O (instanceRef disp_sel_pad))
(portRef disp_sel)
))
(net n_rst_c_i (joined
(portRef Z (instanceRef n_rst_pad_RNIQVTF))
(portRef PD (instanceRef bttn_state_fifo_3))
(portRef PD (instanceRef bttn_state_fifo_2))
(portRef PD (instanceRef bttn_state_fifo_1))
(portRef CD (instanceRef symbol_scan_cntr_7))
(portRef CD (instanceRef symbol_scan_cntr_6))
(portRef CD (instanceRef symbol_scan_cntr_5))
(portRef CD (instanceRef symbol_scan_cntr_4))
(portRef CD (instanceRef symbol_scan_cntr_3))
(portRef CD (instanceRef symbol_scan_cntr_2))
(portRef CD (instanceRef symbol_scan_cntr_1))
(portRef CD (instanceRef symbol_scan_cntr_0))
(portRef PD (instanceRef bttn_state_fifo_0io_0))
))
(net (rename symbol_scan_cntr_i_7 "symbol_scan_cntr_i[7]") (joined
(portRef Z (instanceRef disp_data_pad_RNO_14))
(portRef I (instanceRef disp_data_pad_14))
))
(net N_1 (joined
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_0))
))
)
(property orig_inst_of (string "DisplayDriverWrapper"))
)
296,5 → 1053,5
)
)
(design DisplayDriverWrapper (cellRef DisplayDriverWrapper (libraryRef work))
(property PART (string "lfe5u_45f-6") ))
(property PART (string "lfe5um5g_45f-8") ))
)
/Lattice_FPGA_Build/impl1/impl1.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/impl1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/impl1.srr
3,7 → 3,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
#Implementation: impl1
 
17,23 → 17,29
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
Options changed - recompiling
VHDL syntax check successful!
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
@W: CL240 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":38:8:38:16|disp_data is not assigned a value (floating) -- simulation mismatch possible.
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
47,7 → 53,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
###########################################################]
@END
57,7 → 63,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:32 2017
# Tue Jan 17 01:29:36 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
71,7 → 77,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Sun Jan 08 00:49:34 2017
# Tue Jan 17 01:29:37 2017
 
###########################################################]
Pre-mapping Report
94,10 → 100,10
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
 
ICG Latch Removal Summary:
Number of ICG latches removed: 0
104,7 → 110,7
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
 
 
111,29 → 117,30
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
---------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=========================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
None
None
 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
Pre-mapping successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 08 00:49:34 2017
# Tue Jan 17 01:29:38 2017
 
###########################################################]
Map & Optimize Report
170,6 → 177,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
186,7 → 194,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
199,13 → 207,21
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.62ns 7 / 13
 
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
213,15 → 229,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
=============================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
231,7 → 247,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
238,21 → 254,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Sun Jan 08 00:49:36 2017
# Timing Report written on Tue Jan 17 01:29:40 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 1297.0 MHz
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
266,13 → 282,13
*******************
 
 
Worst slack in design: -0.136
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
==================================================================================================================================
 
 
 
285,7 → 301,7
-------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.771 -0.136 | No paths - | No paths - | No paths -
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
308,37 → 324,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.853 -0.136
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.853 -0.136
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.853 -0.136
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.853 -0.136
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.853 -0.136
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.853 -0.136
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.853 -0.136
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.853 -0.136
==============================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
===================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.717 -0.136
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.717 -0.136
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.717 -0.136
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.717 -0.136
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.717 -0.136
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.717 -0.136
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.717 -0.136
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.717 -0.136
===============================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
================================================================================================================================
 
 
 
347,128 → 367,191
 
 
Path information for path number 1:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (critical) : -0.407
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[0] / Q
Ending point: DDwD_Top.ascii_reg[0] / D
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.853 0.853 -
ascii_reg[0] Net - - - - 1
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[1] / Q
Ending point: DDwD_Top.ascii_reg[1] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.853 0.853 -
ascii_reg[1] Net - - - - 1
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[2] / Q
Ending point: DDwD_Top.ascii_reg[2] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.853 0.853 -
ascii_reg[2] Net - - - - 1
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[3] / Q
Ending point: DDwD_Top.ascii_reg[3] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.853 0.853 -
ascii_reg[3] Net - - - - 1
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 0.771
- Setup time: 0.054
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.717
= Required time: 2.094
 
- Propagation time: 0.853
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.136
= Slack (non-critical) : -0.348
 
Number of logic level(s): 0
Starting point: DDwD_Top.ascii_reg[4] / Q
Ending point: DDwD_Top.ascii_reg[4] / D
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.853 0.853 -
ascii_reg[4] Net - - - - 1
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.853 -
=======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
 
477,35 → 560,40
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5u_45f-6
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 17
I/O cells: 19
 
 
Details:
FD1S3IX: 5
CCU2C: 5
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
OB: 15
IB: 3
IFS1P3JX: 1
INV: 2
OB: 16
ORCALUT4: 4
PUR: 1
VHI: 2
ROM128X1A: 14
VHI: 1
VLO: 1
false: 1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 08 00:49:36 2017
# Tue Jan 17 01:29:40 2017
 
###########################################################]
/Lattice_FPGA_Build/impl1/impl1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Lattice_FPGA_Build/impl1/impl1.xcf
7,12 → 7,10
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Vendor>Micron</Vendor>
<Family>ECP5UM5G</Family>
<Name>LFE5UM5G-45F</Name>
<IDCode>0x81112043</IDCode>
<Package>All</Package>
<PON>LFE5UM5G-45F</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
20,17 → 18,73
<BScanVal>0</BScanVal>
</Bypass>
<File>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bit</File>
<FileTime>01/13/17 00:55:08</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<FileTime>01/17/17 01:37:17</FileTime>
<Operation>SPI Flash Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>510</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<Usercode>0x00000000</Usercode>
<AccessMode>JTAG</AccessMode>
<AccessMode>SPI Flash Background Programming</AccessMode>
</Option>
<FPGALoader>
<CPLDDevice>
<Device>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>ECP5UM5G</Family>
<Name>LFE5UM5G-45F</Name>
<IDCode>0x81112043</IDCode>
<Package>All</Package>
<PON>LFE5UM5G-45F</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<MaskFile>C:/lscc/diamond/3.8_x64/data/vmdata/database\xpga\ecp5\LFE5UM-45F.msk</MaskFile>
<Operation>Bypass</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>510</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
</CPLDDevice>
<FlashDevice>
<Device>
<Pos>1</Pos>
<Vendor>Micron</Vendor>
<Family>SPI Serial Flash</Family>
<Name>SPI-N25Q128A</Name>
<IDCode>0x18</IDCode>
<Package>16-pin SO16</Package>
<Operation>SPI Flash Erase,Program,Verify</Operation>
<File>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bit</File>
<AddressBase>0x00000000</AddressBase>
<EndAddress>0x000F0000</EndAddress>
<DeviceSize>128</DeviceSize>
<DataSize>1032647</DataSize>
<NumberOfDevices>1</NumberOfDevices>
<ReInitialize value="FALSE"/>
</Device>
</FlashDevice>
<FPGADevice>
<Device>
<Pos>1</Pos>
<Name></Name>
<File>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bit</File>
<LocalChainList>
<LocalDevice index="-99"
name="Unknown"
file="C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bit"/>
</LocalChainList>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
</Option>
</Device>
</FPGADevice>
</FPGALoader>
</Device>
</Chain>
<ProjectOptions>
/Lattice_FPGA_Build/impl1/impl1_cck.rpt
1,7 → 1,7
# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Sun Jan 08 00:49:34 2017
# Written on Tue Jan 17 01:29:38 2017
 
 
##### DESIGN INFO #######################################################
24,9 → 24,11
Clock Relationships
*******************
 
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------
===================================================================================================================================
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 1000.000 | No paths | No paths | No paths
DisplayDriverWrapper|bttn_state_derived_clock DisplayDriverWrapper|bttn_state_derived_clock | 1000.000 | No paths | No paths | No paths
===============================================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
49,8 → 51,9
p:disp_data[11]
p:disp_data[12]
p:disp_data[13]
p:disp_data[14]
p:disp_sel
p:rst
p:n_rst
 
 
Inapplicable constraints
/Lattice_FPGA_Build/impl1/impl1_scck.rpt
1,7 → 1,7
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Sun Jan 08 00:49:34 2017
# Written on Tue Jan 17 01:29:38 2017
 
 
##### DESIGN INFO #######################################################
21,8 → 21,9
Clock Summary
*************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
=====================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
---------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=========================================================================================================================================================
/Lattice_FPGA_Build/impl1/impl1_syn.prd
0,0 → 1,11
#-- Synopsys, Inc.
#-- Version L-2016.03L-1
#-- Project file C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_syn.prd
#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear
/Lattice_FPGA_Build/impl1/impl1_syn.prj
1,13 → 1,15
#-- Synopsys, Inc.
#-- Version L-2016.03L-1
#-- Project file C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_syn.prj
#-- Written on Sun Jan 08 00:48:40 2017
#-- Written on Tue Jan 17 01:28:16 2017
 
 
#project files
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5u.vhd"
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
 
 
 
21,10 → 23,10
set_option -project_relative_includes 1
 
#device options
set_option -technology ECP5U
set_option -part LFE5U_45F
set_option -technology ECP5UM5G
set_option -part LFE5UM5G_45F
set_option -package BG381C
set_option -speed_grade -6
set_option -speed_grade -8
set_option -part_companion ""
 
#compilation/mapping options
/Lattice_FPGA_Build/impl1/impl1_synplify.lpf
3,7 → 3,7
#
 
# Period Constraints
#FREQUENCY PORT "clk" 1297.0 MHz;
#FREQUENCY PORT "clk" 433.9 MHz;
 
 
# Output Constraints
/Lattice_FPGA_Build/impl1/launch_synplify.tcl
1,6 → 1,6
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
#-- Written on Sun Jan 8 00:48:39 2017
#-- Written on Tue Jan 17 01:28:15 2017
 
project -close
set filename "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj"
13,10 → 13,10
set create_new 0
 
#device options
set_option -technology ECP5U
set_option -part LFE5U_45F
set_option -technology ECP5UM5G
set_option -part LFE5UM5G_45F
set_option -package BG381C
set_option -speed_grade -6
set_option -speed_grade -8
 
if {$create_new == 1} {
#-- add synthesis options
44,9 → 44,11
}
#-- add_file options
add_file -vhdl "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5u.vhd"
add_file -vhdl "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
#-- top module name
set_option -top_module {}
project -result_file {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.edi}
/Lattice_FPGA_Build/impl1/message.xml
1,18 → 1,30
<?xml version="1.0" encoding="UTF-8"?>
<BaliMessageLog>
<Task name="Bitgen">
<Task name="Map">
<Message>
<ID>71001181</ID>
<ID>1101672</ID>
<Severity>Warning</Severity>
<Dynamic>0</Dynamic>
<Dynamic>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in &quot;USERCODE ASCII &quot;G.L.&quot; ; &quot;: </Dynamic>
<Dynamic>Invalid Ascii char &lt;.&gt;.Invalid Ascii char &lt;.&gt;.</Dynamic>
<Navigation>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf</Navigation>
<Navigation>21</Navigation>
</Message>
</Task>
<Task name="Map">
<Message>
<ID>51001046</ID>
<ID>1104062</ID>
<Severity>Warning</Severity>
<Dynamic>button</Dynamic>
<Dynamic></Dynamic>
<Dynamic>1 semantic error</Dynamic>
</Message>
<Message>
<ID>51001030</ID>
<Severity>Warning</Severity>
<Dynamic>n_rst_c</Dynamic>
</Message>
<Message>
<ID>51001230</ID>
<Severity>Warning</Severity>
<Dynamic>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf</Dynamic>
</Message>
</Task>
<Task name="Lattice_Synthesis">
<Message>
117,8 → 129,8
</Task>
<Task name="PAR">
<Message>
<ID>60001135</ID>
<Severity>Info</Severity>
<ID>2030012</ID>
<Severity>Warning</Severity>
</Message>
</Task>
<Task name="Translate">
126,13 → 138,27
<ID>1166052</ID>
<Severity>Warning</Severity>
<Dynamic>logical</Dynamic>
<Dynamic>button</Dynamic>
<Navigation>button</Navigation>
<Dynamic>symbol_scan_cntr_cry_0_S0[0]</Dynamic>
<Navigation>symbol_scan_cntr_cry_0_S0[0]</Navigation>
</Message>
<Message>
<ID>1166052</ID>
<Severity>Warning</Severity>
<Dynamic>logical</Dynamic>
<Dynamic>symbol_scan_cntr_s_0_S1[7]</Dynamic>
<Navigation>symbol_scan_cntr_s_0_S1[7]</Navigation>
</Message>
<Message>
<ID>1166052</ID>
<Severity>Warning</Severity>
<Dynamic>logical</Dynamic>
<Dynamic>symbol_scan_cntr_s_0_COUT[7]</Dynamic>
<Navigation>symbol_scan_cntr_s_0_COUT[7]</Navigation>
</Message>
<Message>
<ID>1163101</ID>
<Severity>Warning</Severity>
<Dynamic>1</Dynamic>
<Dynamic>3</Dynamic>
</Message>
</Task>
<Task name="Synplify_Synthesis">
155,21 → 181,57
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>MT529 :&quot;c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd&quot;:76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
<Dynamic>CD638 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd&quot;:53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</Dynamic>
<Navigation>CD638</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd</Navigation>
<Navigation>53</Navigation>
<Navigation>11</Navigation>
<Navigation>53</Navigation>
<Navigation>19</Navigation>
<Navigation>Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>CL169 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd&quot;:54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.</Dynamic>
<Navigation>CL169</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd</Navigation>
<Navigation>54</Navigation>
<Navigation>4</Navigation>
<Navigation>54</Navigation>
<Navigation>5</Navigation>
<Navigation>Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>CL169 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd&quot;:54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.</Dynamic>
<Navigation>CL169</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd</Navigation>
<Navigation>54</Navigation>
<Navigation>4</Navigation>
<Navigation>54</Navigation>
<Navigation>5</Navigation>
<Navigation>Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>MT529 :&quot;c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd&quot;:74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
<Navigation>MT529</Navigation>
<Navigation>c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd</Navigation>
<Navigation>76</Navigation>
<Navigation>8</Navigation>
<Navigation>76</Navigation>
<Navigation>9</Navigation>
<Navigation>Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
<Navigation>c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd</Navigation>
<Navigation>74</Navigation>
<Navigation>4</Navigation>
<Navigation>74</Navigation>
<Navigation>5</Navigation>
<Navigation>Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
</Message>
<Message>
<ID>2019993</ID>
<Severity>Warning</Severity>
<Dynamic>MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object &quot;p:clk&quot;</Dynamic>
<Dynamic>MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object &quot;p:button&quot;</Dynamic>
<Navigation>MT420</Navigation>
<Navigation>Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object &quot;p:clk&quot;</Navigation>
<Navigation>Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object &quot;p:button&quot;</Navigation>
</Message>
</Task>
</BaliMessageLog>
/Lattice_FPGA_Build/impl1/run_options.txt
6,6 → 6,8
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
 
 
 
15,7 → 17,7
#
#implementation attributes
 
set_option -vlog_std v2001
set_option -vlog_std sysv
set_option -project_relative_includes 1
 
#device options
26,7 → 28,6
set_option -part_companion ""
 
#compilation/mapping options
set_option -top_module "DisplayDriverWrapper"
 
# hdl_compiler_options
set_option -distributed_compile 0
40,11 → 41,11
set_option -write_vhdl 0
 
# Lattice XP
set_option -maxfan 1000
set_option -maxfan 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr false
set_option -forcegsr no
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
69,8 → 70,5
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "./DisplayDriverwDecoder_impl1.edi"
 
#set log file
set_option log_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srf"
project -result_file "./impl1.edi"
impl -active "impl1"
/Lattice_FPGA_Build/impl1/scratchproject.prs
6,6 → 6,8
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
 
 
 
15,7 → 17,7
#
#implementation attributes
 
set_option -vlog_std v2001
set_option -vlog_std sysv
set_option -project_relative_includes 1
set_option -include_path {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/}
 
27,7 → 29,6
set_option -part_companion ""
 
#compilation/mapping options
set_option -top_module "DisplayDriverWrapper"
 
# hdl_compiler_options
set_option -distributed_compile 0
41,11 → 42,11
set_option -write_vhdl 0
 
# Lattice XP
set_option -maxfan 1000
set_option -maxfan 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr false
set_option -forcegsr no
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
70,8 → 71,5
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.edi"
 
#set log file
set_option log_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srf"
project -result_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.edi"
impl -active "impl1"
/Lattice_FPGA_Build/impl1/synlog.tcl
1,8 → 7,5
run_tcl -fg DisplayDriverwDecoder_impl1_synplify.tcl
source "C:/Users/GL/AppData/Local/Synplicity/scm_perforce.tcl"
history clear
run_tcl -fg C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
project -run
project -run
project -run
project -close C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj
/Lattice_FPGA_Build/.spreadsheet_view.ini
8,15 → 8,15
[Port%20Assignments]
Name="223,0"
Group%20By="94,1"
Pin="97,2"
Pin="60,2"
BANK="72,3"
BANK_VCC="100,4"
VREF="70,5"
IO_TYPE="223,6"
PULLMODE="137,7"
IO_TYPE="112,6"
PULLMODE="102,7"
DRIVE="77,8"
SLEWRATE="139,9"
CLAMP="83,10"
SLEWRATE="102,9"
CLAMP="81,10"
OPENDRAIN="107,11"
DIFFRESISTOR="124,12"
DIFFDRIVE="102,13"
38,13 → 38,13
Polarity="87,3"
BANK="0,4"
BANK_VCC="100,5"
IO_TYPE="223,6"
Signal%20Name="241,7"
Signal%20Type="157,8"
IO_TYPE="112,6"
Signal%20Name="121,7"
Signal%20Type="108,8"
sort_columns="Pin,Ascending"
 
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Type="116,ELLIPSIS"
Clock%20Name="100,ELLIPSIS"
Selection="100,ELLIPSIS"
Quadrant="100,ELLIPSIS"
51,7 → 51,7
 
[Global%20Preferences]
Preference%20Name="303,ELLIPSIS"
Preference%20Value="332,ELLIPSIS"
Preference%20Value="157,ELLIPSIS"
 
[Cell%20Mapping]
Type="100,ELLIPSIS"
/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf
9,6 → 9,12
<Source name="../Sources/DisplayDriverWrapper.vhd" type="VHDL" type_short="VHDL">
<Options top_module="DisplayDriverWrapper"/>
</Source>
<Source name="../Sources/ASCIIDecoder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="DisplayDriverwDecoder.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf
9,7 → 9,6
LOCATE COMP "disp_data[5]" SITE "M18" ;
LOCATE COMP "disp_data[7]" SITE "P17" ;
LOCATE COMP "disp_data[8]" SITE "N16" ;
LOCATE COMP "rst" SITE "T1" ;
LOCATE COMP "clk" SITE "P3" ;
IOBUF PORT "clk" IO_TYPE=LVDS ;
LOCATE COMP "disp_sel" SITE "J1" ;
19,3 → 18,8
LOCATE COMP "disp_data[14]" SITE "U1" ;
LOCATE COMP "disp_data[9]" SITE "M17" ;
LOCATE COMP "disp_data[13]" SITE "R16" ;
USERCODE ASCII "G.L." ;
IOBUF PORT "button" PULLMODE=UP IO_TYPE=LVCMOS25 ;
LOCATE COMP "n_rst" SITE "K20" ;
IOBUF PORT "n_rst" PULLMODE=UP IO_TYPE=LVCMOS25 ;
LOCATE COMP "button" SITE "T1" ;
/Lattice_FPGA_Build/DisplayDriverwDecoder_tcl.html
119,6 → 119,43
 
 
 
<A name="pn170113005643"></A><B><U><big>pn170113005643</big></U></B>
#Start recording tcl command: 1/12/2017 23:36:58
#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder
prj_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf"
prj_dev set -part LFE5UM5G-45F-8BG381C
prj_run Translate -impl impl1
prj_run Export -impl impl1 -task Bitgen
prj_run Export -impl impl1 -task Bitgen
pgr_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.xcf"
pgr_project close
pgr_program run
pgr_program run
pgr_program set -port FTUSB-1
pgr_program run
pgr_program set -port FTUSB-0
pgr_program run
pgr_program run
pgr_program run
prj_run Export -impl impl1 -task Bitgen
prj_run Translate -impl impl1
pgr_project save "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.xcf"
prj_run Export -impl impl1 -task Bitgen
pgr_program run
prj_run Translate -impl impl1
pgr_project save "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.xcf"
prj_run Export -impl impl1 -task Bitgen
pgr_program run
prj_run Export -impl impl1 -task Bitgen
pgr_program run
prj_run Export -impl impl1 -task Bitgen
prj_project save
pgr_project save "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.xcf"
pgr_project close
#Stop recording: 1/13/2017 00:56:43
 
 
 
<BR>
<BR>
<BR>
/Lattice_FPGA_Build/promote.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml" version="Diamond (64-bit) 3.8.0.115.3" date="Fri Jan 13 00:56:43 2017" vendor="Lattice Semiconductor Corporation" >
<userSetting name="C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml" version="Diamond (64-bit) 3.8.0.115.3" date="Tue Jan 17 01:51:32 2017" vendor="Lattice Semiconductor Corporation" >
<msg mid="35921504" type="Info" />
<msg mid="35921205" type="Warning" />
</userSetting>
/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/._Real_._Math_.vhd
0,0 → 1,2574
 
 
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
 
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
 
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
 
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
 
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
 
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
 
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
 
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
 
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
 
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
 
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
 
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
 
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
 
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
 
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
 
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
 
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
 
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
 
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
 
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
 
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
 
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
 
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
 
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
 
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
 
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
 
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
 
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
 
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
 
 
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
 
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
 
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
 
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
 
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
 
end MATH_REAL;
 
 
 
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
 
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
 
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
 
package body MATH_REAL is
 
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
 
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
 
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
 
 
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
 
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
 
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
 
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
 
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
 
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
 
begin
if ABS(X) >= LARGE then
return X;
end if;
 
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
 
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
 
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
 
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
 
begin
if ABS( X ) >= LARGE then
return X;
end if;
 
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
 
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
 
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
 
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
 
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
 
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
 
 
 
 
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
 
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
 
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
 
return VALUE;
end "MOD";
 
 
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
 
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
 
 
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
 
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
 
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
 
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
 
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
 
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
 
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
 
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
 
 
 
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
 
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
 
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
 
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
 
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
 
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
 
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
 
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
 
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
 
begin
 
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
 
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
 
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
 
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
 
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
 
return NEWVAL;
end CBRT;
 
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
 
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
 
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
 
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
 
if ( X = 1 ) then
return 1.0;
end if;
 
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
 
if ( Y = 1.0) then
return (REAL(X));
end if;
 
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
 
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
 
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
 
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
 
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
 
if ( X = 1.0 ) then
return 1.0;
end if;
 
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
 
if ( Y = 1.0) then
return (X);
end if;
 
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
 
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
 
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
 
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
 
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
 
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
 
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
 
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
 
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
 
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
 
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
 
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
 
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
 
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
 
return NEWVAL;
end EXP;
 
 
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
 
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
 
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
 
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
 
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
 
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
 
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
 
constant N: INTEGER := 128;
 
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
 
type REAL_VECTOR is array (NATURAL range <>) of REAL;
 
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
 
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
 
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
 
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
 
-- double logb(), ldexp();
 
variable U1:REAL;
 
begin
 
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
 
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
 
if ( X = MATH_E ) then
return 1.0;
end if;
 
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
 
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
 
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
 
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
 
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
 
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
 
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
 
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
 
 
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
 
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
 
if ( X = 2.0 ) then
return 1.0;
end if;
 
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
 
 
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
 
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
 
if ( X = 10.0 ) then
return 1.0;
end if;
 
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
 
 
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
 
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
 
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
 
if ( X = BASE ) then
return 1.0;
end if;
 
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
 
 
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
 
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
 
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
 
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
 
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
 
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
 
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
 
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
 
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
 
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
 
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
 
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
 
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
 
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
 
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
 
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
 
 
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
 
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
 
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
 
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
 
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
 
if XLOCAL = MATH_PI then
return -1.0;
end if;
 
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
 
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
 
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
 
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
 
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
 
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
 
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
 
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
 
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
 
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
 
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
 
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
 
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
 
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
 
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
 
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
 
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
 
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
 
if NEGATIVE then
VALUE := -VALUE;
end if;
 
return VALUE;
end ARCSIN;
 
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
 
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
 
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
 
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
 
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
 
 
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
 
return VALUE;
end ARCCOS;
 
 
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
 
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
 
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
 
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
 
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
 
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
 
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
 
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
 
if NEGATIVE then
VALUE := -VALUE;
end if;
 
return VALUE;
end ARCTAN;
 
 
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
 
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
 
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
 
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
 
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
 
 
-- Compute value for general cases
YLOCAL := ABS(Y/X);
 
VALUE := ARCTAN(YLOCAL);
 
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
 
if Y < 0.0 then
VALUE := -VALUE;
end if;
 
return VALUE;
end ARCTAN;
 
 
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
 
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
 
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
 
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
 
if NEGATIVE then
VALUE := -VALUE;
end if;
 
return VALUE;
end SINH;
 
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
 
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
 
 
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
 
return VALUE;
end COSH;
 
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
 
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
 
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
 
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
 
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
 
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
 
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
 
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
 
 
 
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
 
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
 
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
 
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
 
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
 
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
 
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
 
end MATH_REAL;
Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/._Real_._Math_.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.edn =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.edn (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.edn (revision 6) @@ -0,0 +1,294 @@ +(edif DistRomAsciiDecoder + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2017 1 13 23 14 11) + (program "SCUBA" (version "Diamond (64-bit) 3.8.0.115.3")))) + (comment "C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell ROM128X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD6 + (direction INPUT)) + (port AD5 + (direction INPUT)) + (port AD4 + (direction INPUT)) + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell DistRomAsciiDecoder + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Address "Address(6:0)") 7) + (direction INPUT)) + (port (array (rename Q "Q(13:0)") 14) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance mem_0_13 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xDA3FFFFFBA3FFFFFB7FE6997BFFFFFFE"))) + (instance mem_0_12 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xEDEFFDEBFDEFFDEB7BFFB3E718FFD7FF"))) + (instance mem_0_11 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xF679B7FFEE79B7FFEFDFFA97BFFFFFDF"))) + (instance mem_0_10 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xF0BFD7FFB8BFD7FFEFFE7A176DFFFFFE"))) + (instance mem_0_9 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xEFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF"))) + (instance mem_0_8 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xDCFF9FFEECFF9FFFBFFFF9976DFFFFFF"))) + (instance mem_0_7 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x9FF2FE59FFF2FE585CA3D3C7D0FFB0A3"))) + (instance mem_0_6 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xB7F2F69DFFF2F69DDC8B93C7D0FF388B"))) + (instance mem_0_5 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7F100615F7100614FC8EFFC3E3FF288E"))) + (instance mem_0_4 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x3F180215F7180214FEBABFF7EBFF2ABA"))) + (instance mem_0_3 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7BD56B4353D56B42DC92BFA7DAFF8492"))) + (instance mem_0_2 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7F551A69DF551A69FC24FF85FFFFD024"))) + (instance mem_0_1 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x3F581AE99F581AE87C60FFF5F7FFD060"))) + (instance mem_0_0 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7BE07F0193E07F007C12FFA7F2FF0012"))) + (net qdataout13 + (joined + (portRef (member Q 0)) + (portRef DO0 (instanceRef mem_0_13)))) + (net qdataout12 + (joined + (portRef (member Q 1)) + (portRef DO0 (instanceRef mem_0_12)))) + (net qdataout11 + (joined + (portRef (member Q 2)) + (portRef DO0 (instanceRef mem_0_11)))) + (net qdataout10 + (joined + (portRef (member Q 3)) + (portRef DO0 (instanceRef mem_0_10)))) + (net qdataout9 + (joined + (portRef (member Q 4)) + (portRef DO0 (instanceRef mem_0_9)))) + (net qdataout8 + (joined + (portRef (member Q 5)) + (portRef DO0 (instanceRef mem_0_8)))) + (net qdataout7 + (joined + (portRef (member Q 6)) + (portRef DO0 (instanceRef mem_0_7)))) + (net qdataout6 + (joined + (portRef (member Q 7)) + (portRef DO0 (instanceRef mem_0_6)))) + (net qdataout5 + (joined + (portRef (member Q 8)) + (portRef DO0 (instanceRef mem_0_5)))) + (net qdataout4 + (joined + (portRef (member Q 9)) + (portRef DO0 (instanceRef mem_0_4)))) + (net qdataout3 + (joined + (portRef (member Q 10)) + (portRef DO0 (instanceRef mem_0_3)))) + (net qdataout2 + (joined + (portRef (member Q 11)) + (portRef DO0 (instanceRef mem_0_2)))) + (net qdataout1 + (joined + (portRef (member Q 12)) + (portRef DO0 (instanceRef mem_0_1)))) + (net qdataout0 + (joined + (portRef (member Q 13)) + (portRef DO0 (instanceRef mem_0_0)))) + (net addr6 + (joined + (portRef (member Address 0)) + (portRef AD6 (instanceRef mem_0_13)) + (portRef AD6 (instanceRef mem_0_12)) + (portRef AD6 (instanceRef mem_0_11)) + (portRef AD6 (instanceRef mem_0_10)) + (portRef AD6 (instanceRef mem_0_9)) + (portRef AD6 (instanceRef mem_0_8)) + (portRef AD6 (instanceRef mem_0_7)) + (portRef AD6 (instanceRef mem_0_6)) + (portRef AD6 (instanceRef mem_0_5)) + (portRef AD6 (instanceRef mem_0_4)) + (portRef AD6 (instanceRef mem_0_3)) + (portRef AD6 (instanceRef mem_0_2)) + (portRef AD6 (instanceRef mem_0_1)) + (portRef AD6 (instanceRef mem_0_0)))) + (net addr5 + (joined + (portRef (member Address 1)) + (portRef AD5 (instanceRef mem_0_13)) + (portRef AD5 (instanceRef mem_0_12)) + (portRef AD5 (instanceRef mem_0_11)) + (portRef AD5 (instanceRef mem_0_10)) + (portRef AD5 (instanceRef mem_0_9)) + (portRef AD5 (instanceRef mem_0_8)) + (portRef AD5 (instanceRef mem_0_7)) + (portRef AD5 (instanceRef mem_0_6)) + (portRef AD5 (instanceRef mem_0_5)) + (portRef AD5 (instanceRef mem_0_4)) + (portRef AD5 (instanceRef mem_0_3)) + (portRef AD5 (instanceRef mem_0_2)) + (portRef AD5 (instanceRef mem_0_1)) + (portRef AD5 (instanceRef mem_0_0)))) + (net addr4 + (joined + (portRef (member Address 2)) + (portRef AD4 (instanceRef mem_0_13)) + (portRef AD4 (instanceRef mem_0_12)) + (portRef AD4 (instanceRef mem_0_11)) + (portRef AD4 (instanceRef mem_0_10)) + (portRef AD4 (instanceRef mem_0_9)) + (portRef AD4 (instanceRef mem_0_8)) + (portRef AD4 (instanceRef mem_0_7)) + (portRef AD4 (instanceRef mem_0_6)) + (portRef AD4 (instanceRef mem_0_5)) + (portRef AD4 (instanceRef mem_0_4)) + (portRef AD4 (instanceRef mem_0_3)) + (portRef AD4 (instanceRef mem_0_2)) + (portRef AD4 (instanceRef mem_0_1)) + (portRef AD4 (instanceRef mem_0_0)))) + (net addr3 + (joined + (portRef (member Address 3)) + (portRef AD3 (instanceRef mem_0_13)) + (portRef AD3 (instanceRef mem_0_12)) + (portRef AD3 (instanceRef mem_0_11)) + (portRef AD3 (instanceRef mem_0_10)) + (portRef AD3 (instanceRef mem_0_9)) + (portRef AD3 (instanceRef mem_0_8)) + (portRef AD3 (instanceRef mem_0_7)) + (portRef AD3 (instanceRef mem_0_6)) + (portRef AD3 (instanceRef mem_0_5)) + (portRef AD3 (instanceRef mem_0_4)) + (portRef AD3 (instanceRef mem_0_3)) + (portRef AD3 (instanceRef mem_0_2)) + (portRef AD3 (instanceRef mem_0_1)) + (portRef AD3 (instanceRef mem_0_0)))) + (net addr2 + (joined + (portRef (member Address 4)) + (portRef AD2 (instanceRef mem_0_13)) + (portRef AD2 (instanceRef mem_0_12)) + (portRef AD2 (instanceRef mem_0_11)) + (portRef AD2 (instanceRef mem_0_10)) + (portRef AD2 (instanceRef mem_0_9)) + (portRef AD2 (instanceRef mem_0_8)) + (portRef AD2 (instanceRef mem_0_7)) + (portRef AD2 (instanceRef mem_0_6)) + (portRef AD2 (instanceRef mem_0_5)) + (portRef AD2 (instanceRef mem_0_4)) + (portRef AD2 (instanceRef mem_0_3)) + (portRef AD2 (instanceRef mem_0_2)) + (portRef AD2 (instanceRef mem_0_1)) + (portRef AD2 (instanceRef mem_0_0)))) + (net addr1 + (joined + (portRef (member Address 5)) + (portRef AD1 (instanceRef mem_0_13)) + (portRef AD1 (instanceRef mem_0_12)) + (portRef AD1 (instanceRef mem_0_11)) + (portRef AD1 (instanceRef mem_0_10)) + (portRef AD1 (instanceRef mem_0_9)) + (portRef AD1 (instanceRef mem_0_8)) + (portRef AD1 (instanceRef mem_0_7)) + (portRef AD1 (instanceRef mem_0_6)) + (portRef AD1 (instanceRef mem_0_5)) + (portRef AD1 (instanceRef mem_0_4)) + (portRef AD1 (instanceRef mem_0_3)) + (portRef AD1 (instanceRef mem_0_2)) + (portRef AD1 (instanceRef mem_0_1)) + (portRef AD1 (instanceRef mem_0_0)))) + (net addr0 + (joined + (portRef (member Address 6)) + (portRef AD0 (instanceRef mem_0_13)) + (portRef AD0 (instanceRef mem_0_12)) + (portRef AD0 (instanceRef mem_0_11)) + (portRef AD0 (instanceRef mem_0_10)) + (portRef AD0 (instanceRef mem_0_9)) + (portRef AD0 (instanceRef mem_0_8)) + (portRef AD0 (instanceRef mem_0_7)) + (portRef AD0 (instanceRef mem_0_6)) + (portRef AD0 (instanceRef mem_0_5)) + (portRef AD0 (instanceRef mem_0_4)) + (portRef AD0 (instanceRef mem_0_3)) + (portRef AD0 (instanceRef mem_0_2)) + (portRef AD0 (instanceRef mem_0_1)) + (portRef AD0 (instanceRef mem_0_0)))))))) + (design DistRomAsciiDecoder + (cellRef DistRomAsciiDecoder + (libraryRef ORCLIB))) +) Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc (revision 6) @@ -0,0 +1,2 @@ +###==== Start Configuration + Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.jhd =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.jhd (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.jhd (revision 6) @@ -0,0 +1,2 @@ +VHDL_ENTITY_ONLY DistRomAsciiDecoder DEFIN DistRomAsciiDecoder.vhd +MODULE DistRomAsciiDecoder DEFIN DistRomAsciiDecoder.vhd Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.lpc =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.lpc (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.lpc (revision 6) @@ -0,0 +1,40 @@ +[Device] +Family=ecp5um5g +PartType=LFE5UM5G-45F +PartName=LFE5UM5G-45F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.8 +ModuleName=DistRomAsciiDecoder +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=01/13/2017 +Time=23:14:03 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=128 +Data=14 +LUT=0 +MemFile=c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem +MemFormat=bin + +[FilesGenerated] +c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem=mem + +[Command] +cmd_line= -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.naf =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.naf (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.naf (revision 6) @@ -0,0 +1,2 @@ +Address i +Q o Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx (revision 6) @@ -0,0 +1,205 @@ + + + + Lattice Semiconductor Corporation + LEGACY + Distributed_ROM + 2.8 + + + Diamond_Simulation + simulation + + ./DistRomAsciiDecoder.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./DistRomAsciiDecoder.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + + + + + + LFE5UM5G-45F-8BG381C + synplify + 2017-01-13.23:14:11 + 2017-01-13.23:14:11 + 3.8.0.115.3 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um5g + + + OperatingCondition + COM + + + Package + CABGA381 + + + PartName + LFE5UM5G-45F-8BG381C + + + PartType + LFE5UM5G-45F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + Distributed_ROM + + + CoreRevision + 2.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 01/13/2017 + + + ModuleName + DistRomAsciiDecoder + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 23:14:03 + + + VendorName + Lattice Semiconductor Corporation + + + + Addresses + 128 + + + Data + 14 + + + Destination + Synplicity + + + EDIF + 1 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + LUT + 0 + + + MemFile + c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem + + + MemFormat + bin + + + Order + Big Endian [MSB:LSB] + + + VHDL + 1 + + + Verilog + 0 + + + + c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem + mem + + + + cmd_line + -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin + + + + + + + LATTICE + LOCAL + DistRomAsciiDecoder + 1.0 + + + + Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sort =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sort (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sort (revision 6) @@ -0,0 +1 @@ +DistRomAsciiDecoder.vhd Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.srp =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.srp (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.srp (revision 6) @@ -0,0 +1,30 @@ +SCUBA, Version Diamond (64-bit) 3.8.0.115.3 +Fri Jan 13 23:14:11 2017 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc + Circuit name : DistRomAsciiDecoder + Module type : rom + Module Version : 2.8 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[13:0] + I/O buffer : not inserted + Memory file : c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem + EDIF output : DistRomAsciiDecoder.edn + VHDL output : DistRomAsciiDecoder.vhd + VHDL template : DistRomAsciiDecoder_tmpl.vhd + VHDL testbench : tb_DistRomAsciiDecoder_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : DistRomAsciiDecoder.srp + Element Usage : + ROM128X1A : 14 + Estimated Resource Usage: + LUT : 56 Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym (revision 6)
Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd (revision 6) @@ -0,0 +1,109 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +-- Module Version: 2.8 +--C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc + +-- Fri Jan 13 23:14:11 2017 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity DistRomAsciiDecoder is + port ( + Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(13 downto 0)); +end DistRomAsciiDecoder; + +architecture Structure of DistRomAsciiDecoder is + + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + mem_0_13: ROM128X1A + generic map (initval=> X"DA3FFFFFBA3FFFFFB7FE6997BFFFFFFE") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(13)); + + mem_0_12: ROM128X1A + generic map (initval=> X"EDEFFDEBFDEFFDEB7BFFB3E718FFD7FF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(12)); + + mem_0_11: ROM128X1A + generic map (initval=> X"F679B7FFEE79B7FFEFDFFA97BFFFFFDF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(11)); + + mem_0_10: ROM128X1A + generic map (initval=> X"F0BFD7FFB8BFD7FFEFFE7A176DFFFFFE") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(10)); + + mem_0_9: ROM128X1A + generic map (initval=> X"EFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(9)); + + mem_0_8: ROM128X1A + generic map (initval=> X"DCFF9FFEECFF9FFFBFFFF9976DFFFFFF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(8)); + + mem_0_7: ROM128X1A + generic map (initval=> X"9FF2FE59FFF2FE585CA3D3C7D0FFB0A3") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(7)); + + mem_0_6: ROM128X1A + generic map (initval=> X"B7F2F69DFFF2F69DDC8B93C7D0FF388B") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(6)); + + mem_0_5: ROM128X1A + generic map (initval=> X"7F100615F7100614FC8EFFC3E3FF288E") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(5)); + + mem_0_4: ROM128X1A + generic map (initval=> X"3F180215F7180214FEBABFF7EBFF2ABA") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(4)); + + mem_0_3: ROM128X1A + generic map (initval=> X"7BD56B4353D56B42DC92BFA7DAFF8492") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM128X1A + generic map (initval=> X"7F551A69DF551A69FC24FF85FFFFD024") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM128X1A + generic map (initval=> X"3F581AE99F581AE87C60FFF5F7FFD060") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM128X1A + generic map (initval=> X"7BE07F0193E07F007C12FFA7F2FF0012") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure;
Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd (revision 6) @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +-- Module Version: 2.8 +-- Fri Jan 13 23:14:11 2017 + +-- parameterized module component declaration +component DistRomAsciiDecoder + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(13 downto 0)); +end component; + +-- parameterized module component instance +__ : DistRomAsciiDecoder + port map (Address(6 downto 0)=>__, Q(13 downto 0)=>__);
Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl (revision 6) @@ -0,0 +1,100 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "DistRomAsciiDecoder" +set lang "vhdl" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "sa5p00g" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_ngd.tcl =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_ngd.tcl (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_ngd.tcl (revision 6) @@ -0,0 +1,74 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "DistRomAsciiDecoder" +set Para(Module) "Distributed_ROM" +set Para(libname) ecp5um5g +set Para(arch_name) sa5p00g +set Para(PartType) "LFE5UM5G-45F" + +set Para(tech_syn) ecp5um5g +set Para(tech_cae) ecp5um5g +set Para(Package) "CABGA381" +set Para(SpeedGrade) "8" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd (revision 6) @@ -0,0 +1,42 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component DistRomAsciiDecoder + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(13 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(13 downto 0); +begin + u1 : DistRomAsciiDecoder + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test;
Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.cst =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.cst (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.cst (revision 6) @@ -0,0 +1,3 @@ +Date=01/13/2017 +Time=23:10:29 + Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.lpc =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.lpc (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.lpc (revision 6) @@ -0,0 +1,40 @@ +[Device] +Family=ecp5um5g +PartType=LFE5UM5G-45F +PartName=LFE5UM5G-45F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.8 +ModuleName=Dist_ROM_ASCII_Decoder +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=01/13/2017 +Time=23:10:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=127 +Data=14 +LUT=0 +MemFile=c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem +MemFormat=bin + +[FilesGenerated] +c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem=mem + +[Command] +cmd_line= -w -n Dist_ROM_ASCII_Decoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 127 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin Index: Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.srp =================================================================== --- Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.srp (nonexistent) +++ Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.srp (revision 6) @@ -0,0 +1,10 @@ +SCUBA, Version Diamond (64-bit) 3.8.0.115.3 +Fri Jan 13 23:10:29 2017 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n Dist_ROM_ASCII_Decoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 127 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin Index: Sources/Decoding_Table/ROM_Init_Vals.csv =================================================================== --- Sources/Decoding_Table/ROM_Init_Vals.csv (nonexistent) +++ Sources/Decoding_Table/ROM_Init_Vals.csv (revision 6) @@ -0,0 +1,128 @@ +00,01101111000000 +01,11111111111001 +02,11111100100100 +03,11111101110000 +04,11111100011001 +05,11011110010110 +06,11111100000010 +07,11111111111000 +08,11111100000000 +09,11111100010000 +0A,11111100001000 +0B,10110101110000 +0C,11111111000110 +0D,10110111110000 +0E,11111100000110 +0F,11111110001110 +10,11111111111111 +11,11111111111111 +12,11111111111111 +13,11111111111111 +14,11111111111111 +15,11111111111111 +16,11111111111111 +17,11111111111111 +18,10110100110110 +19,10101000111111 +1A,10110100000110 +1B,11111100011100 +1C,11101011001111 +1D,10110100110111 +1E,00010111111111 +1F,10100011111111 +20,11111111111111 +21,11111111111001 +22,11110111011111 +23,00000000000000 +24,10110100010010 +25,01001000011011 +26,01001011110010 +27,11101111111111 +28,11001111111111 +29,01111011111111 +2A,00000000111111 +2B,10110100111111 +2C,01111111111111 +2D,11111100111111 +2E,10111110100111 +2F,01101111111111 +30,01101111000000 +31,11111111111001 +32,11111100100100 +33,11111101110000 +34,11111100011001 +35,11011110010110 +36,11111100000010 +37,11111111111000 +38,11111100000000 +39,11111100010000 +3A,10110111111111 +3B,01110111111111 +3C,11001111111111 +3D,11111100110111 +3E,01111011111111 +3F,10111101111100 +40,11110101000100 +41,11111100001000 +42,10110101110000 +43,11111111000110 +44,10110111110000 +45,11111100000110 +46,11111110001110 +47,11111101000010 +48,11111100001001 +49,10110111111111 +4A,11111111100001 +4B,11001110001111 +4C,11111111000111 +4D,11101011001001 +4E,11011011001001 +4F,11111111000000 +50,11111100001100 +51,11011111000000 +52,11011100001100 +53,11111100010010 +54,10110111111110 +55,11111111000001 +56,01101111001111 +57,01011111001001 +58,01001011111111 +59,10101011111111 +5A,01101111110110 +5B,11111111000110 +5C,11011011111111 +5D,11111111110000 +5E,01101111111100 +5F,11111111110111 +60,11111011111111 +61,11111100001000 +62,10110101110000 +63,11111111000110 +64,10110111110000 +65,11111100000110 +66,11111110001110 +67,11111101000010 +68,11111100001001 +69,10110111111111 +6A,11111111100001 +6B,11001110001111 +6C,11111111000111 +6D,11101011001001 +6E,11011011001001 +6F,11111111000000 +70,11111100001100 +71,11011111000000 +72,11011100001100 +73,11111100010010 +74,10110111111110 +75,11111111000001 +76,01101111001111 +77,01011111001001 +78,01001011111111 +79,10101011111111 +7A,01101111110110 +7B,11001110111111 +7C,10110111111111 +7D,01111001111111 +7E,11111100101101 +7F,11111111000000 \ No newline at end of file Index: Sources/Decoding_Table/RomInitValsBin.mem =================================================================== --- Sources/Decoding_Table/RomInitValsBin.mem (nonexistent) +++ Sources/Decoding_Table/RomInitValsBin.mem (revision 6) @@ -0,0 +1,128 @@ +01101111000000 +11111111111001 +11111100100100 +11111101110000 +11111100011001 +11011110010110 +11111100000010 +11111111111000 +11111100000000 +11111100010000 +11111100001000 +10110101110000 +11111111000110 +10110111110000 +11111100000110 +11111110001110 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +10110100110110 +10101000111111 +10110100000110 +11111100011100 +11101011001111 +10110100110111 +00010111111111 +10100011111111 +11111111111111 +11111111111001 +11110111011111 +00000000000000 +10110100010010 +01001000011011 +01001011110010 +11101111111111 +11001111111111 +01111011111111 +00000000111111 +10110100111111 +01111111111111 +11111100111111 +10111110100111 +01101111111111 +01101111000000 +11111111111001 +11111100100100 +11111101110000 +11111100011001 +11011110010110 +11111100000010 +11111111111000 +11111100000000 +11111100010000 +10110111111111 +01110111111111 +11001111111111 +11111100110111 +01111011111111 +10111101111100 +11110101000100 +11111100001000 +10110101110000 +11111111000110 +10110111110000 +11111100000110 +11111110001110 +11111101000010 +11111100001001 +10110111111111 +11111111100001 +11001110001111 +11111111000111 +11101011001001 +11011011001001 +11111111000000 +11111100001100 +11011111000000 +11011100001100 +11111100010010 +10110111111110 +11111111000001 +01101111001111 +01011111001001 +01001011111111 +10101011111111 +01101111110110 +11111111000110 +11011011111111 +11111111110000 +01101111111100 +11111111110111 +11111011111111 +11111100001000 +10110101110000 +11111111000110 +10110111110000 +11111100000110 +11111110001110 +11111101000010 +11111100001001 +10110111111111 +11111111100001 +11001110001111 +11111111000111 +11101011001001 +11011011001001 +11111111000000 +11111100001100 +11011111000000 +11011100001100 +11111100010010 +10110111111110 +11111111000001 +01101111001111 +01011111001001 +01001011111111 +10101011111111 +01101111110110 +11001110111111 +10110111111111 +01111001111111 +11111100101101 +11111111000000 \ No newline at end of file Index: Sources/ASCIIDecoder.vhd =================================================================== --- Sources/ASCIIDecoder.vhd (revision 5) +++ Sources/ASCIIDecoder.vhd (revision 6) @@ -17,17 +17,30 @@ clk : in std_logic; -- input clock, xx MHz. reset : in std_logic; + --! ascii_in(7) represents the DP state so it is not decoded. + --! Symbol codes from 0x00 to 0x7F are without DP lit. Symbol codes from 0x80 to 0xFF have DP lit. ascii_in: in std_logic_vector(7 downto 0); - disp_data : out std_logic_vector(13 downto 0) + + disp_data : out std_logic_vector(14 downto 0) ); end ASCIIDecoder; architecture arch of ASCIIDecoder is + --! Q represents the symbol's bit mapping overlay over the 14-segment display. + signal Q : std_logic_vector(13 downto 0); begin ---! @details T +--! @details Decoding table +rom_decoding_table: entity work.DistRomAsciiDecoder +port map( + Address => ascii_in(6 downto 0), + Q => Q +); +--! Inversion of ascii_in(7) is needed as '0' is display segment active level +disp_data <= (not ascii_in(7)) & Q; + end arch;
/Sources/DisplayDriverWrapper.vhd
7,7 → 7,7
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
--! @file
--! @brief Top wrapper for design FPGA prove.
14,10 → 14,10
--! @details This wrapper is designed for Lattice ECP5-5G Versa Development Kit.
entity DisplayDriverWrapper is
port (
clk : in std_logic; --! input clock, xx MHz.
rst : in std_logic; --! active high
clk : in std_logic; --! input clock, xx MHz.
n_rst : in std_logic; --! active low on board. active high in design.
button : in std_logic; --! dev board tact switch to scroll through some test symbols
button : in std_logic; --! dev board tact switch to scroll through some test symbols, active low
--! Typically the data fed to display (single or multiple) is provided for single display at a time.
--! If multiple displays are required together with data goes display select (according typical dynamic display indication).
29,20 → 29,64
disp_sel : out std_logic
);
attribute syn_force_pad: boolean;
attribute syn_force_pad of clk, rst, button, disp_sel, disp_data: signal is true;
attribute syn_force_pad of clk, n_rst, button, disp_sel, disp_data: signal is true;
end DisplayDriverWrapper;
 
--! @details The architecture consists of the DisplayDriverwDecoder_Top itself (as DUT) plus
--! sample symbol generator triggered by the button on the dev board
architecture arch of DisplayDriverWrapper is
signal empty: std_logic;
signal rst: std_logic;
--! Debounce the glitches shorter than 4 clock cycles. Expand at will according the clock speed and glitch duration to filter.
signal bttn_state_fifo: unsigned(3 downto 0);
--! Active high i.e. '1' means "button pressed"
signal bttn_state: std_logic;
--! Incremented by 1 each time button is clicked. Provides ASCII symbol code for test purposes
--! Counter range is double the decoder table size because codes from 0x00 to 0x7F are the symbols with decimal point dark.
--! Codes from 0x80 to 0xFF are the same symbols but with decimal point lit. The decoder should handle this. The counter is lineary incremented.
signal symbol_scan_cntr: unsigned(7 downto 0);
begin
 
--! invert n_rst to make it active high on design recommendation
rst <= not n_rst;
 
BtnDebouncer:process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bttn_state_fifo <= (others=>'1'); -- active low
bttn_state <= '0'; -- active high
else
bttn_state_fifo <= shift_left(bttn_state_fifo,1);
bttn_state_fifo(bttn_state_fifo'right) <= button;
if bttn_state_fifo = "0000" then -- button actuated for more than X clocks and no bounces present
bttn_state <= '1'; -- report button is actuated
else
bttn_state <= '0';
end if;
end if;
end if;
end process;
 
 
AddrScanCntr:process(rst,bttn_state)
begin
if rst='1' then
symbol_scan_cntr <= (others=>'0');
elsif rising_edge(bttn_state) then -- TODO: Fix this to edge detector implementation
symbol_scan_cntr <= symbol_scan_cntr + 1; -- I count ont the natural rolloff of this counter
end if;
end process;
 
 
DDwD_Top:entity work.DisplayDriverwDecoder_Top
port map(
clk => clk,
reset => rst,
ascii_in => (others=>'0'),
ascii_in => std_logic_vector(symbol_scan_cntr),
wr_en => '0',
disp_data => disp_data,
disp_sel => disp_sel
/Sources/DisplayDriverwDecoder_Top.vhd
32,9 → 32,9
--! If multiple displays are required disp_sel signal must be provided (according typical dynamic display indication).
--!
--! \section disp_data_bit_mapping Display Segment Bit Mapping
--! |Bit Number |0 | 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14|
--! |Bit Number | 14| 13| 12| 11| 10| 9| 8| 7| 6| 5| 4| 3| 2| 1|0 |
--! |:--------: |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|
--! |Display Segment|a | b| c| d| e| f| g1| g2| h| i| j| k| l| m| dp|
--! |Display Segment| dp| m| l| k| j| i| h| g2| g1| f| e| d| c| b|a |
--! Note that there is no standard way to name the segments.
--! Current data bits correspondt to display segments according this picture: https://www.maximintegrated.com/en/images/appnotes/3211/3211Fig02.gif
disp_data : out std_logic_vector(14 downto 0);
71,23 → 71,18
--!
--! etc...
ascii_in_reg:process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
ascii_reg <= x"52"; -- display 'R' while reset is hold
else
if wr_en = '1' then
ascii_reg <= ascii_in;
end if;
end if;
end if;
end process;
ascii_decoder_module:entity work.ASCIIDecoder
port map(
clk => clk,
reset => reset,
ascii_in => ascii_in,
disp_data => disp_data
);
disp_sel <= '0'; -- TODO: implement this correctly
 
-- disp_data <= "110110111110000"; -- D
disp_data <= "010110101110000"; -- B.
-- disp_data <= "010110101110000"; -- B.
 
end arch;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.