URL
https://opencores.org/ocsvn/soc_maker/soc_maker/trunk
Subversion Repositories soc_maker
Compare Revisions
- This comparison shows the changes necessary to convert path
/soc_maker/trunk/core_lib/cores/wb_connect
- from Rev 7 to Rev 10
- ↔ Reverse comparison
Rev 7 → Rev 10
/wb_connect.yaml
1,7 → 1,7
SOCM_CORE |
name: wb_connect |
description: A block to connect RISC and peripheral controllers together |
version: "1" |
id: wb_connect,1 |
license: LGPL |
licensefile: |
author: Damjan Lampret |
13,7 → 13,7
:clk: SOCM_IFC |
name: clk |
dir: 1 |
version: "1" |
id: clk,1 |
ports: |
:wb_clk_i: SOCM_PORT |
len: 1 |
22,7 → 22,7
:rst: SOCM_IFC |
name: rst |
dir: 1 |
version: "1" |
id: rst,1 |
ports: |
:wb_rst_i: SOCM_PORT |
len: 1 |
33,7 → 33,7
:i0: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i0_wb_clk_o: SOCM_PORT |
defn: clk |
71,7 → 71,7
:i1: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i1_wb_clk_o: SOCM_PORT |
defn: clk |
109,7 → 109,7
:i2: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i2_wb_clk_o: SOCM_PORT |
defn: clk |
147,7 → 147,7
:i3: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i3_wb_clk_o: SOCM_PORT |
defn: clk |
185,7 → 185,7
:i4: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i4_wb_clk_o: SOCM_PORT |
defn: clk |
223,7 → 223,7
:i5: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i5_wb_clk_o: SOCM_PORT |
defn: clk |
261,7 → 261,7
:i6: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i6_wb_clk_o: SOCM_PORT |
defn: clk |
299,7 → 299,7
:i7: SOCM_IFC |
name: wishbone_ma |
dir: 0 |
version: "b3" |
id: wishbone_ma,b3 |
ports: |
:i7_wb_clk_o: SOCM_PORT |
defn: clk |
337,7 → 337,7
:t0: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t0_wb_clk_o: SOCM_PORT |
defn: clk |
375,7 → 375,7
:t1: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t1_wb_clk_o: SOCM_PORT |
defn: clk |
413,7 → 413,7
:t2: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t2_wb_clk_o: SOCM_PORT |
defn: clk |
451,7 → 451,7
:t3: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t3_wb_clk_o: SOCM_PORT |
defn: clk |
489,7 → 489,7
:t4: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t4_wb_clk_o: SOCM_PORT |
defn: clk |
527,7 → 527,7
:t5: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t5_wb_clk_o: SOCM_PORT |
defn: clk |
565,7 → 565,7
:t6: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t6_wb_clk_o: SOCM_PORT |
defn: clk |
603,7 → 603,7
:t7: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t7_wb_clk_o: SOCM_PORT |
defn: clk |
641,7 → 641,7
:t8: SOCM_IFC |
name: wishbone_sl |
dir: 0 |
version: "b3" |
id: wishbone_sl,b3 |
ports: |
:t8_wb_clk_o: SOCM_PORT |
defn: clk |