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Subversion Repositories soc_maker

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  • This comparison shows the changes necessary to convert path 
    /soc_maker/trunk/core_lib
    from Rev 8 to Rev 10
    ↔ Reverse comparison
  •

Rev 8 → Rev 10

/interfaces/clk_rst/single.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: single
version: "1"
id: single,1
ports:
:single:
:dir: 0
/interfaces/clk_rst/rst.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: rst
version: "1"
id: rst,1
ports:
:rst:
:dir: 0
/interfaces/clk_rst/clk.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: clk
version: "1"
id: clk,1
ports:
:clk:
:dir: 0
/interfaces/jtag/jtag.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: jtag
version: "1"
id: jtag,1
ports:
:tck:
:dir: 1
/interfaces/jtag/jtag_tap.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: jtag_tap
version: "1"
id: jtag_tap,1
ports:
:tck:
:dir: 0
/interfaces/debug/debug.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: debug
version: "1"
id: debug,1
ports:
:dbg_stall:
:dir: 0
/interfaces/power/or_power.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: or_power_management
version: "1"
id: or_power_management,1
ports:
:pm_cpustall:
:dir: 0
/interfaces/wishbone/wishbone_ma_b3.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: wishbone_ma
version: "b3"
name: Wishbone Master
id: wishbone_ma,b3
ports:
:clk:
:dir: 0
/interfaces/wishbone/wishbone_sl_b3.yaml
1,6 → 1,6
SOCM_IFC_SPC
name: wishbone_sl
version: "b3"
name: Wishbone Slave
id: wishbone_sl,b3
ports:
:clk:
:dir: 0
/cores/wb_connect/wb_connect.yaml
1,7 → 1,7
SOCM_CORE
name: wb_connect
description: A block to connect RISC and peripheral controllers together
version: "1"
id: wb_connect,1
license: LGPL
licensefile:
author: Damjan Lampret
13,7 → 13,7
:clk: SOCM_IFC
name: clk
dir: 1
version: "1"
id: clk,1
ports:
:wb_clk_i: SOCM_PORT
len: 1
22,7 → 22,7
:rst: SOCM_IFC
name: rst
dir: 1
version: "1"
id: rst,1
ports:
:wb_rst_i: SOCM_PORT
len: 1
33,7 → 33,7
:i0: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i0_wb_clk_o: SOCM_PORT
defn: clk
71,7 → 71,7
:i1: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i1_wb_clk_o: SOCM_PORT
defn: clk
109,7 → 109,7
:i2: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i2_wb_clk_o: SOCM_PORT
defn: clk
147,7 → 147,7
:i3: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i3_wb_clk_o: SOCM_PORT
defn: clk
185,7 → 185,7
:i4: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i4_wb_clk_o: SOCM_PORT
defn: clk
223,7 → 223,7
:i5: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i5_wb_clk_o: SOCM_PORT
defn: clk
261,7 → 261,7
:i6: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i6_wb_clk_o: SOCM_PORT
defn: clk
299,7 → 299,7
:i7: SOCM_IFC
name: wishbone_ma
dir: 0
version: "b3"
id: wishbone_ma,b3
ports:
:i7_wb_clk_o: SOCM_PORT
defn: clk
337,7 → 337,7
:t0: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t0_wb_clk_o: SOCM_PORT
defn: clk
375,7 → 375,7
:t1: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t1_wb_clk_o: SOCM_PORT
defn: clk
413,7 → 413,7
:t2: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t2_wb_clk_o: SOCM_PORT
defn: clk
451,7 → 451,7
:t3: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t3_wb_clk_o: SOCM_PORT
defn: clk
489,7 → 489,7
:t4: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t4_wb_clk_o: SOCM_PORT
defn: clk
527,7 → 527,7
:t5: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t5_wb_clk_o: SOCM_PORT
defn: clk
565,7 → 565,7
:t6: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t6_wb_clk_o: SOCM_PORT
defn: clk
603,7 → 603,7
:t7: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t7_wb_clk_o: SOCM_PORT
defn: clk
641,7 → 641,7
:t8: SOCM_IFC
name: wishbone_sl
dir: 0
version: "b3"
id: wishbone_sl,b3
ports:
:t8_wb_clk_o: SOCM_PORT
defn: clk
/cores/or1200_rel2/01_or1200.yaml
1,7 → 1,7
SOCM_CORE
name: or1200
name: OpenRISC 1200
description: OpenRISC CPU
version: rel2
id: or1200,rel2
license: LGPL
licensefile:
author:
12,7 → 12,7
:clmode: SOCM_IFC
name: single
dir: 1
version: "1"
id: single,1
ports:
:clmode_i: SOCM_PORT
len: 2
21,7 → 21,7
:pic_ints: SOCM_IFC
name: single
dir: 1
version: "1"
id: single,1
ports:
:pic_ints_i: SOCM_PORT
len: 20
30,7 → 30,7
:clk: SOCM_IFC
name: clk
dir: 1
version: "1"
id: clk,1
ports:
:clk_i: SOCM_PORT
len: 1
39,7 → 39,7
:rst: SOCM_IFC
name: rst
dir: 1
version: "1"
id: rst,1
ports:
:rst_i: SOCM_PORT
len: 1
48,7 → 48,7
:wb_instruction: SOCM_IFC
name: wishbone_ma
dir: 1
version: "b3"
id: wishbone_ma,b3
ports:
:iwb_clk_i: SOCM_PORT
defn: clk
90,7 → 90,7
:wb_data: SOCM_IFC
name: wishbone_ma
dir: 1
version: "b3"
id: wishbone_ma,b3
ports:
:dwb_clk_i: SOCM_PORT
defn: clk
132,7 → 132,7
:ext_debug: SOCM_IFC
name: debug
dir: 1
version: "1"
id: debug,1
ports:
:dbg_stall_i: SOCM_PORT
defn: dbg_stall
174,7 → 174,7
:pow_man: SOCM_IFC
name: or_power_management
dir: 1
version: "1"
id: or_power_management,1
ports:
:pm_cpustall_i: SOCM_PORT
len: 1
/cores/ram_wb/ram_wb.yaml
1,7 → 1,7
SOCM_CORE
name: ram_wb
name: Wishbone RAM
description: Onchip-RAM
version: b3
id: ram_wb,b3
license: LGPL
licensefile:
author:
11,9 → 11,9
 
interfaces:
:wb_ifc: SOCM_IFC
name: wishbone_sl
name: Wishbone IFC
dir: 1
version: "b3"
id: wishbone_sl,b3
ports:
:wb_adr_i: SOCM_PORT
len: 32
/cores/adv_debug_sys/01_adv_debug_sys.yaml
1,7 → 1,7
SOCM_CORE
name: adv_debug_sys
name: Advanced Debug System
description: Advanced Debug System
version: ads_3
id: adv_debug_sys,ads_3
license: LGPL
licensefile:
author:
16,7 → 16,7
:jtag: SOCM_IFC
name: jtag_tap
dir: 1
version: "1"
id: jtag_tap,1
ports:
:tck_i: SOCM_PORT
len: 1
53,7 → 53,7
:wb_ifc: SOCM_IFC
name: wishbone_ma
dir: 1
version: "b3"
id: wishbone_ma,b3
ports:
:wb_clk_i: SOCM_PORT
len: 1
101,7 → 101,7
:cpu0_dbg_clk: SOCM_IFC
name: clk
dir: 1
version: "1"
id: clk,1
ports:
:cpu0_clk_i: SOCM_PORT
len: 1
110,7 → 110,7
:cpu0_dbg_rst: SOCM_IFC
name: rst
dir: 0
version: "1"
id: rst,1
ports:
:cpu0_rst_o: SOCM_PORT
len: 1
119,7 → 119,7
:cpu0_dbg: SOCM_IFC
name: debug
dir: 0
version: "1"
id: debug,1
ports:
:cpu0_addr_o: SOCM_PORT
len: 32

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