OpenCores
URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /soc_maker/trunk/core_lib
    from Rev 5 to Rev 7
    ↔ Reverse comparison
  •

Rev 5 → Rev 7

/interfaces/jtag/jtag.yaml
0,0 → 1,9
SOCM_IFC_SPC
name: jtag
version: "1"
ports:
:tck: 1
:tdi: 1
:tdo: 0
:rst: 1
 
/interfaces/jtag/jtag_tap.yaml
0,0 → 1,13
SOCM_IFC_SPC
name: jtag_tap
version: "1"
ports:
:tck: 0
:tdi: 0
:tdo: 1
:rst: 0
:shift: 0
:pause: 0
:update: 0
:capture: 0
:select: 0
/interfaces/debug/debug.yaml
11,6 → 11,6
:dbg_stb: 0
:dbg_we: 0
:dbg_adr: 0
:dbg_dat: 0
:dbg_dat: 1
:dbg_dat_i: 1
:dbg_dat_o: 0
:dbg_ack: 1
/interfaces/wishbone/wishbone_ma_b3.yaml
2,8 → 2,10
name: wishbone_ma
version: "b3"
ports:
:dat_i: 0
:dat_o: 1
:clk: 0
:rst: 0
:dat_i: 1
:dat_o: 0
:tgd_i: 1
:tgd_o: 0
:adr: 1
17,3 → 19,6
:tgc: 1
:we: 1
:ack: 0
:cab: 1
:cti: 1
:bte: 1
/interfaces/wishbone/wishbone_sl_b3.yaml
2,8 → 2,10
name: wishbone_sl
version: "b3"
ports:
:dat_i: 0
:dat_o: 1
:clk: 0
:rst: 0
:dat_i: 1
:dat_o: 0
:tgd_i: 1
:tgd_o: 0
:ack: 1
17,4 → 19,5
:tga: 0
:tgc: 0
:we: 0
 
:bte: 0
:cti: 0
/inc.yaml
2,7 → 2,10
dirs:
- cores/or1200_rel2
- cores/wb_connect
- cores/adv_debug_sys
- cores/ram_wb
- interfaces/clk_rst
- interfaces/debug
- interfaces/power
- interfaces/wishbone
- interfaces/jtag
/cores/wb_connect/wb_connect.yaml
8,11 → 8,39
authormail: lampret@opencores.org
toplevel: minsoc_tc_top
interfaces:
 
 
:clk: SOCM_IFC
name: clk
dir: 1
version: "1"
ports:
:wb_clk_i: SOCM_PORT
len: 1
defn: clk
:rst: SOCM_IFC
name: rst
dir: 1
version: "1"
ports:
:wb_rst_i: SOCM_PORT
len: 1
defn: rst
 
 
 
:i0: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i0_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i0_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i0_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
24,7 → 52,7
len: 32
:i0_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i0_wb_we_i: SOCM_PORT
defn: we
len: 1
42,9 → 70,15
len: 1
:i1: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i1_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i1_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i1_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
56,7 → 90,7
len: 32
:i1_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i1_wb_we_i: SOCM_PORT
defn: we
len: 1
74,9 → 108,15
len: 1
:i2: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i2_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i2_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i2_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
88,7 → 128,7
len: 32
:i2_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i2_wb_we_i: SOCM_PORT
defn: we
len: 1
106,9 → 146,15
len: 1
:i3: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i3_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i3_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i3_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
120,7 → 166,7
len: 32
:i3_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i3_wb_we_i: SOCM_PORT
defn: we
len: 1
138,9 → 184,15
len: 1
:i4: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i4_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i4_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i4_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
152,7 → 204,7
len: 32
:i4_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i4_wb_we_i: SOCM_PORT
defn: we
len: 1
170,9 → 222,15
len: 1
:i5: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i5_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i5_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i5_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
184,7 → 242,7
len: 32
:i5_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i5_wb_we_i: SOCM_PORT
defn: we
len: 1
202,9 → 260,15
len: 1
:i6: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i6_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i6_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i6_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
216,7 → 280,7
len: 32
:i6_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i6_wb_we_i: SOCM_PORT
defn: we
len: 1
234,9 → 298,15
len: 1
:i7: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i7_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i7_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i7_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
248,7 → 318,7
len: 32
:i7_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i7_wb_we_i: SOCM_PORT
defn: we
len: 1
266,9 → 336,15
len: 1
:t0: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t0_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t0_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t0_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
280,12 → 356,12
len: 32
:t0_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t0_wb_we_o: SOCM_PORT
defn: we
len: 1
:t0_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t0_wb_dat_i: SOCM_PORT
defn: dat_i
298,9 → 374,15
len: 1
:t1: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t1_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t1_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t1_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
312,12 → 394,12
len: 32
:t1_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t1_wb_we_o: SOCM_PORT
defn: we
len: 1
:t1_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t1_wb_dat_i: SOCM_PORT
defn: dat_i
330,9 → 412,15
len: 1
:t2: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t2_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t2_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t2_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
344,12 → 432,12
len: 32
:t2_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t2_wb_we_o: SOCM_PORT
defn: we
len: 1
:t2_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t2_wb_dat_i: SOCM_PORT
defn: dat_i
362,9 → 450,15
len: 1
:t3: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t3_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t3_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t3_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
376,12 → 470,12
len: 32
:t3_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t3_wb_we_o: SOCM_PORT
defn: we
len: 1
:t3_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t3_wb_dat_i: SOCM_PORT
defn: dat_i
394,9 → 488,15
len: 1
:t4: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t4_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t4_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t4_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
408,12 → 508,12
len: 32
:t4_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t4_wb_we_o: SOCM_PORT
defn: we
len: 1
:t4_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t4_wb_dat_i: SOCM_PORT
defn: dat_i
426,9 → 526,15
len: 1
:t5: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t5_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t5_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t5_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
440,12 → 546,12
len: 32
:t5_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t5_wb_we_o: SOCM_PORT
defn: we
len: 1
:t5_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t5_wb_dat_i: SOCM_PORT
defn: dat_i
458,9 → 564,15
len: 1
:t6: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t6_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t6_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t6_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
472,12 → 584,12
len: 32
:t6_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t6_wb_we_o: SOCM_PORT
defn: we
len: 1
:t6_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t6_wb_dat_i: SOCM_PORT
defn: dat_i
490,9 → 602,15
len: 1
:t7: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t7_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t7_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t7_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
504,12 → 622,12
len: 32
:t7_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t7_wb_we_o: SOCM_PORT
defn: we
len: 1
:t7_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t7_wb_dat_i: SOCM_PORT
defn: dat_i
522,9 → 640,15
len: 1
:t8: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t8_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t8_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t8_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
536,12 → 660,12
len: 32
:t8_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t8_wb_we_o: SOCM_PORT
defn: we
len: 1
:t8_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t8_wb_dat_i: SOCM_PORT
defn: dat_i
/cores/wb_connect/minsoc_tc_top.v
98,6 → 98,8
wb_clk_i,
wb_rst_i,
 
i0_wb_clk_o,
i0_wb_rst_o,
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_adr_i,
108,6 → 110,8
i0_wb_ack_o,
i0_wb_err_o,
 
i1_wb_clk_o,
i1_wb_rst_o,
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_adr_i,
118,6 → 122,8
i1_wb_ack_o,
i1_wb_err_o,
 
i2_wb_clk_o,
i2_wb_rst_o,
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_adr_i,
128,6 → 134,8
i2_wb_ack_o,
i2_wb_err_o,
 
i3_wb_clk_o,
i3_wb_rst_o,
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_adr_i,
138,6 → 146,8
i3_wb_ack_o,
i3_wb_err_o,
 
i4_wb_clk_o,
i4_wb_rst_o,
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_adr_i,
148,6 → 158,8
i4_wb_ack_o,
i4_wb_err_o,
 
i5_wb_clk_o,
i5_wb_rst_o,
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_adr_i,
158,6 → 170,8
i5_wb_ack_o,
i5_wb_err_o,
 
i6_wb_clk_o,
i6_wb_rst_o,
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_adr_i,
168,6 → 182,8
i6_wb_ack_o,
i6_wb_err_o,
 
i7_wb_clk_o,
i7_wb_rst_o,
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_adr_i,
178,6 → 194,8
i7_wb_ack_o,
i7_wb_err_o,
 
t0_wb_clk_o,
t0_wb_rst_o,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_adr_o,
188,6 → 206,8
t0_wb_ack_i,
t0_wb_err_i,
 
t1_wb_clk_o,
t1_wb_rst_o,
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_adr_o,
198,6 → 218,8
t1_wb_ack_i,
t1_wb_err_i,
 
t2_wb_clk_o,
t2_wb_rst_o,
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_adr_o,
208,6 → 230,8
t2_wb_ack_i,
t2_wb_err_i,
 
t3_wb_clk_o,
t3_wb_rst_o,
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_adr_o,
218,6 → 242,8
t3_wb_ack_i,
t3_wb_err_i,
 
t4_wb_clk_o,
t4_wb_rst_o,
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_adr_o,
228,6 → 254,8
t4_wb_ack_i,
t4_wb_err_i,
 
t5_wb_clk_o,
t5_wb_rst_o,
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_adr_o,
238,6 → 266,8
t5_wb_ack_i,
t5_wb_err_i,
 
t6_wb_clk_o,
t6_wb_rst_o,
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_adr_o,
248,6 → 278,8
t6_wb_ack_i,
t6_wb_err_i,
 
t7_wb_clk_o,
t7_wb_rst_o,
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_adr_o,
258,6 → 290,8
t7_wb_ack_i,
t7_wb_err_i,
 
t8_wb_clk_o,
t8_wb_rst_o,
t8_wb_cyc_o,
t8_wb_stb_o,
t8_wb_adr_o,
515,6 → 549,49
input t8_wb_ack_i;
input t8_wb_err_i;
 
 
output i0_wb_clk_o;
output i0_wb_rst_o;
output i1_wb_clk_o;
output i1_wb_rst_o;
output i2_wb_clk_o;
output i2_wb_rst_o;
output i3_wb_clk_o;
output i3_wb_rst_o;
output i4_wb_clk_o;
output i4_wb_rst_o;
output i5_wb_clk_o;
output i5_wb_rst_o;
output i6_wb_clk_o;
output i6_wb_rst_o;
output i7_wb_clk_o;
output i7_wb_rst_o;
output t0_wb_clk_o;
output t0_wb_rst_o;
output t1_wb_clk_o;
output t1_wb_rst_o;
output t2_wb_clk_o;
output t2_wb_rst_o;
output t3_wb_clk_o;
output t3_wb_rst_o;
output t4_wb_clk_o;
output t4_wb_rst_o;
output t5_wb_clk_o;
output t5_wb_rst_o;
output t6_wb_clk_o;
output t6_wb_rst_o;
output t7_wb_clk_o;
output t7_wb_rst_o;
output t8_wb_clk_o;
output t8_wb_rst_o;
 
 
 
 
 
 
 
 
//
// Internal wires & registers
//
585,7 → 662,48
wire z_wb_ack_t;
wire z_wb_err_t;
 
 
//
// Assign clock and resets
//
assign i0_wb_clk_o = wb_clk_i;
assign i0_wb_rst_o = wb_rst_i;
assign i1_wb_clk_o = wb_clk_i;
assign i1_wb_rst_o = wb_rst_i;
assign i2_wb_clk_o = wb_clk_i;
assign i2_wb_rst_o = wb_rst_i;
assign i3_wb_clk_o = wb_clk_i;
assign i3_wb_rst_o = wb_rst_i;
assign i4_wb_clk_o = wb_clk_i;
assign i4_wb_rst_o = wb_rst_i;
assign i5_wb_clk_o = wb_clk_i;
assign i5_wb_rst_o = wb_rst_i;
assign i6_wb_clk_o = wb_clk_i;
assign i6_wb_rst_o = wb_rst_i;
assign i7_wb_clk_o = wb_clk_i;
assign i7_wb_rst_o = wb_rst_i;
assign t0_wb_clk_o = wb_clk_i;
assign t0_wb_rst_o = wb_rst_i;
assign t1_wb_clk_o = wb_clk_i;
assign t1_wb_rst_o = wb_rst_i;
assign t2_wb_clk_o = wb_clk_i;
assign t2_wb_rst_o = wb_rst_i;
assign t3_wb_clk_o = wb_clk_i;
assign t3_wb_rst_o = wb_rst_i;
assign t4_wb_clk_o = wb_clk_i;
assign t4_wb_rst_o = wb_rst_i;
assign t5_wb_clk_o = wb_clk_i;
assign t5_wb_rst_o = wb_rst_i;
assign t6_wb_clk_o = wb_clk_i;
assign t6_wb_rst_o = wb_rst_i;
assign t7_wb_clk_o = wb_clk_i;
assign t7_wb_rst_o = wb_rst_i;
assign t8_wb_clk_o = wb_clk_i;
assign t8_wb_rst_o = wb_rst_i;
 
 
 
//
// Outputs for initiators are ORed from both mi_to_st blocks
//
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
/cores/or1200_rel2/01_or1200.yaml
18,13 → 18,13
len: 2
defn: single
:pic_inst: SOCM_IFC
:pic_ints: SOCM_IFC
name: single
dir: 1
version: "1"
ports:
:pic_inst_i: SOCM_PORT
len: 2
:pic_ints_i: SOCM_PORT
len: 20
defn: single
:clk: SOCM_IFC
33,7 → 33,7
version: "1"
ports:
:clk_i: SOCM_PORT
len: 2
len: 1
defn: clk
:rst: SOCM_IFC
42,7 → 42,7
version: "1"
ports:
:rst_i: SOCM_PORT
len: 2
len: 1
defn: rst
:wb_instruction: SOCM_IFC
50,6 → 50,12
dir: 1
version: "b3"
ports:
:iwb_clk_i: SOCM_PORT
defn: clk
len: 1
:iwb_rst_i: SOCM_PORT
defn: rst
len: 1
:iwb_cyc_o: SOCM_PORT
defn: cyc
len: 1
61,7 → 67,7
len: 32
:iwb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:iwb_we_o: SOCM_PORT
defn: we
len: 1
78,7 → 84,7
defn: err
len: 1
:iwb_rty_i: SOCM_PORT
defn: err
defn: rty
len: 1
 
:wb_data: SOCM_IFC
86,6 → 92,12
dir: 1
version: "b3"
ports:
:dwb_clk_i: SOCM_PORT
defn: clk
len: 1
:dwb_rst_i: SOCM_PORT
defn: rst
len: 1
:dwb_cyc_o: SOCM_PORT
defn: cyc
len: 1
97,7 → 109,7
len: 32
:dwb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:dwb_we_o: SOCM_PORT
defn: we
len: 1
105,7 → 117,7
defn: dat_i
len: 32
:dwb_dat_i: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:dwb_ack_i: SOCM_PORT
defn: ack
114,7 → 126,7
defn: err
len: 1
:dwb_rty_i: SOCM_PORT
defn: err
defn: rty
len: 1
 
:ext_debug: SOCM_IFC
151,10 → 163,10
defn: dbg_adr
:dbg_dat_i: SOCM_PORT
len: 32
defn: dbg_dat
defn: dbg_dat_o
:dbg_dat_o: SOCM_PORT
len: 32
defn: dbg_dat
defn: dbg_dat_i
:dbg_ack_o: SOCM_PORT
len: 1
defn: dbg_ack
/cores/ram_wb/ram_wb.yaml
0,0 → 1,66
SOCM_CORE
name: ram_wb
description: Onchip-RAM
version: b3
license: LGPL
licensefile:
author:
authormail:
vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb@655 rtl
toplevel: ram_wb_b3
 
interfaces:
:wb_ifc: SOCM_IFC
name: wishbone_sl
dir: 1
version: "b3"
ports:
:wb_adr_i: SOCM_PORT
len: 32
defn: adr
:wb_bte_i: SOCM_PORT
len: 2
defn: bte
:wb_cti_i: SOCM_PORT
len: 3
defn: cti
:wb_cyc_i: SOCM_PORT
len: 1
defn: cyc
:wb_dat_i: SOCM_PORT
len: 32
defn: dat_o
:wb_sel_i: SOCM_PORT
len: 4
defn: sel
:wb_stb_i: SOCM_PORT
len: 1
defn: stb
:wb_we_i: SOCM_PORT
len: 1
defn: we
:wb_ack_o: SOCM_PORT
len: 1
defn: ack
:wb_err_o: SOCM_PORT
len: 1
defn: err
:wb_rty_o: SOCM_PORT
len: 1
defn: rty
:wb_dat_o: SOCM_PORT
len: 32
defn: dat_i
:wb_clk_i: SOCM_PORT
len: 1
defn: clk
:wb_rst_i: SOCM_PORT
len: 1
defn: rst
 
hdlfiles:
:ram_wb_b3: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/ram_wb_b3.v
/cores/adv_debug_sys/01_adv_debug_sys.yaml
0,0 → 1,245
SOCM_CORE
name: adv_debug_sys
description: Advanced Debug System
version: ads_3
license: LGPL
licensefile:
author:
authormail:
vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
toplevel: adbg_top
 
interfaces:
 
 
 
:jtag: SOCM_IFC
name: jtag_tap
dir: 1
version: "1"
ports:
:tck_i: SOCM_PORT
len: 1
defn: tck
:tdi_i: SOCM_PORT
len: 1
defn: tdi
:tdo_o: SOCM_PORT
len: 1
defn: tdo
:rst_i: SOCM_PORT
len: 1
defn: rst
 
:shift_dr_i: SOCM_PORT
len: 1
defn: shift
:pause_dr_i: SOCM_PORT
len: 1
defn: pause
:update_dr_i: SOCM_PORT
len: 1
defn: update
:capture_dr_i: SOCM_PORT
len: 1
defn: capture
:debug_select_i: SOCM_PORT
len: 1
defn: select
 
 
 
 
:wb_ifc: SOCM_IFC
name: wishbone_ma
dir: 1
version: "b3"
ports:
:wb_clk_i: SOCM_PORT
len: 1
defn: clk
:wb_rst_i: SOCM_PORT
len: 1
defn: rst
:wb_adr_o: SOCM_PORT
defn: adr
len: 32
:wb_dat_o: SOCM_PORT
defn: dat_i
len: 32
:wb_dat_i: SOCM_PORT
defn: dat_o
len: 32
:wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
:wb_stb_o: SOCM_PORT
defn: stb
len: 1
:wb_sel_o: SOCM_PORT
defn: sel
len: 4
:wb_we_o: SOCM_PORT
defn: we
len: 1
:wb_ack_i: SOCM_PORT
defn: ack
len: 1
:wb_cab_o: SOCM_PORT
defn: cab
len: 1
:wb_err_i: SOCM_PORT
defn: err
len: 1
:wb_cti_o: SOCM_PORT
defn: cti
len: 3
:wb_bte_o: SOCM_PORT
defn: bte
len: 2
 
:cpu0_dbg_clk: SOCM_IFC
name: clk
dir: 1
version: "1"
ports:
:cpu0_clk_i: SOCM_PORT
len: 1
defn: clk
 
:cpu0_dbg_rst: SOCM_IFC
name: rst
dir: 0
version: "1"
ports:
:cpu0_rst_o: SOCM_PORT
len: 1
defn: rst
 
:cpu0_dbg: SOCM_IFC
name: debug
dir: 0
version: "1"
ports:
:cpu0_addr_o: SOCM_PORT
len: 32
defn: dbg_adr
:cpu0_data_o: SOCM_PORT
len: 32
defn: dbg_dat_o
:cpu0_data_i: SOCM_PORT
len: 32
defn: dbg_dat_i
:cpu0_bp_i: SOCM_PORT
len: 1
defn: dbg_bpo
:cpu0_stall_o: SOCM_PORT
defn: dbg_stall
len: 1
:cpu0_stb_o: SOCM_PORT
len: 1
defn: dbg_stb
:cpu0_we_o: SOCM_PORT
len: 1
defn: dbg_we
:cpu0_ack_i: SOCM_PORT
len: 1
defn: dbg_ack
 
# :dbg_ewt_i: SOCM_PORT
# len: 1
# defn: dbg_ewt
# :dbg_lss_o: SOCM_PORT
# len: 4
# defn: dbg_lss
# :dbg_is_o: SOCM_PORT
# len: 2
# defn: dbg_iso
# :dbg_wp_o: SOCM_PORT
# len: 11
# defn: dbg_wpo
 
 
hdlfiles:
:adbg_top: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_top.v
 
:adbg_crc32: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_crc32.v
:adbg_defines: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_defines.v
:adbg_jsp_biu: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_jsp_biu.v
:adbg_jsp_module: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_jsp_module.v
:adbg_or1k_biu: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_or1k_biu.v
:adbg_or1k_defines: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_or1k_defines.v
:adbg_or1k_module: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_or1k_module.v
:adbg_or1k_status_reg: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_or1k_status_reg.v
:adbg_top: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_top.v
:adbg_wb_biu: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_wb_biu.v
:adbg_wb_defines: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_wb_defines.v
:adbg_wb_module: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/adbg_wb_module.v
:bytefifo: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/bytefifo.v
:syncflow: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/syncflop.v
:syncreg: SOCM_HDL_FILE
use_syn: true
use_sim: true
type: verilog
path: rtl/verilog/syncreg.v
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.