URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/digilentinc.com/Nexys2/ip/sram/rtl
- from Rev 131 to Rev 134
- ↔ Reverse comparison
Rev 131 → Rev 134
/xml/sram_def.xml
132,7 → 132,6
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>1024</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'b1}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
/xml/sram_dp.xml
132,7 → 132,6
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>1024</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'b1}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
|
/xml/sram_be.xml
123,7 → 123,6
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>1024</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'b1}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
/verilog/sram_def.v
25,7 → 25,6
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
MEM="NONE", |
INSTANCE_NAME="../../../../../children/") |
70,7 → 69,7
always@(posedge clk) l_raddr <= addr; |
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
78,7 → 77,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/verilog/lint/sram_def.v
5,7 → 5,6
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
19,5 → 18,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/verilog/lint/sram_dp.v
5,7 → 5,6
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
20,5 → 19,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/verilog/lint/sram_be.v
5,7 → 5,6
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
20,5 → 19,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/verilog/sram_dp.v
25,7 → 25,6
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
MEM="NONE", |
INSTANCE_NAME="../../../../../children/") |
74,7 → 73,7
always@(posedge clk) l_raddr <= raddr; |
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
82,7 → 81,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/verilog/sram_be.v
25,7 → 25,6
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
MEM="NONE", |
INSTANCE_NAME="../../../../../children/") |
77,7 → 76,7
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
85,7 → 84,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |