OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/Projects/digilentinc.com
    from Rev 133 to Rev 134
    ↔ Reverse comparison
  •

Rev 133 → Rev 134

/Nexys2/ip/sram/rtl/xml/sram_def.xml
132,7 → 132,6
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>1024</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'b1}}</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
/Nexys2/ip/sram/rtl/xml/sram_dp.xml
132,7 → 132,6
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>1024</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'b1}}</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
 
/Nexys2/ip/sram/rtl/xml/sram_be.xml
123,7 → 123,6
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>1024</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'b1}}</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
/Nexys2/ip/sram/rtl/verilog/sram_def.v
25,7 → 25,6
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
MEM="NONE",
INSTANCE_NAME="../../../../../children/")
70,7 → 69,7
always@(posedge clk) l_raddr <= addr;
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [WIDTH-1:0] tmp_rdata;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
always@(*) rdata = tmp_rdata;
end
else
78,7 → 77,7
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];
else rdata <= DEFAULT;
else rdata <= {WIDTH{1'b1}};
end
endgenerate
endmodule
/Nexys2/ip/sram/rtl/verilog/lint/sram_def.v
5,7 → 5,6
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
19,5 → 18,5
// Simple loop back for linting and code coverage
always@(posedge clk)
if( rd && cs ) rdata <= wdata;
else rdata <= DEFAULT;
else rdata <= {WIDTH{1'b1}};
endmodule
/Nexys2/ip/sram/rtl/verilog/lint/sram_dp.v
5,7 → 5,6
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
20,5 → 19,5
// Simple loop back for linting and code coverage
always@(posedge clk)
if( rd && cs ) rdata <= wdata;
else rdata <= DEFAULT;
else rdata <= {WIDTH{1'b1}};
endmodule
/Nexys2/ip/sram/rtl/verilog/lint/sram_be.v
5,7 → 5,6
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
20,5 → 19,5
// Simple loop back for linting and code coverage
always@(posedge clk)
if( rd && cs ) rdata <= wdata;
else rdata <= DEFAULT;
else rdata <= {WIDTH{1'b1}};
endmodule
/Nexys2/ip/sram/rtl/verilog/sram_dp.v
25,7 → 25,6
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
MEM="NONE",
INSTANCE_NAME="../../../../../children/")
74,7 → 73,7
always@(posedge clk) l_raddr <= raddr;
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [WIDTH-1:0] tmp_rdata;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
always@(*) rdata = tmp_rdata;
end
else
82,7 → 81,7
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}];
else rdata <= DEFAULT;
else rdata <= {WIDTH{1'b1}};
end
endgenerate
endmodule
/Nexys2/ip/sram/rtl/verilog/sram_be.v
25,7 → 25,6
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
MEM="NONE",
INSTANCE_NAME="../../../../../children/")
77,7 → 76,7
 
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [7:0] tmp_rdata;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
always@(*) rdata = tmp_rdata;
end
else
85,7 → 84,7
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];
else rdata <= DEFAULT;
else rdata <= {WIDTH{1'b1}};
end
endgenerate
endmodule
/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?>
<?xml version="1.0" encoding="utf-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
40,7 → 40,28
 
<spirit:componentGenerators>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog_pad</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>pad</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.fpga</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_ise_filelist</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
1267,30 → 1288,11
 
 
 
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog_pad</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>pad</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.fpga</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
</spirit:componentGenerators>
 
 
 
1339,15 → 1341,6
<spirit:modelParameter><spirit:name>CLOCK_SRC</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RESET_SENSE</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID</spirit:name><spirit:value>32'hf1c2e093</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_1</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_2</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_3</spirit:name><spirit:value>3</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_4</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_7</spirit:name><spirit:value>7</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_8</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_16</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_23</spirit:name><spirit:value>23</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH_40</spirit:name><spirit:value>40</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:views>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.