URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/Mos6502/ip/core
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/componentCfg.xml
26,8 → 26,20
</socgen:doc> |
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<socgen:configurations> |
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<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>VEC_TABLE</socgen:name><socgen:value>8'hff</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>BOOT_VEC</socgen:name><socgen:value>8'hfc</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
</socgen:configurations> |
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<socgen:sim> |
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/rtl/xml/core_def.design.xml
File deleted
/rtl/xml/core_def.xml
112,26 → 112,7
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
140,12 → 121,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>core_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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158,12 → 135,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>core_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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190,7 → 163,7
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:name>../verilog/sim/core_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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275,7 → 248,7
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:name>../verilog/syn/core_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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349,15 → 322,7
<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Mos6502" |
spirit:name="core" |
spirit:version="def.design"/> |
</spirit:view> |
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<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
/rtl/verilog/alu
42,6 → 42,7
reg c_result; |
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wire r_result; |
wire r_result_nc; |
wire [7:0] result; |
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wire [7:0] and_out; |
84,7 → 85,7
.alu_op_b ( alu_op_b ), |
.alu_op_c ( alu_op_c ), |
.result ( result ), |
.r_result ( ), |
.r_result ( r_result_nc ), |
.c_result ( r_result ), |
.v_result ( v_result ), |
.and_out ( and_out ), |