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Tools

URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

This comparison shows the changes necessary to convert path
```
/socgen/trunk/Projects/opencores.org/Mos6502/ip/cpu/sim
```
from Rev 133 to Rev 134
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 133 → Rev 134

/testbenches/xml/cpu_def_dutg.design.xml File deleted

/testbenches/xml/cpu_def_duth.design.xml

119,7 → 119,6

<spirit:configurableElementValue spirit:referenceId="BOOT_VEC">BOOT_VEC</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="CPU_ADD">CPU_ADD</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="PROG_ROM_ADD">PROG_ROM_ADD</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="PROG_ROM_FILE">PROG_ROM_FILE</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="PROG_ROM_WORDS">PROG_ROM_WORDS</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="VEC_TABLE">VEC_TABLE</spirit:configurableElementValue>

</spirit:configurableElementValues>

/testbenches/xml/cpu_bfm.design.xml

582,7 → 582,6

<spirit:configurableElementValue spirit:referenceId="WIDTH">16</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="ADDR">ROM_ADD</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="WORDS">ROM_WORDS</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="DEFAULT">16'hffff</spirit:configurableElementValue>

</spirit:configurableElementValues>

</spirit:componentInstance>

596,7 → 595,6

<spirit:configurableElementValue spirit:referenceId="WIDTH">16</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="ADDR">PROG_ROM_ADD</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="WORDS">PROG_ROM_WORDS</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="DEFAULT">16'hffff</spirit:configurableElementValue>

</spirit:configurableElementValues>

</spirit:componentInstance>

608,7 → 606,6

<spirit:configurableElementValues>

<spirit:configurableElementValue spirit:referenceId="ADDR">RAM_ADD</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="WORDS">RAM_WORDS</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="DEFAULT">16'hffff</spirit:configurableElementValue>

</spirit:configurableElementValues>

</spirit:componentInstance>

622,7 → 619,6

<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="ADDR">7</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="WORDS">128</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="DEFAULT">8'hff</spirit:configurableElementValue>

</spirit:configurableElementValues>

</spirit:componentInstance>

634,7 → 630,6

<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="ADDR">7</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="WORDS">128</spirit:configurableElementValue>

<spirit:configurableElementValue spirit:referenceId="DEFAULT">8'hff</spirit:configurableElementValue>

</spirit:configurableElementValues>

</spirit:componentInstance>

/testbenches/xml/cpu_def_dut.params.xml

30,7 → 30,6

</spirit:view>

</spirit:views>

<spirit:modelParameters>

    <spirit:modelParameter><spirit:name>PROG_ROM_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>

</spirit:modelParameters>

</spirit:model>

</spirit:component>

/testbenches/xml/cpu_def_tb.xml

51,20 → 51,9

   <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
     <spirit:parameters>
     <spirit:parameter>
-      <spirit:name>configuration</spirit:name>
-      <spirit:value>default</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
       <spirit:name>destination</spirit:name>
-      <spirit:value>tb.tb</spirit:value>
+      <spirit:value>cpu_def_tb</spirit:value>
     </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>dest_dir</spirit:name>
-      <spirit:value>../verilog</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>top</spirit:name>
-    </spirit:parameter>
   </spirit:parameters>
 </spirit:componentGenerator>

209,7 → 198,7

       <spirit:file>
         <spirit:logicalName></spirit:logicalName>
-        <spirit:name>../verilog/common/tb.tb</spirit:name>
+        <spirit:name>../verilog/common/cpu_def_tb</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
       </spirit:file>

226,7 → 215,7

       <spirit:file>
         <spirit:logicalName></spirit:logicalName>
-        <spirit:name>../verilog/common/tb.tb</spirit:name>
+        <spirit:name>../verilog/common/cpu_def_tb</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
       </spirit:file>

/testbenches/xml/cpu_def_lint.xml

41,45 → 41,9

-<spirit:componentGenerators>
-<spirit:componentGenerator>
-  <spirit:name>elab_verilog</spirit:name>
-  <spirit:phase>102.1</spirit:phase>
-  <spirit:apiType>none</spirit:apiType>
-  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
->
-  <spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
-    <spirit:parameters>
-    <spirit:parameter>
-      <spirit:name>configuration</spirit:name>
-      <spirit:value>default</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>dest_dir</spirit:name>
-      <spirit:value>io_ports</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
-</spirit:componentGenerator>
-<spirit:componentGenerator>
-  <spirit:name>gen_design</spirit:name>
-  <spirit:phase>102.1</spirit:phase>
-  <spirit:apiType>none</spirit:apiType>
-  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
->
-  <spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
-    <spirit:parameters>
-    <spirit:parameter>
-      <spirit:name>dest_dir</spirit:name>
-      <spirit:value>io_ports</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
-</spirit:componentGenerator>
-</spirit:componentGenerators>
 <spirit:model>

/testbenches/verilog/sram.load

1,4 → 1,4

parameter PREFIX ="../../../../../children/";

parameter PREFIX ="../../../../../../children/";

initial

begin