OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc
    from Rev 131 to Rev 133
    ↔ Reverse comparison
  •

Rev 131 → Rev 133

/Geda/html/adv_dbg_if_cpu1.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 583px; height: 302px;" alt="" src="../png/adv_dbg_if_cpu1_sym.png"><br>
<img style="width: 703px; height: 374px;" alt="" src="../png/adv_dbg_if_cpu1_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
92,6 → 92,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
98,6 → 116,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
104,6 → 134,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">debug_select_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
173,7 → 221,7
<br>
<br>
<br>
<img style="width: 583px; height: 302px;" alt="" src="../png/adv_dbg_if_cpu1_sch.png"><br>
<img style="width: 703px; height: 374px;" alt="" src="../png/adv_dbg_if_cpu1_sch.png"><br>
<b><br>
<br>
<br>
/Geda/html/adv_dbg_if_wb_cpu0_jsp.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 723px; height: 638px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jsp_sym.png"><br>
<img style="width: 723px; height: 710px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jsp_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
98,6 → 98,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
104,6 → 122,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
110,6 → 140,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">debug_select_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
347,7 → 395,7
<br>
<br>
<br>
<img style="width: 723px; height: 638px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jsp_sch.png"><br>
<img style="width: 723px; height: 710px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jsp_sch.png"><br>
<b><br>
<br>
<br>
/Geda/html/adv_dbg_if_wb_cpu0_jfifo.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 703px; height: 470px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jfifo_sym.png"><br>
<img style="width: 703px; height: 566px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jfifo_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
98,6 → 98,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
104,6 → 122,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
110,6 → 140,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">debug_select_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
287,7 → 335,7
<br>
<br>
<br>
<img style="width: 703px; height: 470px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jfifo_sch.png"><br>
<img style="width: 703px; height: 566px;" alt="" src="../png/adv_dbg_if_wb_cpu0_jfifo_sch.png"><br>
<b><br>
<br>
<br>
/Geda/html/adv_dbg_if_wb_cpu2_jsp.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 723px; height: 662px;" alt="" src="../png/adv_dbg_if_wb_cpu2_jsp_sym.png"><br>
<img style="width: 723px; height: 806px;" alt="" src="../png/adv_dbg_if_wb_cpu2_jsp_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
92,6 → 92,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
98,6 → 116,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
104,6 → 134,42
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
110,6 → 176,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
116,6 → 194,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu1_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">debug_select_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
347,7 → 443,7
<br>
<br>
<br>
<img style="width: 723px; height: 662px;" alt="" src="../png/adv_dbg_if_wb_cpu2_jsp_sch.png"><br>
<img style="width: 723px; height: 806px;" alt="" src="../png/adv_dbg_if_wb_cpu2_jsp_sch.png"><br>
<b><br>
<br>
<br>
/Geda/html/adv_dbg_if_wb_cpu0.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 643px; height: 422px;" alt="" src="../png/adv_dbg_if_wb_cpu0_sym.png"><br>
<img style="width: 703px; height: 494px;" alt="" src="../png/adv_dbg_if_wb_cpu0_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
92,6 → 92,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
98,6 → 116,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
104,6 → 134,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">debug_select_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
257,7 → 305,7
<br>
<br>
<br>
<img style="width: 643px; height: 422px;" alt="" src="../png/adv_dbg_if_wb_cpu0_sch.png"><br>
<img style="width: 703px; height: 494px;" alt="" src="../png/adv_dbg_if_wb_cpu0_sch.png"><br>
<b><br>
<br>
<br>
/Geda/html/adv_dbg_if_cpu0.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 583px; height: 302px;" alt="" src="../png/adv_dbg_if_cpu0_sym.png"><br>
<img style="width: 703px; height: 374px;" alt="" src="../png/adv_dbg_if_cpu0_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
92,6 → 92,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_ack_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_addr_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_bp_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_clk_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
98,6 → 116,18
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_i[31:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_data_o[31:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_rst_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
104,6 → 134,24
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stall_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_stb_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cpu0_we_o<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">debug_select_i<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
173,7 → 221,7
<br>
<br>
<br>
<img style="width: 583px; height: 302px;" alt="" src="../png/adv_dbg_if_cpu0_sch.png"><br>
<img style="width: 703px; height: 374px;" alt="" src="../png/adv_dbg_if_cpu0_sch.png"><br>
<b><br>
<br>
<br>
/Geda/src/adv_dbg_if_cpu0.v
1493,7 → 1493,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
1625,7 → 1625,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_cpu1.v
1493,7 → 1493,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
1625,7 → 1625,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_wb.v
1516,7 → 1516,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
1648,7 → 1648,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_wb_cpu0_jsp.v
3672,7 → 3672,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
3804,7 → 3804,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_jsp.v
1371,7 → 1371,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
1503,7 → 1503,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_wb_cpu0_jfifo.v
3378,7 → 3378,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
3510,7 → 3510,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_jfifo.v
1070,7 → 1070,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
1202,7 → 1202,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_wb_cpu2_jsp.v
3717,7 → 3717,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
3849,7 → 3849,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/src/adv_dbg_if_wb_cpu0.v
2657,7 → 2657,7
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
2789,7 → 2789,7
4'h6: DATA_OUT = reg5;
4'h7: DATA_OUT = reg6;
4'h8: DATA_OUT = reg7;
default: DATA_OUT = 8'hXX;
default: DATA_OUT = 8'h00;
endcase
end
endmodule
/Geda/sym/adv_dbg_if_cpu0.sym
1,20 → 1,20
v 20100214 1
B 300 0 2800 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
B 300 0 3800 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2650 5 10 1 1 0 0 1 1
device=adv_dbg_if_cpu0
T 400 2250 8 10 1 1 0 0 1 1
T 400 2850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=update_dr_i
T 400 200 5 10 0 1 0 1 1 1
T 400 200 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=tdi_i
pinnumber=update_dr_i
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
21,7 → 21,7
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=tck_i
pinnumber=tdi_i
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
28,7 → 28,7
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=shift_dr_i
pinnumber=tck_i
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
35,7 → 35,7
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=rst_i
pinnumber=shift_dr_i
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
42,7 → 42,7
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=debug_select_i
pinnumber=rst_i
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
49,7 → 49,7
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cpu0_clk_i
pinnumber=debug_select_i
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
56,21 → 56,77
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
pinnumber=cpu0_clk_i
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 3100 200 3400 200 4 0 1
P 300 1800 0 1800 4 0 1
{
T 3000 200 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 3100 200 5 10 0 1 0 7 1 1
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=cpu0_bp_i
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 3100 400 3400 400 4 0 1
P 300 2000 0 2000 4 0 1
{
T 3000 400 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 3100 400 5 10 0 1 0 7 1 1
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=cpu0_ack_i
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=cpu0_data_o[31:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=12
}
P 4100 400 4400 400 10 1 1
{
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=cpu0_addr_o[31:0]
T 4000 400 5 10 0 1 0 7 1 1
pinseq=13
}
P 4100 600 4400 600 4 0 1
{
T 4000 600 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 4100 600 5 10 0 1 0 7 1 1
pinseq=14
}
P 4100 800 4400 800 4 0 1
{
T 4000 800 5 10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4100 800 5 10 0 1 0 7 1 1
pinseq=15
}
P 4100 1000 4400 1000 4 0 1
{
T 4000 1000 5 10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4100 1000 5 10 0 1 0 7 1 1
pinseq=16
}
P 4100 1200 4400 1200 4 0 1
{
T 4000 1200 5 10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4100 1200 5 10 0 1 0 7 1 1
pinseq=17
}
P 4100 1400 4400 1400 4 0 1
{
T 4000 1400 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4100 1400 5 10 0 1 0 7 1 1
pinseq=18
}
/Geda/sym/adv_dbg_if_cpu1.sym
1,20 → 1,20
v 20100214 1
B 300 0 2800 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
B 300 0 3800 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2650 5 10 1 1 0 0 1 1
device=adv_dbg_if_cpu1
T 400 2250 8 10 1 1 0 0 1 1
T 400 2850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=update_dr_i
T 400 200 5 10 0 1 0 1 1 1
T 400 200 5 10 1 1 0 1 1 1
pinnumber=cpu1_data_i[31:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=tdi_i
pinnumber=update_dr_i
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
21,7 → 21,7
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=tck_i
pinnumber=tdi_i
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
28,7 → 28,7
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=shift_dr_i
pinnumber=tck_i
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
35,7 → 35,7
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=rst_i
pinnumber=shift_dr_i
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
42,7 → 42,7
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=debug_select_i
pinnumber=rst_i
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
49,7 → 49,7
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cpu1_clk_i
pinnumber=debug_select_i
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
56,21 → 56,77
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
pinnumber=cpu1_clk_i
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 3100 200 3400 200 4 0 1
P 300 1800 0 1800 4 0 1
{
T 3000 200 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 3100 200 5 10 0 1 0 7 1 1
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=cpu1_bp_i
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 3100 400 3400 400 4 0 1
P 300 2000 0 2000 4 0 1
{
T 3000 400 5 10 1 1 0 7 1 1
pinnumber=cpu1_rst_o
T 3100 400 5 10 0 1 0 7 1 1
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=cpu1_ack_i
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=cpu1_data_o[31:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=12
}
P 4100 400 4400 400 10 1 1
{
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=cpu1_addr_o[31:0]
T 4000 400 5 10 0 1 0 7 1 1
pinseq=13
}
P 4100 600 4400 600 4 0 1
{
T 4000 600 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 4100 600 5 10 0 1 0 7 1 1
pinseq=14
}
P 4100 800 4400 800 4 0 1
{
T 4000 800 5 10 1 1 0 7 1 1
pinnumber=cpu1_we_o
T 4100 800 5 10 0 1 0 7 1 1
pinseq=15
}
P 4100 1000 4400 1000 4 0 1
{
T 4000 1000 5 10 1 1 0 7 1 1
pinnumber=cpu1_stb_o
T 4100 1000 5 10 0 1 0 7 1 1
pinseq=16
}
P 4100 1200 4400 1200 4 0 1
{
T 4000 1200 5 10 1 1 0 7 1 1
pinnumber=cpu1_stall_o
T 4100 1200 5 10 0 1 0 7 1 1
pinseq=17
}
P 4100 1400 4400 1400 4 0 1
{
T 4000 1400 5 10 1 1 0 7 1 1
pinnumber=cpu1_rst_o
T 4100 1400 5 10 0 1 0 7 1 1
pinseq=18
}
/Geda/sym/adv_dbg_if_wb_cpu0_jsp.sym
1,8 → 1,8
v 20100214 1
B 300 0 4000 4700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 4850 5 10 1 1 0 0 1 1
B 300 0 4000 5300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 5450 5 10 1 1 0 0 1 1
device=adv_dbg_if_wb_cpu0_jsp
T 400 5050 8 10 1 1 0 0 1 1
T 400 5650 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
46,17 → 46,17
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
P 300 1400 0 1400 10 1 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=wb_rst_i
T 400 1400 5 10 0 1 0 1 1 1
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_we_i
pinnumber=wb_rst_i
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
63,7 → 63,7
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_stb_i
pinnumber=wb_jsp_we_i
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
70,7 → 70,7
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_cyc_i
pinnumber=wb_jsp_stb_i
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
77,7 → 77,7
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_cab_i
pinnumber=wb_jsp_cyc_i
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
84,7 → 84,7
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=wb_err_i
pinnumber=wb_jsp_cab_i
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
91,7 → 91,7
P 300 2600 0 2600 4 0 1
{
T 400 2600 5 10 1 1 0 1 1 1
pinnumber=wb_clk_i
pinnumber=wb_err_i
T 400 2600 5 10 0 1 0 1 1 1
pinseq=13
}
98,7 → 98,7
P 300 2800 0 2800 4 0 1
{
T 400 2800 5 10 1 1 0 1 1 1
pinnumber=wb_ack_i
pinnumber=wb_clk_i
T 400 2800 5 10 0 1 0 1 1 1
pinseq=14
}
105,7 → 105,7
P 300 3000 0 3000 4 0 1
{
T 400 3000 5 10 1 1 0 1 1 1
pinnumber=update_dr_i
pinnumber=wb_ack_i
T 400 3000 5 10 0 1 0 1 1 1
pinseq=15
}
112,7 → 112,7
P 300 3200 0 3200 4 0 1
{
T 400 3200 5 10 1 1 0 1 1 1
pinnumber=tdi_i
pinnumber=update_dr_i
T 400 3200 5 10 0 1 0 1 1 1
pinseq=16
}
119,7 → 119,7
P 300 3400 0 3400 4 0 1
{
T 400 3400 5 10 1 1 0 1 1 1
pinnumber=tck_i
pinnumber=tdi_i
T 400 3400 5 10 0 1 0 1 1 1
pinseq=17
}
126,7 → 126,7
P 300 3600 0 3600 4 0 1
{
T 400 3600 5 10 1 1 0 1 1 1
pinnumber=shift_dr_i
pinnumber=tck_i
T 400 3600 5 10 0 1 0 1 1 1
pinseq=18
}
133,7 → 133,7
P 300 3800 0 3800 4 0 1
{
T 400 3800 5 10 1 1 0 1 1 1
pinnumber=rst_i
pinnumber=shift_dr_i
T 400 3800 5 10 0 1 0 1 1 1
pinseq=19
}
140,7 → 140,7
P 300 4000 0 4000 4 0 1
{
T 400 4000 5 10 1 1 0 1 1 1
pinnumber=debug_select_i
pinnumber=rst_i
T 400 4000 5 10 0 1 0 1 1 1
pinseq=20
}
147,7 → 147,7
P 300 4200 0 4200 4 0 1
{
T 400 4200 5 10 1 1 0 1 1 1
pinnumber=cpu0_clk_i
pinnumber=debug_select_i
T 400 4200 5 10 0 1 0 1 1 1
pinseq=21
}
154,16 → 154,37
P 300 4400 0 4400 4 0 1
{
T 400 4400 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
pinnumber=cpu0_clk_i
T 400 4400 5 10 0 1 0 1 1 1
pinseq=22
}
P 300 4600 0 4600 4 0 1
{
T 400 4600 5 10 1 1 0 1 1 1
pinnumber=cpu0_bp_i
T 400 4600 5 10 0 1 0 1 1 1
pinseq=23
}
P 300 4800 0 4800 4 0 1
{
T 400 4800 5 10 1 1 0 1 1 1
pinnumber=cpu0_ack_i
T 400 4800 5 10 0 1 0 1 1 1
pinseq=24
}
P 300 5000 0 5000 4 0 1
{
T 400 5000 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
T 400 5000 5 10 0 1 0 1 1 1
pinseq=25
}
P 4300 200 4600 200 10 1 1
{
T 4200 200 5 10 1 1 0 7 1 1
pinnumber=wb_sel_o[3:0]
T 4200 200 5 10 0 1 0 7 1 1
pinseq=23
pinseq=26
}
P 4300 400 4600 400 10 1 1
{
170,7 → 191,7
T 4200 400 5 10 1 1 0 7 1 1
pinnumber=wb_jsp_dat_o[31:0]
T 4200 400 5 10 0 1 0 7 1 1
pinseq=24
pinseq=27
}
P 4300 600 4600 600 10 1 1
{
177,7 → 198,7
T 4200 600 5 10 1 1 0 7 1 1
pinnumber=wb_dat_o[31:0]
T 4200 600 5 10 0 1 0 7 1 1
pinseq=25
pinseq=28
}
P 4300 800 4600 800 10 1 1
{
184,7 → 205,7
T 4200 800 5 10 1 1 0 7 1 1
pinnumber=wb_cti_o[2:0]
T 4200 800 5 10 0 1 0 7 1 1
pinseq=26
pinseq=29
}
P 4300 1000 4600 1000 10 1 1
{
191,7 → 212,7
T 4200 1000 5 10 1 1 0 7 1 1
pinnumber=wb_bte_o[1:0]
T 4200 1000 5 10 0 1 0 7 1 1
pinseq=27
pinseq=30
}
P 4300 1200 4600 1200 10 1 1
{
198,7 → 219,7
T 4200 1200 5 10 1 1 0 7 1 1
pinnumber=wb_adr_o[31:0]
T 4200 1200 5 10 0 1 0 7 1 1
pinseq=28
pinseq=31
}
P 4300 1400 4600 1400 10 1 1
{
205,75 → 226,110
T 4200 1400 5 10 1 1 0 7 1 1
pinnumber=jsp_data_out[7:0]
T 4200 1400 5 10 0 1 0 7 1 1
pinseq=29
pinseq=32
}
P 4300 1600 4600 1600 4 0 1
P 4300 1600 4600 1600 10 1 1
{
T 4200 1600 5 10 1 1 0 7 1 1
pinnumber=wb_we_o
T 4300 1600 5 10 0 1 0 7 1 1
pinseq=30
T 4200 1600 5 10 1 1 0 7 1 1
pinnumber=cpu0_data_o[31:0]
T 4200 1600 5 10 0 1 0 7 1 1
pinseq=33
}
P 4300 1800 4600 1800 4 0 1
P 4300 1800 4600 1800 10 1 1
{
T 4200 1800 5 10 1 1 0 7 1 1
pinnumber=wb_stb_o
T 4300 1800 5 10 0 1 0 7 1 1
pinseq=31
T 4200 1800 5 10 1 1 0 7 1 1
pinnumber=cpu0_addr_o[31:0]
T 4200 1800 5 10 0 1 0 7 1 1
pinseq=34
}
P 4300 2000 4600 2000 4 0 1
{
T 4200 2000 5 10 1 1 0 7 1 1
pinnumber=wb_jsp_err_o
pinnumber=wb_we_o
T 4300 2000 5 10 0 1 0 7 1 1
pinseq=32
pinseq=35
}
P 4300 2200 4600 2200 4 0 1
{
T 4200 2200 5 10 1 1 0 7 1 1
pinnumber=wb_jsp_ack_o
pinnumber=wb_stb_o
T 4300 2200 5 10 0 1 0 7 1 1
pinseq=33
pinseq=36
}
P 4300 2400 4600 2400 4 0 1
{
T 4200 2400 5 10 1 1 0 7 1 1
pinnumber=wb_cyc_o
pinnumber=wb_jsp_err_o
T 4300 2400 5 10 0 1 0 7 1 1
pinseq=34
pinseq=37
}
P 4300 2600 4600 2600 4 0 1
{
T 4200 2600 5 10 1 1 0 7 1 1
pinnumber=wb_cab_o
pinnumber=wb_jsp_ack_o
T 4300 2600 5 10 0 1 0 7 1 1
pinseq=35
pinseq=38
}
P 4300 2800 4600 2800 4 0 1
{
T 4200 2800 5 10 1 1 0 7 1 1
pinnumber=tdo_o
pinnumber=wb_cyc_o
T 4300 2800 5 10 0 1 0 7 1 1
pinseq=36
pinseq=39
}
P 4300 3000 4600 3000 4 0 1
{
T 4200 3000 5 10 1 1 0 7 1 1
pinnumber=int_o
pinnumber=wb_cab_o
T 4300 3000 5 10 0 1 0 7 1 1
pinseq=37
pinseq=40
}
P 4300 3200 4600 3200 4 0 1
{
T 4200 3200 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
pinnumber=tdo_o
T 4300 3200 5 10 0 1 0 7 1 1
pinseq=38
pinseq=41
}
P 4300 3400 4600 3400 4 0 1
{
T 4200 3400 5 10 1 1 0 7 1 1
pinnumber=biu_wr_strobe
pinnumber=int_o
T 4300 3400 5 10 0 1 0 7 1 1
pinseq=39
pinseq=42
}
P 4300 3600 4600 3600 4 0 1
{
T 4200 3600 5 10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4300 3600 5 10 0 1 0 7 1 1
pinseq=43
}
P 4300 3800 4600 3800 4 0 1
{
T 4200 3800 5 10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4300 3800 5 10 0 1 0 7 1 1
pinseq=44
}
P 4300 4000 4600 4000 4 0 1
{
T 4200 4000 5 10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4300 4000 5 10 0 1 0 7 1 1
pinseq=45
}
P 4300 4200 4600 4200 4 0 1
{
T 4200 4200 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4300 4200 5 10 0 1 0 7 1 1
pinseq=46
}
P 4300 4400 4600 4400 4 0 1
{
T 4200 4400 5 10 1 1 0 7 1 1
pinnumber=biu_wr_strobe
T 4300 4400 5 10 0 1 0 7 1 1
pinseq=47
}
/Geda/sym/adv_dbg_if_wb_cpu0_jfifo.sym
1,8 → 1,8
v 20100214 1
B 300 0 3800 3300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 3450 5 10 1 1 0 0 1 1
B 300 0 3800 4100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 4250 5 10 1 1 0 0 1 1
device=adv_dbg_if_wb_cpu0_jfifo
T 400 3650 8 10 1 1 0 0 1 1
T 400 4450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
18,17 → 18,17
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=wb_rst_i
T 400 600 5 10 0 1 0 1 1 1
T 400 600 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_stb_i
pinnumber=wb_rst_i
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
35,7 → 35,7
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=wb_err_i
pinnumber=wb_jsp_stb_i
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
42,7 → 42,7
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=wb_clk_i
pinnumber=wb_err_i
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
49,7 → 49,7
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=wb_ack_i
pinnumber=wb_clk_i
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
56,7 → 56,7
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=update_dr_i
pinnumber=wb_ack_i
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
63,7 → 63,7
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=tdi_i
pinnumber=update_dr_i
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
70,7 → 70,7
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=tck_i
pinnumber=tdi_i
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
77,7 → 77,7
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=shift_dr_i
pinnumber=tck_i
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
84,7 → 84,7
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=rst_i
pinnumber=shift_dr_i
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
91,7 → 91,7
P 300 2600 0 2600 4 0 1
{
T 400 2600 5 10 1 1 0 1 1 1
pinnumber=debug_select_i
pinnumber=rst_i
T 400 2600 5 10 0 1 0 1 1 1
pinseq=13
}
98,7 → 98,7
P 300 2800 0 2800 4 0 1
{
T 400 2800 5 10 1 1 0 1 1 1
pinnumber=cpu0_clk_i
pinnumber=debug_select_i
T 400 2800 5 10 0 1 0 1 1 1
pinseq=14
}
105,16 → 105,37
P 300 3000 0 3000 4 0 1
{
T 400 3000 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
pinnumber=cpu0_clk_i
T 400 3000 5 10 0 1 0 1 1 1
pinseq=15
}
P 300 3200 0 3200 4 0 1
{
T 400 3200 5 10 1 1 0 1 1 1
pinnumber=cpu0_bp_i
T 400 3200 5 10 0 1 0 1 1 1
pinseq=16
}
P 300 3400 0 3400 4 0 1
{
T 400 3400 5 10 1 1 0 1 1 1
pinnumber=cpu0_ack_i
T 400 3400 5 10 0 1 0 1 1 1
pinseq=17
}
P 300 3600 0 3600 4 0 1
{
T 400 3600 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
T 400 3600 5 10 0 1 0 1 1 1
pinseq=18
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=wb_sel_o[3:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=16
pinseq=19
}
P 4100 400 4400 400 10 1 1
{
121,7 → 142,7
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=wb_dat_o[31:0]
T 4000 400 5 10 0 1 0 7 1 1
pinseq=17
pinseq=20
}
P 4100 600 4400 600 10 1 1
{
128,7 → 149,7
T 4000 600 5 10 1 1 0 7 1 1
pinnumber=wb_cti_o[2:0]
T 4000 600 5 10 0 1 0 7 1 1
pinseq=18
pinseq=21
}
P 4100 800 4400 800 10 1 1
{
135,7 → 156,7
T 4000 800 5 10 1 1 0 7 1 1
pinnumber=wb_bte_o[1:0]
T 4000 800 5 10 0 1 0 7 1 1
pinseq=19
pinseq=22
}
P 4100 1000 4400 1000 10 1 1
{
142,7 → 163,7
T 4000 1000 5 10 1 1 0 7 1 1
pinnumber=wb_adr_o[31:0]
T 4000 1000 5 10 0 1 0 7 1 1
pinseq=20
pinseq=23
}
P 4100 1200 4400 1200 10 1 1
{
149,61 → 170,96
T 4000 1200 5 10 1 1 0 7 1 1
pinnumber=jsp_data_out[7:0]
T 4000 1200 5 10 0 1 0 7 1 1
pinseq=21
pinseq=24
}
P 4100 1400 4400 1400 4 0 1
P 4100 1400 4400 1400 10 1 1
{
T 4000 1400 5 10 1 1 0 7 1 1
pinnumber=wb_we_o
T 4100 1400 5 10 0 1 0 7 1 1
pinseq=22
T 4000 1400 5 10 1 1 0 7 1 1
pinnumber=cpu0_data_o[31:0]
T 4000 1400 5 10 0 1 0 7 1 1
pinseq=25
}
P 4100 1600 4400 1600 4 0 1
P 4100 1600 4400 1600 10 1 1
{
T 4000 1600 5 10 1 1 0 7 1 1
pinnumber=wb_stb_o
T 4100 1600 5 10 0 1 0 7 1 1
pinseq=23
T 4000 1600 5 10 1 1 0 7 1 1
pinnumber=cpu0_addr_o[31:0]
T 4000 1600 5 10 0 1 0 7 1 1
pinseq=26
}
P 4100 1800 4400 1800 4 0 1
{
T 4000 1800 5 10 1 1 0 7 1 1
pinnumber=wb_cyc_o
pinnumber=wb_we_o
T 4100 1800 5 10 0 1 0 7 1 1
pinseq=24
pinseq=27
}
P 4100 2000 4400 2000 4 0 1
{
T 4000 2000 5 10 1 1 0 7 1 1
pinnumber=wb_cab_o
pinnumber=wb_stb_o
T 4100 2000 5 10 0 1 0 7 1 1
pinseq=25
pinseq=28
}
P 4100 2200 4400 2200 4 0 1
{
T 4000 2200 5 10 1 1 0 7 1 1
pinnumber=tdo_o
pinnumber=wb_cyc_o
T 4100 2200 5 10 0 1 0 7 1 1
pinseq=26
pinseq=29
}
P 4100 2400 4400 2400 4 0 1
{
T 4000 2400 5 10 1 1 0 7 1 1
pinnumber=int_o
pinnumber=wb_cab_o
T 4100 2400 5 10 0 1 0 7 1 1
pinseq=27
pinseq=30
}
P 4100 2600 4400 2600 4 0 1
{
T 4000 2600 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
pinnumber=tdo_o
T 4100 2600 5 10 0 1 0 7 1 1
pinseq=28
pinseq=31
}
P 4100 2800 4400 2800 4 0 1
{
T 4000 2800 5 10 1 1 0 7 1 1
pinnumber=biu_wr_strobe
pinnumber=int_o
T 4100 2800 5 10 0 1 0 7 1 1
pinseq=29
pinseq=32
}
P 4100 3000 4400 3000 4 0 1
{
T 4000 3000 5 10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4100 3000 5 10 0 1 0 7 1 1
pinseq=33
}
P 4100 3200 4400 3200 4 0 1
{
T 4000 3200 5 10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4100 3200 5 10 0 1 0 7 1 1
pinseq=34
}
P 4100 3400 4400 3400 4 0 1
{
T 4000 3400 5 10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4100 3400 5 10 0 1 0 7 1 1
pinseq=35
}
P 4100 3600 4400 3600 4 0 1
{
T 4000 3600 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4100 3600 5 10 0 1 0 7 1 1
pinseq=36
}
P 4100 3800 4400 3800 4 0 1
{
T 4000 3800 5 10 1 1 0 7 1 1
pinnumber=biu_wr_strobe
T 4100 3800 5 10 0 1 0 7 1 1
pinseq=37
}
/Geda/sym/adv_dbg_if_wb_cpu2_jsp.sym
1,8 → 1,8
v 20100214 1
B 300 0 4000 4900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 5050 5 10 1 1 0 0 1 1
B 300 0 4000 6100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 6250 5 10 1 1 0 0 1 1
device=adv_dbg_if_wb_cpu2_jsp
T 400 5250 8 10 1 1 0 0 1 1
T 400 6450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
46,24 → 46,24
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
P 300 1400 0 1400 10 1 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=wb_rst_i
T 400 1400 5 10 0 1 0 1 1 1
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cpu1_data_i[31:0]
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
P 300 1600 0 1600 10 1 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_we_i
T 400 1600 5 10 0 1 0 1 1 1
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_stb_i
pinnumber=wb_rst_i
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
70,7 → 70,7
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_cyc_i
pinnumber=wb_jsp_we_i
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
77,7 → 77,7
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_cab_i
pinnumber=wb_jsp_stb_i
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
84,7 → 84,7
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=wb_err_i
pinnumber=wb_jsp_cyc_i
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
91,7 → 91,7
P 300 2600 0 2600 4 0 1
{
T 400 2600 5 10 1 1 0 1 1 1
pinnumber=wb_clk_i
pinnumber=wb_jsp_cab_i
T 400 2600 5 10 0 1 0 1 1 1
pinseq=13
}
98,7 → 98,7
P 300 2800 0 2800 4 0 1
{
T 400 2800 5 10 1 1 0 1 1 1
pinnumber=wb_ack_i
pinnumber=wb_err_i
T 400 2800 5 10 0 1 0 1 1 1
pinseq=14
}
105,7 → 105,7
P 300 3000 0 3000 4 0 1
{
T 400 3000 5 10 1 1 0 1 1 1
pinnumber=update_dr_i
pinnumber=wb_clk_i
T 400 3000 5 10 0 1 0 1 1 1
pinseq=15
}
112,7 → 112,7
P 300 3200 0 3200 4 0 1
{
T 400 3200 5 10 1 1 0 1 1 1
pinnumber=tdi_i
pinnumber=wb_ack_i
T 400 3200 5 10 0 1 0 1 1 1
pinseq=16
}
119,7 → 119,7
P 300 3400 0 3400 4 0 1
{
T 400 3400 5 10 1 1 0 1 1 1
pinnumber=tck_i
pinnumber=update_dr_i
T 400 3400 5 10 0 1 0 1 1 1
pinseq=17
}
126,7 → 126,7
P 300 3600 0 3600 4 0 1
{
T 400 3600 5 10 1 1 0 1 1 1
pinnumber=shift_dr_i
pinnumber=tdi_i
T 400 3600 5 10 0 1 0 1 1 1
pinseq=18
}
133,7 → 133,7
P 300 3800 0 3800 4 0 1
{
T 400 3800 5 10 1 1 0 1 1 1
pinnumber=rst_i
pinnumber=tck_i
T 400 3800 5 10 0 1 0 1 1 1
pinseq=19
}
140,7 → 140,7
P 300 4000 0 4000 4 0 1
{
T 400 4000 5 10 1 1 0 1 1 1
pinnumber=debug_select_i
pinnumber=shift_dr_i
T 400 4000 5 10 0 1 0 1 1 1
pinseq=20
}
147,7 → 147,7
P 300 4200 0 4200 4 0 1
{
T 400 4200 5 10 1 1 0 1 1 1
pinnumber=cpu1_clk_i
pinnumber=rst_i
T 400 4200 5 10 0 1 0 1 1 1
pinseq=21
}
154,7 → 154,7
P 300 4400 0 4400 4 0 1
{
T 400 4400 5 10 1 1 0 1 1 1
pinnumber=cpu0_clk_i
pinnumber=debug_select_i
T 400 4400 5 10 0 1 0 1 1 1
pinseq=22
}
161,16 → 161,58
P 300 4600 0 4600 4 0 1
{
T 400 4600 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
pinnumber=cpu1_clk_i
T 400 4600 5 10 0 1 0 1 1 1
pinseq=23
}
P 300 4800 0 4800 4 0 1
{
T 400 4800 5 10 1 1 0 1 1 1
pinnumber=cpu1_bp_i
T 400 4800 5 10 0 1 0 1 1 1
pinseq=24
}
P 300 5000 0 5000 4 0 1
{
T 400 5000 5 10 1 1 0 1 1 1
pinnumber=cpu1_ack_i
T 400 5000 5 10 0 1 0 1 1 1
pinseq=25
}
P 300 5200 0 5200 4 0 1
{
T 400 5200 5 10 1 1 0 1 1 1
pinnumber=cpu0_clk_i
T 400 5200 5 10 0 1 0 1 1 1
pinseq=26
}
P 300 5400 0 5400 4 0 1
{
T 400 5400 5 10 1 1 0 1 1 1
pinnumber=cpu0_bp_i
T 400 5400 5 10 0 1 0 1 1 1
pinseq=27
}
P 300 5600 0 5600 4 0 1
{
T 400 5600 5 10 1 1 0 1 1 1
pinnumber=cpu0_ack_i
T 400 5600 5 10 0 1 0 1 1 1
pinseq=28
}
P 300 5800 0 5800 4 0 1
{
T 400 5800 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
T 400 5800 5 10 0 1 0 1 1 1
pinseq=29
}
P 4300 200 4600 200 10 1 1
{
T 4200 200 5 10 1 1 0 7 1 1
pinnumber=wb_sel_o[3:0]
T 4200 200 5 10 0 1 0 7 1 1
pinseq=24
pinseq=30
}
P 4300 400 4600 400 10 1 1
{
177,7 → 219,7
T 4200 400 5 10 1 1 0 7 1 1
pinnumber=wb_jsp_dat_o[31:0]
T 4200 400 5 10 0 1 0 7 1 1
pinseq=25
pinseq=31
}
P 4300 600 4600 600 10 1 1
{
184,7 → 226,7
T 4200 600 5 10 1 1 0 7 1 1
pinnumber=wb_dat_o[31:0]
T 4200 600 5 10 0 1 0 7 1 1
pinseq=26
pinseq=32
}
P 4300 800 4600 800 10 1 1
{
191,7 → 233,7
T 4200 800 5 10 1 1 0 7 1 1
pinnumber=wb_cti_o[2:0]
T 4200 800 5 10 0 1 0 7 1 1
pinseq=27
pinseq=33
}
P 4300 1000 4600 1000 10 1 1
{
198,7 → 240,7
T 4200 1000 5 10 1 1 0 7 1 1
pinnumber=wb_bte_o[1:0]
T 4200 1000 5 10 0 1 0 7 1 1
pinseq=28
pinseq=34
}
P 4300 1200 4600 1200 10 1 1
{
205,75 → 247,145
T 4200 1200 5 10 1 1 0 7 1 1
pinnumber=wb_adr_o[31:0]
T 4200 1200 5 10 0 1 0 7 1 1
pinseq=29
pinseq=35
}
P 4300 1400 4600 1400 4 0 1
P 4300 1400 4600 1400 10 1 1
{
T 4200 1400 5 10 1 1 0 7 1 1
pinnumber=wb_we_o
T 4300 1400 5 10 0 1 0 7 1 1
pinseq=30
T 4200 1400 5 10 1 1 0 7 1 1
pinnumber=cpu1_data_o[31:0]
T 4200 1400 5 10 0 1 0 7 1 1
pinseq=36
}
P 4300 1600 4600 1600 4 0 1
P 4300 1600 4600 1600 10 1 1
{
T 4200 1600 5 10 1 1 0 7 1 1
pinnumber=wb_stb_o
T 4300 1600 5 10 0 1 0 7 1 1
pinseq=31
T 4200 1600 5 10 1 1 0 7 1 1
pinnumber=cpu1_addr_o[31:0]
T 4200 1600 5 10 0 1 0 7 1 1
pinseq=37
}
P 4300 1800 4600 1800 4 0 1
P 4300 1800 4600 1800 10 1 1
{
T 4200 1800 5 10 1 1 0 7 1 1
pinnumber=wb_jsp_err_o
T 4300 1800 5 10 0 1 0 7 1 1
pinseq=32
T 4200 1800 5 10 1 1 0 7 1 1
pinnumber=cpu0_data_o[31:0]
T 4200 1800 5 10 0 1 0 7 1 1
pinseq=38
}
P 4300 2000 4600 2000 4 0 1
P 4300 2000 4600 2000 10 1 1
{
T 4200 2000 5 10 1 1 0 7 1 1
pinnumber=wb_jsp_ack_o
T 4300 2000 5 10 0 1 0 7 1 1
pinseq=33
T 4200 2000 5 10 1 1 0 7 1 1
pinnumber=cpu0_addr_o[31:0]
T 4200 2000 5 10 0 1 0 7 1 1
pinseq=39
}
P 4300 2200 4600 2200 4 0 1
{
T 4200 2200 5 10 1 1 0 7 1 1
pinnumber=wb_cyc_o
pinnumber=wb_we_o
T 4300 2200 5 10 0 1 0 7 1 1
pinseq=34
pinseq=40
}
P 4300 2400 4600 2400 4 0 1
{
T 4200 2400 5 10 1 1 0 7 1 1
pinnumber=wb_cab_o
pinnumber=wb_stb_o
T 4300 2400 5 10 0 1 0 7 1 1
pinseq=35
pinseq=41
}
P 4300 2600 4600 2600 4 0 1
{
T 4200 2600 5 10 1 1 0 7 1 1
pinnumber=tdo_o
pinnumber=wb_jsp_err_o
T 4300 2600 5 10 0 1 0 7 1 1
pinseq=36
pinseq=42
}
P 4300 2800 4600 2800 4 0 1
{
T 4200 2800 5 10 1 1 0 7 1 1
pinnumber=int_o
pinnumber=wb_jsp_ack_o
T 4300 2800 5 10 0 1 0 7 1 1
pinseq=37
pinseq=43
}
P 4300 3000 4600 3000 4 0 1
{
T 4200 3000 5 10 1 1 0 7 1 1
pinnumber=cpu1_rst_o
pinnumber=wb_cyc_o
T 4300 3000 5 10 0 1 0 7 1 1
pinseq=38
pinseq=44
}
P 4300 3200 4600 3200 4 0 1
{
T 4200 3200 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
pinnumber=wb_cab_o
T 4300 3200 5 10 0 1 0 7 1 1
pinseq=39
pinseq=45
}
P 4300 3400 4600 3400 4 0 1
{
T 4200 3400 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 4300 3400 5 10 0 1 0 7 1 1
pinseq=46
}
P 4300 3600 4600 3600 4 0 1
{
T 4200 3600 5 10 1 1 0 7 1 1
pinnumber=int_o
T 4300 3600 5 10 0 1 0 7 1 1
pinseq=47
}
P 4300 3800 4600 3800 4 0 1
{
T 4200 3800 5 10 1 1 0 7 1 1
pinnumber=cpu1_we_o
T 4300 3800 5 10 0 1 0 7 1 1
pinseq=48
}
P 4300 4000 4600 4000 4 0 1
{
T 4200 4000 5 10 1 1 0 7 1 1
pinnumber=cpu1_stb_o
T 4300 4000 5 10 0 1 0 7 1 1
pinseq=49
}
P 4300 4200 4600 4200 4 0 1
{
T 4200 4200 5 10 1 1 0 7 1 1
pinnumber=cpu1_stall_o
T 4300 4200 5 10 0 1 0 7 1 1
pinseq=50
}
P 4300 4400 4600 4400 4 0 1
{
T 4200 4400 5 10 1 1 0 7 1 1
pinnumber=cpu1_rst_o
T 4300 4400 5 10 0 1 0 7 1 1
pinseq=51
}
P 4300 4600 4600 4600 4 0 1
{
T 4200 4600 5 10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4300 4600 5 10 0 1 0 7 1 1
pinseq=52
}
P 4300 4800 4600 4800 4 0 1
{
T 4200 4800 5 10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4300 4800 5 10 0 1 0 7 1 1
pinseq=53
}
P 4300 5000 4600 5000 4 0 1
{
T 4200 5000 5 10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4300 5000 5 10 0 1 0 7 1 1
pinseq=54
}
P 4300 5200 4600 5200 4 0 1
{
T 4200 5200 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4300 5200 5 10 0 1 0 7 1 1
pinseq=55
}
/Geda/sym/adv_dbg_if_wb_cpu0.sym
1,8 → 1,8
v 20100214 1
B 300 0 3200 2900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 3050 5 10 1 1 0 0 1 1
B 300 0 3800 3500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 3650 5 10 1 1 0 0 1 1
device=adv_dbg_if_wb_cpu0
T 400 3250 8 10 1 1 0 0 1 1
T 400 3850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
11,17 → 11,17
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=wb_rst_i
T 400 400 5 10 0 1 0 1 1 1
T 400 400 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=wb_err_i
pinnumber=wb_rst_i
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
28,7 → 28,7
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wb_clk_i
pinnumber=wb_err_i
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
35,7 → 35,7
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=wb_ack_i
pinnumber=wb_clk_i
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
42,7 → 42,7
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=update_dr_i
pinnumber=wb_ack_i
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
49,7 → 49,7
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=tdi_i
pinnumber=update_dr_i
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
56,7 → 56,7
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=tck_i
pinnumber=tdi_i
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
63,7 → 63,7
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=shift_dr_i
pinnumber=tck_i
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
70,7 → 70,7
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=rst_i
pinnumber=shift_dr_i
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
77,7 → 77,7
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=debug_select_i
pinnumber=rst_i
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
84,7 → 84,7
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=cpu0_clk_i
pinnumber=debug_select_i
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
91,84 → 91,140
P 300 2600 0 2600 4 0 1
{
T 400 2600 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
pinnumber=cpu0_clk_i
T 400 2600 5 10 0 1 0 1 1 1
pinseq=13
}
P 3500 200 3800 200 10 1 1
P 300 2800 0 2800 4 0 1
{
T 3400 200 5 10 1 1 0 7 1 1
pinnumber=wb_sel_o[3:0]
T 3400 200 5 10 0 1 0 7 1 1
T 400 2800 5 10 1 1 0 1 1 1
pinnumber=cpu0_bp_i
T 400 2800 5 10 0 1 0 1 1 1
pinseq=14
}
P 3500 400 3800 400 10 1 1
P 300 3000 0 3000 4 0 1
{
T 3400 400 5 10 1 1 0 7 1 1
pinnumber=wb_dat_o[31:0]
T 3400 400 5 10 0 1 0 7 1 1
T 400 3000 5 10 1 1 0 1 1 1
pinnumber=cpu0_ack_i
T 400 3000 5 10 0 1 0 1 1 1
pinseq=15
}
P 3500 600 3800 600 10 1 1
P 300 3200 0 3200 4 0 1
{
T 3400 600 5 10 1 1 0 7 1 1
pinnumber=wb_cti_o[2:0]
T 3400 600 5 10 0 1 0 7 1 1
T 400 3200 5 10 1 1 0 1 1 1
pinnumber=capture_dr_i
T 400 3200 5 10 0 1 0 1 1 1
pinseq=16
}
P 3500 800 3800 800 10 1 1
P 4100 200 4400 200 10 1 1
{
T 3400 800 5 10 1 1 0 7 1 1
pinnumber=wb_bte_o[1:0]
T 3400 800 5 10 0 1 0 7 1 1
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=wb_sel_o[3:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=17
}
P 3500 1000 3800 1000 10 1 1
P 4100 400 4400 400 10 1 1
{
T 3400 1000 5 10 1 1 0 7 1 1
pinnumber=wb_adr_o[31:0]
T 3400 1000 5 10 0 1 0 7 1 1
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=wb_dat_o[31:0]
T 4000 400 5 10 0 1 0 7 1 1
pinseq=18
}
P 3500 1200 3800 1200 4 0 1
P 4100 600 4400 600 10 1 1
{
T 3400 1200 5 10 1 1 0 7 1 1
pinnumber=wb_we_o
T 3500 1200 5 10 0 1 0 7 1 1
T 4000 600 5 10 1 1 0 7 1 1
pinnumber=wb_cti_o[2:0]
T 4000 600 5 10 0 1 0 7 1 1
pinseq=19
}
P 3500 1400 3800 1400 4 0 1
P 4100 800 4400 800 10 1 1
{
T 3400 1400 5 10 1 1 0 7 1 1
pinnumber=wb_stb_o
T 3500 1400 5 10 0 1 0 7 1 1
T 4000 800 5 10 1 1 0 7 1 1
pinnumber=wb_bte_o[1:0]
T 4000 800 5 10 0 1 0 7 1 1
pinseq=20
}
P 3500 1600 3800 1600 4 0 1
P 4100 1000 4400 1000 10 1 1
{
T 3400 1600 5 10 1 1 0 7 1 1
pinnumber=wb_cyc_o
T 3500 1600 5 10 0 1 0 7 1 1
T 4000 1000 5 10 1 1 0 7 1 1
pinnumber=wb_adr_o[31:0]
T 4000 1000 5 10 0 1 0 7 1 1
pinseq=21
}
P 3500 1800 3800 1800 4 0 1
P 4100 1200 4400 1200 10 1 1
{
T 3400 1800 5 10 1 1 0 7 1 1
pinnumber=wb_cab_o
T 3500 1800 5 10 0 1 0 7 1 1
T 4000 1200 5 10 1 1 0 7 1 1
pinnumber=cpu0_data_o[31:0]
T 4000 1200 5 10 0 1 0 7 1 1
pinseq=22
}
P 3500 2000 3800 2000 4 0 1
P 4100 1400 4400 1400 10 1 1
{
T 3400 2000 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 3500 2000 5 10 0 1 0 7 1 1
T 4000 1400 5 10 1 1 0 7 1 1
pinnumber=cpu0_addr_o[31:0]
T 4000 1400 5 10 0 1 0 7 1 1
pinseq=23
}
P 3500 2200 3800 2200 4 0 1
P 4100 1600 4400 1600 4 0 1
{
T 3400 2200 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 3500 2200 5 10 0 1 0 7 1 1
T 4000 1600 5 10 1 1 0 7 1 1
pinnumber=wb_we_o
T 4100 1600 5 10 0 1 0 7 1 1
pinseq=24
}
P 4100 1800 4400 1800 4 0 1
{
T 4000 1800 5 10 1 1 0 7 1 1
pinnumber=wb_stb_o
T 4100 1800 5 10 0 1 0 7 1 1
pinseq=25
}
P 4100 2000 4400 2000 4 0 1
{
T 4000 2000 5 10 1 1 0 7 1 1
pinnumber=wb_cyc_o
T 4100 2000 5 10 0 1 0 7 1 1
pinseq=26
}
P 4100 2200 4400 2200 4 0 1
{
T 4000 2200 5 10 1 1 0 7 1 1
pinnumber=wb_cab_o
T 4100 2200 5 10 0 1 0 7 1 1
pinseq=27
}
P 4100 2400 4400 2400 4 0 1
{
T 4000 2400 5 10 1 1 0 7 1 1
pinnumber=tdo_o
T 4100 2400 5 10 0 1 0 7 1 1
pinseq=28
}
P 4100 2600 4400 2600 4 0 1
{
T 4000 2600 5 10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4100 2600 5 10 0 1 0 7 1 1
pinseq=29
}
P 4100 2800 4400 2800 4 0 1
{
T 4000 2800 5 10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4100 2800 5 10 0 1 0 7 1 1
pinseq=30
}
P 4100 3000 4400 3000 4 0 1
{
T 4000 3000 5 10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4100 3000 5 10 0 1 0 7 1 1
pinseq=31
}
P 4100 3200 4400 3200 4 0 1
{
T 4000 3200 5 10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4100 3200 5 10 0 1 0 7 1 1
pinseq=32
}
/Geda/sch/adv_dbg_if_wb_cpu0.sch
1,121 → 1,161
v 20100214 1
C 1600 300 1 0 0 in_port_v.sym
C 1900 300 1 0 0 in_port_v.sym
{
T 1600 300 5 10 1 1 0 6 1 1
T 1900 300 5 10 1 1 0 6 1 1
refdes=wb_dat_i[31:0]
}
C 1600 700 1 0 0 in_port.sym
C 1900 700 1 0 0 in_port_v.sym
{
T 1600 700 5 10 1 1 0 6 1 1
T 1900 700 5 10 1 1 0 6 1 1
refdes=cpu0_data_i[31:0]
}
C 1900 1100 1 0 0 in_port.sym
{
T 1900 1100 5 10 1 1 0 6 1 1
refdes=wb_rst_i
}
C 1600 1100 1 0 0 in_port.sym
C 1900 1500 1 0 0 in_port.sym
{
T 1600 1100 5 10 1 1 0 6 1 1
T 1900 1500 5 10 1 1 0 6 1 1
refdes=wb_err_i
}
C 1600 1500 1 0 0 in_port.sym
C 1900 1900 1 0 0 in_port.sym
{
T 1600 1500 5 10 1 1 0 6 1 1
T 1900 1900 5 10 1 1 0 6 1 1
refdes=wb_clk_i
}
C 1600 1900 1 0 0 in_port.sym
C 1900 2300 1 0 0 in_port.sym
{
T 1600 1900 5 10 1 1 0 6 1 1
T 1900 2300 5 10 1 1 0 6 1 1
refdes=wb_ack_i
}
C 1600 2300 1 0 0 in_port.sym
C 1900 2700 1 0 0 in_port.sym
{
T 1600 2300 5 10 1 1 0 6 1 1
T 1900 2700 5 10 1 1 0 6 1 1
refdes=update_dr_i
}
C 1600 2700 1 0 0 in_port.sym
C 1900 3100 1 0 0 in_port.sym
{
T 1600 2700 5 10 1 1 0 6 1 1
T 1900 3100 5 10 1 1 0 6 1 1
refdes=tdi_i
}
C 1600 3100 1 0 0 in_port.sym
C 1900 3500 1 0 0 in_port.sym
{
T 1600 3100 5 10 1 1 0 6 1 1
T 1900 3500 5 10 1 1 0 6 1 1
refdes=tck_i
}
C 1600 3500 1 0 0 in_port.sym
C 1900 3900 1 0 0 in_port.sym
{
T 1600 3500 5 10 1 1 0 6 1 1
T 1900 3900 5 10 1 1 0 6 1 1
refdes=shift_dr_i
}
C 1600 3900 1 0 0 in_port.sym
C 1900 4300 1 0 0 in_port.sym
{
T 1600 3900 5 10 1 1 0 6 1 1
T 1900 4300 5 10 1 1 0 6 1 1
refdes=rst_i
}
C 1600 4300 1 0 0 in_port.sym
C 1900 4700 1 0 0 in_port.sym
{
T 1600 4300 5 10 1 1 0 6 1 1
T 1900 4700 5 10 1 1 0 6 1 1
refdes=debug_select_i
}
C 1600 4700 1 0 0 in_port.sym
C 1900 5100 1 0 0 in_port.sym
{
T 1600 4700 5 10 1 1 0 6 1 1
T 1900 5100 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
}
C 1600 5100 1 0 0 in_port.sym
C 1900 5500 1 0 0 in_port.sym
{
T 1600 5100 5 10 1 1 0 6 1 1
T 1900 5500 5 10 1 1 0 6 1 1
refdes=cpu0_bp_i
}
C 1900 5900 1 0 0 in_port.sym
{
T 1900 5900 5 10 1 1 0 6 1 1
refdes=cpu0_ack_i
}
C 1900 6300 1 0 0 in_port.sym
{
T 1900 6300 5 10 1 1 0 6 1 1
refdes=capture_dr_i
}
C 4300 300 1 0 0 out_port_v.sym
C 4900 300 1 0 0 out_port_v.sym
{
T 5300 300 5 10 1 1 0 0 1 1
T 5900 300 5 10 1 1 0 0 1 1
refdes=wb_sel_o[3:0]
}
C 4300 700 1 0 0 out_port_v.sym
C 4900 700 1 0 0 out_port_v.sym
{
T 5300 700 5 10 1 1 0 0 1 1
T 5900 700 5 10 1 1 0 0 1 1
refdes=wb_dat_o[31:0]
}
C 4300 1100 1 0 0 out_port_v.sym
C 4900 1100 1 0 0 out_port_v.sym
{
T 5300 1100 5 10 1 1 0 0 1 1
T 5900 1100 5 10 1 1 0 0 1 1
refdes=wb_cti_o[2:0]
}
C 4300 1500 1 0 0 out_port_v.sym
C 4900 1500 1 0 0 out_port_v.sym
{
T 5300 1500 5 10 1 1 0 0 1 1
T 5900 1500 5 10 1 1 0 0 1 1
refdes=wb_bte_o[1:0]
}
C 4300 1900 1 0 0 out_port_v.sym
C 4900 1900 1 0 0 out_port_v.sym
{
T 5300 1900 5 10 1 1 0 0 1 1
T 5900 1900 5 10 1 1 0 0 1 1
refdes=wb_adr_o[31:0]
}
C 4300 2300 1 0 0 out_port.sym
C 4900 2300 1 0 0 out_port_v.sym
{
T 5300 2300 5 10 1 1 0 0 1 1
T 5900 2300 5 10 1 1 0 0 1 1
refdes=cpu0_data_o[31:0]
}
C 4900 2700 1 0 0 out_port_v.sym
{
T 5900 2700 5 10 1 1 0 0 1 1
refdes=cpu0_addr_o[31:0]
}
C 4900 3100 1 0 0 out_port.sym
{
T 5900 3100 5 10 1 1 0 0 1 1
refdes=wb_we_o
}
C 4300 2700 1 0 0 out_port.sym
C 4900 3500 1 0 0 out_port.sym
{
T 5300 2700 5 10 1 1 0 0 1 1
T 5900 3500 5 10 1 1 0 0 1 1
refdes=wb_stb_o
}
C 4300 3100 1 0 0 out_port.sym
C 4900 3900 1 0 0 out_port.sym
{
T 5300 3100 5 10 1 1 0 0 1 1
T 5900 3900 5 10 1 1 0 0 1 1
refdes=wb_cyc_o
}
C 4300 3500 1 0 0 out_port.sym
C 4900 4300 1 0 0 out_port.sym
{
T 5300 3500 5 10 1 1 0 0 1 1
T 5900 4300 5 10 1 1 0 0 1 1
refdes=wb_cab_o
}
C 4300 3900 1 0 0 out_port.sym
C 4900 4700 1 0 0 out_port.sym
{
T 5300 3900 5 10 1 1 0 0 1 1
T 5900 4700 5 10 1 1 0 0 1 1
refdes=tdo_o
}
C 4300 4300 1 0 0 out_port.sym
C 4900 5100 1 0 0 out_port.sym
{
T 5300 4300 5 10 1 1 0 0 1 1
T 5900 5100 5 10 1 1 0 0 1 1
refdes=cpu0_we_o
}
C 4900 5500 1 0 0 out_port.sym
{
T 5900 5500 5 10 1 1 0 0 1 1
refdes=cpu0_stb_o
}
C 4900 5900 1 0 0 out_port.sym
{
T 5900 5900 5 10 1 1 0 0 1 1
refdes=cpu0_stall_o
}
C 4900 6300 1 0 0 out_port.sym
{
T 5900 6300 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
}
/Geda/sch/adv_dbg_if_cpu0.sch
1,51 → 1,91
v 20100214 1
C 1600 300 1 0 0 in_port.sym
C 1900 300 1 0 0 in_port_v.sym
{
T 1600 300 5 10 1 1 0 6 1 1
T 1900 300 5 10 1 1 0 6 1 1
refdes=cpu0_data_i[31:0]
}
C 1900 700 1 0 0 in_port.sym
{
T 1900 700 5 10 1 1 0 6 1 1
refdes=update_dr_i
}
C 1600 700 1 0 0 in_port.sym
C 1900 1100 1 0 0 in_port.sym
{
T 1600 700 5 10 1 1 0 6 1 1
T 1900 1100 5 10 1 1 0 6 1 1
refdes=tdi_i
}
C 1600 1100 1 0 0 in_port.sym
C 1900 1500 1 0 0 in_port.sym
{
T 1600 1100 5 10 1 1 0 6 1 1
T 1900 1500 5 10 1 1 0 6 1 1
refdes=tck_i
}
C 1600 1500 1 0 0 in_port.sym
C 1900 1900 1 0 0 in_port.sym
{
T 1600 1500 5 10 1 1 0 6 1 1
T 1900 1900 5 10 1 1 0 6 1 1
refdes=shift_dr_i
}
C 1600 1900 1 0 0 in_port.sym
C 1900 2300 1 0 0 in_port.sym
{
T 1600 1900 5 10 1 1 0 6 1 1
T 1900 2300 5 10 1 1 0 6 1 1
refdes=rst_i
}
C 1600 2300 1 0 0 in_port.sym
C 1900 2700 1 0 0 in_port.sym
{
T 1600 2300 5 10 1 1 0 6 1 1
T 1900 2700 5 10 1 1 0 6 1 1
refdes=debug_select_i
}
C 1600 2700 1 0 0 in_port.sym
C 1900 3100 1 0 0 in_port.sym
{
T 1600 2700 5 10 1 1 0 6 1 1
T 1900 3100 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
}
C 1600 3100 1 0 0 in_port.sym
C 1900 3500 1 0 0 in_port.sym
{
T 1600 3100 5 10 1 1 0 6 1 1
T 1900 3500 5 10 1 1 0 6 1 1
refdes=cpu0_bp_i
}
C 1900 3900 1 0 0 in_port.sym
{
T 1900 3900 5 10 1 1 0 6 1 1
refdes=cpu0_ack_i
}
C 1900 4300 1 0 0 in_port.sym
{
T 1900 4300 5 10 1 1 0 6 1 1
refdes=capture_dr_i
}
C 3900 300 1 0 0 out_port.sym
C 4900 300 1 0 0 out_port_v.sym
{
T 4900 300 5 10 1 1 0 0 1 1
T 5900 300 5 10 1 1 0 0 1 1
refdes=cpu0_data_o[31:0]
}
C 4900 700 1 0 0 out_port_v.sym
{
T 5900 700 5 10 1 1 0 0 1 1
refdes=cpu0_addr_o[31:0]
}
C 4900 1100 1 0 0 out_port.sym
{
T 5900 1100 5 10 1 1 0 0 1 1
refdes=tdo_o
}
C 3900 700 1 0 0 out_port.sym
C 4900 1500 1 0 0 out_port.sym
{
T 4900 700 5 10 1 1 0 0 1 1
T 5900 1500 5 10 1 1 0 0 1 1
refdes=cpu0_we_o
}
C 4900 1900 1 0 0 out_port.sym
{
T 5900 1900 5 10 1 1 0 0 1 1
refdes=cpu0_stb_o
}
C 4900 2300 1 0 0 out_port.sym
{
T 5900 2300 5 10 1 1 0 0 1 1
refdes=cpu0_stall_o
}
C 4900 2700 1 0 0 out_port.sym
{
T 5900 2700 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
}
/Geda/sch/adv_dbg_if_cpu1.sch
1,51 → 1,91
v 20100214 1
C 1600 300 1 0 0 in_port.sym
C 1900 300 1 0 0 in_port_v.sym
{
T 1600 300 5 10 1 1 0 6 1 1
T 1900 300 5 10 1 1 0 6 1 1
refdes=cpu1_data_i[31:0]
}
C 1900 700 1 0 0 in_port.sym
{
T 1900 700 5 10 1 1 0 6 1 1
refdes=update_dr_i
}
C 1600 700 1 0 0 in_port.sym
C 1900 1100 1 0 0 in_port.sym
{
T 1600 700 5 10 1 1 0 6 1 1
T 1900 1100 5 10 1 1 0 6 1 1
refdes=tdi_i
}
C 1600 1100 1 0 0 in_port.sym
C 1900 1500 1 0 0 in_port.sym
{
T 1600 1100 5 10 1 1 0 6 1 1
T 1900 1500 5 10 1 1 0 6 1 1
refdes=tck_i
}
C 1600 1500 1 0 0 in_port.sym
C 1900 1900 1 0 0 in_port.sym
{
T 1600 1500 5 10 1 1 0 6 1 1
T 1900 1900 5 10 1 1 0 6 1 1
refdes=shift_dr_i
}
C 1600 1900 1 0 0 in_port.sym
C 1900 2300 1 0 0 in_port.sym
{
T 1600 1900 5 10 1 1 0 6 1 1
T 1900 2300 5 10 1 1 0 6 1 1
refdes=rst_i
}
C 1600 2300 1 0 0 in_port.sym
C 1900 2700 1 0 0 in_port.sym
{
T 1600 2300 5 10 1 1 0 6 1 1
T 1900 2700 5 10 1 1 0 6 1 1
refdes=debug_select_i
}
C 1600 2700 1 0 0 in_port.sym
C 1900 3100 1 0 0 in_port.sym
{
T 1600 2700 5 10 1 1 0 6 1 1
T 1900 3100 5 10 1 1 0 6 1 1
refdes=cpu1_clk_i
}
C 1600 3100 1 0 0 in_port.sym
C 1900 3500 1 0 0 in_port.sym
{
T 1600 3100 5 10 1 1 0 6 1 1
T 1900 3500 5 10 1 1 0 6 1 1
refdes=cpu1_bp_i
}
C 1900 3900 1 0 0 in_port.sym
{
T 1900 3900 5 10 1 1 0 6 1 1
refdes=cpu1_ack_i
}
C 1900 4300 1 0 0 in_port.sym
{
T 1900 4300 5 10 1 1 0 6 1 1
refdes=capture_dr_i
}
C 3900 300 1 0 0 out_port.sym
C 4900 300 1 0 0 out_port_v.sym
{
T 4900 300 5 10 1 1 0 0 1 1
T 5900 300 5 10 1 1 0 0 1 1
refdes=cpu1_data_o[31:0]
}
C 4900 700 1 0 0 out_port_v.sym
{
T 5900 700 5 10 1 1 0 0 1 1
refdes=cpu1_addr_o[31:0]
}
C 4900 1100 1 0 0 out_port.sym
{
T 5900 1100 5 10 1 1 0 0 1 1
refdes=tdo_o
}
C 3900 700 1 0 0 out_port.sym
C 4900 1500 1 0 0 out_port.sym
{
T 4900 700 5 10 1 1 0 0 1 1
T 5900 1500 5 10 1 1 0 0 1 1
refdes=cpu1_we_o
}
C 4900 1900 1 0 0 out_port.sym
{
T 5900 1900 5 10 1 1 0 0 1 1
refdes=cpu1_stb_o
}
C 4900 2300 1 0 0 out_port.sym
{
T 5900 2300 5 10 1 1 0 0 1 1
refdes=cpu1_stall_o
}
C 4900 2700 1 0 0 out_port.sym
{
T 5900 2700 5 10 1 1 0 0 1 1
refdes=cpu1_rst_o
}
/Geda/sch/adv_dbg_if_wb_cpu0_jsp.sch
29,84 → 29,99
T 2000 2300 5 10 1 1 0 6 1 1
refdes=wb_dat_i[31:0]
}
C 2000 2700 1 0 0 in_port.sym
C 2000 2700 1 0 0 in_port_v.sym
{
T 2000 2700 5 10 1 1 0 6 1 1
refdes=wb_rst_i
T 2000 2700 5 10 1 1 0 6 1 1
refdes=cpu0_data_i[31:0]
}
C 2000 3100 1 0 0 in_port.sym
{
T 2000 3100 5 10 1 1 0 6 1 1
refdes=wb_jsp_we_i
refdes=wb_rst_i
}
C 2000 3500 1 0 0 in_port.sym
{
T 2000 3500 5 10 1 1 0 6 1 1
refdes=wb_jsp_stb_i
refdes=wb_jsp_we_i
}
C 2000 3900 1 0 0 in_port.sym
{
T 2000 3900 5 10 1 1 0 6 1 1
refdes=wb_jsp_cyc_i
refdes=wb_jsp_stb_i
}
C 2000 4300 1 0 0 in_port.sym
{
T 2000 4300 5 10 1 1 0 6 1 1
refdes=wb_jsp_cab_i
refdes=wb_jsp_cyc_i
}
C 2000 4700 1 0 0 in_port.sym
{
T 2000 4700 5 10 1 1 0 6 1 1
refdes=wb_err_i
refdes=wb_jsp_cab_i
}
C 2000 5100 1 0 0 in_port.sym
{
T 2000 5100 5 10 1 1 0 6 1 1
refdes=wb_clk_i
refdes=wb_err_i
}
C 2000 5500 1 0 0 in_port.sym
{
T 2000 5500 5 10 1 1 0 6 1 1
refdes=wb_ack_i
refdes=wb_clk_i
}
C 2000 5900 1 0 0 in_port.sym
{
T 2000 5900 5 10 1 1 0 6 1 1
refdes=update_dr_i
refdes=wb_ack_i
}
C 2000 6300 1 0 0 in_port.sym
{
T 2000 6300 5 10 1 1 0 6 1 1
refdes=tdi_i
refdes=update_dr_i
}
C 2000 6700 1 0 0 in_port.sym
{
T 2000 6700 5 10 1 1 0 6 1 1
refdes=tck_i
refdes=tdi_i
}
C 2000 7100 1 0 0 in_port.sym
{
T 2000 7100 5 10 1 1 0 6 1 1
refdes=shift_dr_i
refdes=tck_i
}
C 2000 7500 1 0 0 in_port.sym
{
T 2000 7500 5 10 1 1 0 6 1 1
refdes=rst_i
refdes=shift_dr_i
}
C 2000 7900 1 0 0 in_port.sym
{
T 2000 7900 5 10 1 1 0 6 1 1
refdes=debug_select_i
refdes=rst_i
}
C 2000 8300 1 0 0 in_port.sym
{
T 2000 8300 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
refdes=debug_select_i
}
C 2000 8700 1 0 0 in_port.sym
{
T 2000 8700 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
}
C 2000 9100 1 0 0 in_port.sym
{
T 2000 9100 5 10 1 1 0 6 1 1
refdes=cpu0_bp_i
}
C 2000 9500 1 0 0 in_port.sym
{
T 2000 9500 5 10 1 1 0 6 1 1
refdes=cpu0_ack_i
}
C 2000 9900 1 0 0 in_port.sym
{
T 2000 9900 5 10 1 1 0 6 1 1
refdes=capture_dr_i
}
C 5100 300 1 0 0 out_port_v.sym
144,53 → 159,78
T 6100 2700 5 10 1 1 0 0 1 1
refdes=jsp_data_out[7:0]
}
C 5100 3100 1 0 0 out_port.sym
C 5100 3100 1 0 0 out_port_v.sym
{
T 6100 3100 5 10 1 1 0 0 1 1
refdes=wb_we_o
T 6100 3100 5 10 1 1 0 0 1 1
refdes=cpu0_data_o[31:0]
}
C 5100 3500 1 0 0 out_port.sym
C 5100 3500 1 0 0 out_port_v.sym
{
T 6100 3500 5 10 1 1 0 0 1 1
refdes=wb_stb_o
T 6100 3500 5 10 1 1 0 0 1 1
refdes=cpu0_addr_o[31:0]
}
C 5100 3900 1 0 0 out_port.sym
{
T 6100 3900 5 10 1 1 0 0 1 1
refdes=wb_jsp_err_o
refdes=wb_we_o
}
C 5100 4300 1 0 0 out_port.sym
{
T 6100 4300 5 10 1 1 0 0 1 1
refdes=wb_jsp_ack_o
refdes=wb_stb_o
}
C 5100 4700 1 0 0 out_port.sym
{
T 6100 4700 5 10 1 1 0 0 1 1
refdes=wb_cyc_o
refdes=wb_jsp_err_o
}
C 5100 5100 1 0 0 out_port.sym
{
T 6100 5100 5 10 1 1 0 0 1 1
refdes=wb_cab_o
refdes=wb_jsp_ack_o
}
C 5100 5500 1 0 0 out_port.sym
{
T 6100 5500 5 10 1 1 0 0 1 1
refdes=tdo_o
refdes=wb_cyc_o
}
C 5100 5900 1 0 0 out_port.sym
{
T 6100 5900 5 10 1 1 0 0 1 1
refdes=int_o
refdes=wb_cab_o
}
C 5100 6300 1 0 0 out_port.sym
{
T 6100 6300 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
refdes=tdo_o
}
C 5100 6700 1 0 0 out_port.sym
{
T 6100 6700 5 10 1 1 0 0 1 1
refdes=int_o
}
C 5100 7100 1 0 0 out_port.sym
{
T 6100 7100 5 10 1 1 0 0 1 1
refdes=cpu0_we_o
}
C 5100 7500 1 0 0 out_port.sym
{
T 6100 7500 5 10 1 1 0 0 1 1
refdes=cpu0_stb_o
}
C 5100 7900 1 0 0 out_port.sym
{
T 6100 7900 5 10 1 1 0 0 1 1
refdes=cpu0_stall_o
}
C 5100 8300 1 0 0 out_port.sym
{
T 6100 8300 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
}
C 5100 8700 1 0 0 out_port.sym
{
T 6100 8700 5 10 1 1 0 0 1 1
refdes=biu_wr_strobe
}
/Geda/sch/adv_dbg_if_wb_cpu0_jfifo.sch
9,69 → 9,84
T 1900 700 5 10 1 1 0 6 1 1
refdes=wb_dat_i[31:0]
}
C 1900 1100 1 0 0 in_port.sym
C 1900 1100 1 0 0 in_port_v.sym
{
T 1900 1100 5 10 1 1 0 6 1 1
refdes=wb_rst_i
T 1900 1100 5 10 1 1 0 6 1 1
refdes=cpu0_data_i[31:0]
}
C 1900 1500 1 0 0 in_port.sym
{
T 1900 1500 5 10 1 1 0 6 1 1
refdes=wb_jsp_stb_i
refdes=wb_rst_i
}
C 1900 1900 1 0 0 in_port.sym
{
T 1900 1900 5 10 1 1 0 6 1 1
refdes=wb_err_i
refdes=wb_jsp_stb_i
}
C 1900 2300 1 0 0 in_port.sym
{
T 1900 2300 5 10 1 1 0 6 1 1
refdes=wb_clk_i
refdes=wb_err_i
}
C 1900 2700 1 0 0 in_port.sym
{
T 1900 2700 5 10 1 1 0 6 1 1
refdes=wb_ack_i
refdes=wb_clk_i
}
C 1900 3100 1 0 0 in_port.sym
{
T 1900 3100 5 10 1 1 0 6 1 1
refdes=update_dr_i
refdes=wb_ack_i
}
C 1900 3500 1 0 0 in_port.sym
{
T 1900 3500 5 10 1 1 0 6 1 1
refdes=tdi_i
refdes=update_dr_i
}
C 1900 3900 1 0 0 in_port.sym
{
T 1900 3900 5 10 1 1 0 6 1 1
refdes=tck_i
refdes=tdi_i
}
C 1900 4300 1 0 0 in_port.sym
{
T 1900 4300 5 10 1 1 0 6 1 1
refdes=shift_dr_i
refdes=tck_i
}
C 1900 4700 1 0 0 in_port.sym
{
T 1900 4700 5 10 1 1 0 6 1 1
refdes=rst_i
refdes=shift_dr_i
}
C 1900 5100 1 0 0 in_port.sym
{
T 1900 5100 5 10 1 1 0 6 1 1
refdes=debug_select_i
refdes=rst_i
}
C 1900 5500 1 0 0 in_port.sym
{
T 1900 5500 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
refdes=debug_select_i
}
C 1900 5900 1 0 0 in_port.sym
{
T 1900 5900 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
}
C 1900 6300 1 0 0 in_port.sym
{
T 1900 6300 5 10 1 1 0 6 1 1
refdes=cpu0_bp_i
}
C 1900 6700 1 0 0 in_port.sym
{
T 1900 6700 5 10 1 1 0 6 1 1
refdes=cpu0_ack_i
}
C 1900 7100 1 0 0 in_port.sym
{
T 1900 7100 5 10 1 1 0 6 1 1
refdes=capture_dr_i
}
C 4900 300 1 0 0 out_port_v.sym
104,43 → 119,68
T 5900 2300 5 10 1 1 0 0 1 1
refdes=jsp_data_out[7:0]
}
C 4900 2700 1 0 0 out_port.sym
C 4900 2700 1 0 0 out_port_v.sym
{
T 5900 2700 5 10 1 1 0 0 1 1
refdes=wb_we_o
T 5900 2700 5 10 1 1 0 0 1 1
refdes=cpu0_data_o[31:0]
}
C 4900 3100 1 0 0 out_port.sym
C 4900 3100 1 0 0 out_port_v.sym
{
T 5900 3100 5 10 1 1 0 0 1 1
refdes=wb_stb_o
T 5900 3100 5 10 1 1 0 0 1 1
refdes=cpu0_addr_o[31:0]
}
C 4900 3500 1 0 0 out_port.sym
{
T 5900 3500 5 10 1 1 0 0 1 1
refdes=wb_cyc_o
refdes=wb_we_o
}
C 4900 3900 1 0 0 out_port.sym
{
T 5900 3900 5 10 1 1 0 0 1 1
refdes=wb_cab_o
refdes=wb_stb_o
}
C 4900 4300 1 0 0 out_port.sym
{
T 5900 4300 5 10 1 1 0 0 1 1
refdes=tdo_o
refdes=wb_cyc_o
}
C 4900 4700 1 0 0 out_port.sym
{
T 5900 4700 5 10 1 1 0 0 1 1
refdes=int_o
refdes=wb_cab_o
}
C 4900 5100 1 0 0 out_port.sym
{
T 5900 5100 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
refdes=tdo_o
}
C 4900 5500 1 0 0 out_port.sym
{
T 5900 5500 5 10 1 1 0 0 1 1
refdes=int_o
}
C 4900 5900 1 0 0 out_port.sym
{
T 5900 5900 5 10 1 1 0 0 1 1
refdes=cpu0_we_o
}
C 4900 6300 1 0 0 out_port.sym
{
T 5900 6300 5 10 1 1 0 0 1 1
refdes=cpu0_stb_o
}
C 4900 6700 1 0 0 out_port.sym
{
T 5900 6700 5 10 1 1 0 0 1 1
refdes=cpu0_stall_o
}
C 4900 7100 1 0 0 out_port.sym
{
T 5900 7100 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
}
C 4900 7500 1 0 0 out_port.sym
{
T 5900 7500 5 10 1 1 0 0 1 1
refdes=biu_wr_strobe
}
/Geda/sch/adv_dbg_if_wb_cpu2_jsp.sch
29,89 → 29,119
T 2000 2300 5 10 1 1 0 6 1 1
refdes=wb_dat_i[31:0]
}
C 2000 2700 1 0 0 in_port.sym
C 2000 2700 1 0 0 in_port_v.sym
{
T 2000 2700 5 10 1 1 0 6 1 1
refdes=wb_rst_i
T 2000 2700 5 10 1 1 0 6 1 1
refdes=cpu1_data_i[31:0]
}
C 2000 3100 1 0 0 in_port.sym
C 2000 3100 1 0 0 in_port_v.sym
{
T 2000 3100 5 10 1 1 0 6 1 1
refdes=wb_jsp_we_i
T 2000 3100 5 10 1 1 0 6 1 1
refdes=cpu0_data_i[31:0]
}
C 2000 3500 1 0 0 in_port.sym
{
T 2000 3500 5 10 1 1 0 6 1 1
refdes=wb_jsp_stb_i
refdes=wb_rst_i
}
C 2000 3900 1 0 0 in_port.sym
{
T 2000 3900 5 10 1 1 0 6 1 1
refdes=wb_jsp_cyc_i
refdes=wb_jsp_we_i
}
C 2000 4300 1 0 0 in_port.sym
{
T 2000 4300 5 10 1 1 0 6 1 1
refdes=wb_jsp_cab_i
refdes=wb_jsp_stb_i
}
C 2000 4700 1 0 0 in_port.sym
{
T 2000 4700 5 10 1 1 0 6 1 1
refdes=wb_err_i
refdes=wb_jsp_cyc_i
}
C 2000 5100 1 0 0 in_port.sym
{
T 2000 5100 5 10 1 1 0 6 1 1
refdes=wb_clk_i
refdes=wb_jsp_cab_i
}
C 2000 5500 1 0 0 in_port.sym
{
T 2000 5500 5 10 1 1 0 6 1 1
refdes=wb_ack_i
refdes=wb_err_i
}
C 2000 5900 1 0 0 in_port.sym
{
T 2000 5900 5 10 1 1 0 6 1 1
refdes=update_dr_i
refdes=wb_clk_i
}
C 2000 6300 1 0 0 in_port.sym
{
T 2000 6300 5 10 1 1 0 6 1 1
refdes=tdi_i
refdes=wb_ack_i
}
C 2000 6700 1 0 0 in_port.sym
{
T 2000 6700 5 10 1 1 0 6 1 1
refdes=tck_i
refdes=update_dr_i
}
C 2000 7100 1 0 0 in_port.sym
{
T 2000 7100 5 10 1 1 0 6 1 1
refdes=shift_dr_i
refdes=tdi_i
}
C 2000 7500 1 0 0 in_port.sym
{
T 2000 7500 5 10 1 1 0 6 1 1
refdes=rst_i
refdes=tck_i
}
C 2000 7900 1 0 0 in_port.sym
{
T 2000 7900 5 10 1 1 0 6 1 1
refdes=debug_select_i
refdes=shift_dr_i
}
C 2000 8300 1 0 0 in_port.sym
{
T 2000 8300 5 10 1 1 0 6 1 1
refdes=cpu1_clk_i
refdes=rst_i
}
C 2000 8700 1 0 0 in_port.sym
{
T 2000 8700 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
refdes=debug_select_i
}
C 2000 9100 1 0 0 in_port.sym
{
T 2000 9100 5 10 1 1 0 6 1 1
refdes=cpu1_clk_i
}
C 2000 9500 1 0 0 in_port.sym
{
T 2000 9500 5 10 1 1 0 6 1 1
refdes=cpu1_bp_i
}
C 2000 9900 1 0 0 in_port.sym
{
T 2000 9900 5 10 1 1 0 6 1 1
refdes=cpu1_ack_i
}
C 2000 10300 1 0 0 in_port.sym
{
T 2000 10300 5 10 1 1 0 6 1 1
refdes=cpu0_clk_i
}
C 2000 10700 1 0 0 in_port.sym
{
T 2000 10700 5 10 1 1 0 6 1 1
refdes=cpu0_bp_i
}
C 2000 11100 1 0 0 in_port.sym
{
T 2000 11100 5 10 1 1 0 6 1 1
refdes=cpu0_ack_i
}
C 2000 11500 1 0 0 in_port.sym
{
T 2000 11500 5 10 1 1 0 6 1 1
refdes=capture_dr_i
}
C 5100 300 1 0 0 out_port_v.sym
144,53 → 174,103
T 6100 2300 5 10 1 1 0 0 1 1
refdes=wb_adr_o[31:0]
}
C 5100 2700 1 0 0 out_port.sym
C 5100 2700 1 0 0 out_port_v.sym
{
T 6100 2700 5 10 1 1 0 0 1 1
refdes=wb_we_o
T 6100 2700 5 10 1 1 0 0 1 1
refdes=cpu1_data_o[31:0]
}
C 5100 3100 1 0 0 out_port.sym
C 5100 3100 1 0 0 out_port_v.sym
{
T 6100 3100 5 10 1 1 0 0 1 1
refdes=wb_stb_o
T 6100 3100 5 10 1 1 0 0 1 1
refdes=cpu1_addr_o[31:0]
}
C 5100 3500 1 0 0 out_port.sym
C 5100 3500 1 0 0 out_port_v.sym
{
T 6100 3500 5 10 1 1 0 0 1 1
refdes=wb_jsp_err_o
T 6100 3500 5 10 1 1 0 0 1 1
refdes=cpu0_data_o[31:0]
}
C 5100 3900 1 0 0 out_port.sym
C 5100 3900 1 0 0 out_port_v.sym
{
T 6100 3900 5 10 1 1 0 0 1 1
refdes=wb_jsp_ack_o
T 6100 3900 5 10 1 1 0 0 1 1
refdes=cpu0_addr_o[31:0]
}
C 5100 4300 1 0 0 out_port.sym
{
T 6100 4300 5 10 1 1 0 0 1 1
refdes=wb_cyc_o
refdes=wb_we_o
}
C 5100 4700 1 0 0 out_port.sym
{
T 6100 4700 5 10 1 1 0 0 1 1
refdes=wb_cab_o
refdes=wb_stb_o
}
C 5100 5100 1 0 0 out_port.sym
{
T 6100 5100 5 10 1 1 0 0 1 1
refdes=tdo_o
refdes=wb_jsp_err_o
}
C 5100 5500 1 0 0 out_port.sym
{
T 6100 5500 5 10 1 1 0 0 1 1
refdes=int_o
refdes=wb_jsp_ack_o
}
C 5100 5900 1 0 0 out_port.sym
{
T 6100 5900 5 10 1 1 0 0 1 1
refdes=cpu1_rst_o
refdes=wb_cyc_o
}
C 5100 6300 1 0 0 out_port.sym
{
T 6100 6300 5 10 1 1 0 0 1 1
refdes=wb_cab_o
}
C 5100 6700 1 0 0 out_port.sym
{
T 6100 6700 5 10 1 1 0 0 1 1
refdes=tdo_o
}
C 5100 7100 1 0 0 out_port.sym
{
T 6100 7100 5 10 1 1 0 0 1 1
refdes=int_o
}
C 5100 7500 1 0 0 out_port.sym
{
T 6100 7500 5 10 1 1 0 0 1 1
refdes=cpu1_we_o
}
C 5100 7900 1 0 0 out_port.sym
{
T 6100 7900 5 10 1 1 0 0 1 1
refdes=cpu1_stb_o
}
C 5100 8300 1 0 0 out_port.sym
{
T 6100 8300 5 10 1 1 0 0 1 1
refdes=cpu1_stall_o
}
C 5100 8700 1 0 0 out_port.sym
{
T 6100 8700 5 10 1 1 0 0 1 1
refdes=cpu1_rst_o
}
C 5100 9100 1 0 0 out_port.sym
{
T 6100 9100 5 10 1 1 0 0 1 1
refdes=cpu0_we_o
}
C 5100 9500 1 0 0 out_port.sym
{
T 6100 9500 5 10 1 1 0 0 1 1
refdes=cpu0_stb_o
}
C 5100 9900 1 0 0 out_port.sym
{
T 6100 9900 5 10 1 1 0 0 1 1
refdes=cpu0_stall_o
}
C 5100 10300 1 0 0 out_port.sym
{
T 6100 10300 5 10 1 1 0 0 1 1
refdes=cpu0_rst_o
}

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