URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
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- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
- from Rev 131 to Rev 133
- ↔ Reverse comparison
Rev 131 → Rev 133
/adbg_bytefifo.v
57,7 → 57,7
// CLK: Clock for all synchronous elements |
// RST: Zeros the counter and all registers asynchronously |
// DATA_IN: Data to be pushed into the FIFO |
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty |
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty |
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the |
// FIFO and the count will be incremented at the next posedge |
// of CLK (assuming the FIFO is not full). When low (and EN |
217,7 → 217,7
4'h6: DATA_OUT = reg5; |
4'h7: DATA_OUT = reg6; |
4'h8: DATA_OUT = reg7; |
default: DATA_OUT = 8'hXX; |
default: DATA_OUT = 8'h00; |
endcase |
end |
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