URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl
- from Rev 131 to Rev 133
- ↔ Reverse comparison
Rev 131 → Rev 133
/xml/adv_dbg_if_jsp.xml
52,6 → 52,23
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
58,12 → 75,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jsp</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_wb_cpu0_jfifo.xml
50,7 → 50,23
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
58,13 → 74,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu0_jfifo</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_jfifo.xml
52,6 → 52,24
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
58,12 → 76,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>fifo</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_wb_cpu2_jsp.xml
49,7 → 49,23
<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
/xml/adv_dbg_if_cpu0_i.xml
76,7 → 76,7
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<spirit:busInterface><spirit:name>cpu0_debug</spirit:name> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="or1k" spirit:name="or1200" spirit:version="dbg_rtl"/> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="or1k" spirit:version="dbg_rtl"/> |
<spirit:master/> |
<spirit:portMaps> |
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/xml/adv_dbg_if_wb_cpu0.xml
45,6 → 45,24
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
51,13 → 69,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu0</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_cpu1_i.xml
76,7 → 76,7
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<spirit:busInterface><spirit:name>cpu1_debug</spirit:name> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="or1k" spirit:name="or1200" spirit:version="dbg_rtl"/> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="or1k" spirit:version="dbg_rtl"/> |
<spirit:master/> |
<spirit:portMaps> |
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/xml/adv_dbg_if_cpu0.xml
44,6 → 44,22
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
50,13 → 66,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>cpu0</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_cpu1.xml
43,7 → 43,24
<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
50,13 → 67,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>cpu1</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_wb.xml
48,6 → 48,27
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
54,13 → 75,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>wb</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/xml/adv_dbg_if_wb_cpu0_jsp.xml
50,7 → 50,22
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
58,13 → 73,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
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<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu0_jsp</spirit:value> |
</spirit:parameter> |
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<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
/verilog/adbg_bytefifo.v
57,7 → 57,7
// CLK: Clock for all synchronous elements |
// RST: Zeros the counter and all registers asynchronously |
// DATA_IN: Data to be pushed into the FIFO |
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty |
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty |
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the |
// FIFO and the count will be incremented at the next posedge |
// of CLK (assuming the FIFO is not full). When low (and EN |
217,7 → 217,7
4'h6: DATA_OUT = reg5; |
4'h7: DATA_OUT = reg6; |
4'h8: DATA_OUT = reg7; |
default: DATA_OUT = 8'hXX; |
default: DATA_OUT = 8'h00; |
endcase |
end |
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