URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/rtl/xml/adv_dbg_if_jsp.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
51,23 → 51,11
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
79,10 → 67,6
<spirit:name>destination</spirit:name> |
<spirit:value>jsp</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_wb_cpu0_jfifo.xml
50,19 → 50,6
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
78,10 → 65,6
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu0_jfifo</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_jfifo.xml
51,24 → 51,8
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
80,10 → 64,6
<spirit:name>destination</spirit:name> |
<spirit:value>fifo</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_wb_cpu2_jsp.xml
50,19 → 50,6
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
72,17 → 59,10
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
|
|
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu2_jsp</spirit:value> |
</spirit:parameter> |
|
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_wb_cpu0.xml
44,24 → 44,9
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
73,10 → 58,6
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu0</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_cpu0.xml
43,22 → 43,10
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
70,10 → 58,6
<spirit:name>destination</spirit:name> |
<spirit:value>cpu0</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_cpu1.xml
44,19 → 44,6
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
71,10 → 58,6
<spirit:name>destination</spirit:name> |
<spirit:value>cpu1</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_wb.xml
39,36 → 39,9
<spirit:name>adv_dbg_if</spirit:name> |
<spirit:version>wb</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
79,10 → 52,6
<spirit:name>destination</spirit:name> |
<spirit:value>wb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/rtl/xml/adv_dbg_if_wb_cpu0_jsp.xml
50,19 → 50,6
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
77,10 → 64,6
<spirit:name>destination</spirit:name> |
<spirit:value>wb_cpu0_jsp</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
/sim/testbenches/xml/adv_dbg_if_cpu0_dutg.design.xml
File deleted
/sim/testbenches/xml/adv_dbg_if_cpu1_dutg.design.xml
File deleted
/sim/testbenches/xml/adv_dbg_if_jsp_dutg.design.xml
File deleted
/sim/testbenches/xml/adv_dbg_if_wb_dutg.design.xml
File deleted
/sim/testbenches/xml/adv_dbg_if_cpu0_lint.xml
39,47 → 39,10
<spirit:name>adv_dbg_if</spirit:name> |
<spirit:version>cpu0_lint</spirit:version> |
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
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|
<spirit:model> |
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|
/sim/testbenches/xml/adv_dbg_if_cpu1_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.cpu1</spirit:value> |
<spirit:value>adv_dbg_if_cpu1_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
178,7 → 171,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.cpu1</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_cpu1_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
192,7 → 185,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.cpu1</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_cpu1_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/sim/testbenches/xml/adv_dbg_if_wb_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.wb</spirit:value> |
<spirit:value>adv_dbg_if_wb_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
189,7 → 182,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.wb</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_wb_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
203,7 → 196,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.wb</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_wb_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/sim/testbenches/xml/adv_dbg_if_jsp_lint.xml
40,46 → 40,9
<spirit:version>jsp_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
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|
<spirit:model> |
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/sim/testbenches/xml/adv_dbg_if_jfifo_lint.xml
40,47 → 40,11
<spirit:version>jfifo_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
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|
<spirit:model> |
|
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/sim/testbenches/xml/adv_dbg_if_cpu0_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.cpu0</spirit:value> |
<spirit:value>adv_dbg_if_cpu0_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
179,7 → 172,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.cpu0</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_cpu0_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
193,7 → 186,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.cpu0</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_cpu0_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/sim/testbenches/xml/adv_dbg_if_wb_lint.xml
39,47 → 39,9
<spirit:name>adv_dbg_if</spirit:name> |
<spirit:version>wb_lint</spirit:version> |
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
|
|
/sim/testbenches/xml/adv_dbg_if_cpu1_lint.xml
41,45 → 41,9
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
<spirit:model> |
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/sim/testbenches/xml/adv_dbg_if_wb_cpu2_jsp_lint.xml
40,47 → 40,10
<spirit:version>wb_cpu2_jsp_lint</spirit:version> |
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:model> |
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/sim/testbenches/xml/adv_dbg_if_jfifo_sync_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.fifo_sync</spirit:value> |
<spirit:value>adv_dbg_if_jfifo_sync_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
191,7 → 184,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.fifo_sync</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_jfifo_sync_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
205,7 → 198,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.fifo_sync</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_jfifo_sync_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/sim/testbenches/xml/adv_dbg_if_jsp_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.jsp</spirit:value> |
<spirit:value>adv_dbg_if_jsp_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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192,7 → 185,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.jsp</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_jsp_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
206,7 → 199,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.jsp</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_jsp_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/sim/testbenches/xml/adv_dbg_if_jfifo_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.jfifo</spirit:value> |
<spirit:value>adv_dbg_if_jfifo_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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190,7 → 183,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.jfifo</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_jfifo_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
204,7 → 197,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.jfifo</spirit:name> |
<spirit:name>../verilog/common/adv_dbg_if_jfifo_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/sim/testbenches/xml/adv_dbg_if_wb_cpu0_lint.xml
39,47 → 39,9
<spirit:name>adv_dbg_if</spirit:name> |
<spirit:version>wb_cpu0_lint</spirit:version> |
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:model> |
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