URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml
- from Rev 131 to Rev 133
- ↔ Reverse comparison
Rev 131 → Rev 133
/Nexys2_T6502_core.xml
45,7 → 45,28
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>core</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
214,50 → 235,10
</spirit:fileSetRef> |
</spirit:view> |
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</spirit:views> |
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>RAM_WORDS</spirit:name><spirit:value>2048</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RAM_ADD</spirit:name><spirit:value>11</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ROM_WORDS</spirit:name><spirit:value>4096</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ROM_ADD</spirit:name><spirit:value>12</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>PROG_ROM_WORDS</spirit:name><spirit:value>ROM_WORDS</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>PROG_ROM_ADD</spirit:name><spirit:value>ROM_ADD</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>VEC_TABLE</spirit:name><spirit:value>8'hff</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>JTAG_SEL</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>JTAG_USER1_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>JTAG_USER1_RESET</spirit:name><spirit:value>8'h12</spirit:value></spirit:modelParameter> |
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</spirit:modelParameters> |
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</spirit:model> |
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</spirit:component> |
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/Nexys2_T6502_core.design.xml
58,7 → 58,6
<spirit:logicalPort><spirit:name>tdo</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>jtag_tdo</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>0</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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66,7 → 65,6
<spirit:logicalPort><spirit:name>select</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>jtag_select</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>0</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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81,13 → 79,23
</spirit:portMaps> |
</spirit:activeInterface> |
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</spirit:interconnection> |
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<spirit:interconnection> |
<spirit:name>aux_jtag</spirit:name> |
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<spirit:activeInterface spirit:componentRef="disp_io" spirit:busRef="jtag"> |
</spirit:activeInterface> |
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</spirit:interconnection> |
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</spirit:interconnections> |
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774,7 → 782,7
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<spirit:componentInstance> |
<spirit:instanceName>disp_io</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="logic" spirit:name="disp_io" spirit:version="def" /> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="logic" spirit:name="disp_io" spirit:version="jtag" /> |
</spirit:componentInstance> |
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<spirit:componentInstance> |
/Nexys2_T6502_default.xml
38,18 → 38,28
<spirit:name>Nexys2_T6502</spirit:name> |
<spirit:version>default</spirit:version> <spirit:configuration>default</spirit:configuration> |
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
58,10 → 68,6
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.T6502_default</spirit:value> |
</spirit:parameter> |
72,20 → 78,10
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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103,19 → 99,10
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
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<spirit:views> |
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<spirit:view> |
/Nexys2_T6502_fpga.design.xml
58,7 → 58,6
<spirit:configurableElementValue spirit:referenceId="UART_PRESCALE">UART_PRESCALE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_PRE_SIZE">UART_PRE_SIZE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_DIV">UART_DIV</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="JTAG_SEL">JTAG_SEL</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="JTAG_USER1_WIDTH">JTAG_USER1_WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="JTAG_USER1_RESET">JTAG_USER1_RESET</spirit:configurableElementValue> |
</spirit:configurableElementValues> |