URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/xml
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/Nexys2_T6502_kim_2.xml
39,49 → 39,10
<spirit:version>kim_2</spirit:version> |
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>env</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>tool</spirit:name> |
<spirit:value>ise</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>unit</spirit:name> |
<spirit:value>chip</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
90,23 → 51,12
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>local_parameters</spirit:name> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>kim_2</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.T6502_kim_2.syn</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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126,28 → 76,10
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram.load</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.T6502_kim_2.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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196,11 → 128,6
</spirit:vendorExtensions> |
</spirit:view> |
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<spirit:view> |
<spirit:name>ise</spirit:name> |
<spirit:vendorExtensions> |
211,10 → 138,6
</spirit:vendorExtensions> |
</spirit:view> |
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<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
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226,16 → 149,9
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</spirit:views> |
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</spirit:model> |
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</spirit:component> |
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