URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/io/ip/io_ps2/sim/testbenches
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/xml/io_ps2_def_dutg.design.xml
File deleted
/xml/io_ps2_mouse_dutg.design.xml
File deleted
/xml/io_ps2_mouse_tb.xml
57,15 → 57,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.mouse.tb</spirit:value> |
<spirit:value>io_ps2_mouse_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
194,7 → 187,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.mouse.tb</spirit:name> |
<spirit:name>../verilog/common/io_ps2_mouse_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
209,7 → 202,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.mouse.tb</spirit:name> |
<spirit:name>../verilog/common/io_ps2_mouse_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/xml/io_ps2_mouse_lint.xml
41,47 → 41,10
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<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:model> |
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/xml/io_ps2_def_tb.xml
58,15 → 58,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
<spirit:value>io_ps2_def_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
207,7 → 200,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/io_ps2_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
219,7 → 212,7
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/io_ps2_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/xml/io_ps2_def_lint.xml
42,49 → 42,9
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<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:model> |
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