OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /socgen/trunk/Projects/opencores.org/io/ip
    from Rev 131 to Rev 133
    Reverse comparison

Rev 131 → Rev 133

/io_pic/rtl/xml/io_pic_def.xml
142,14 → 142,26
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/io_pic/sim/testbenches/xml/io_pic_def_lint.xml
39,9 → 39,46
<spirit:name>io_pic</spirit:name>
<spirit:version>def_lint</spirit:version>
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:model>
 
 
/io_pic/sim/testbenches/xml/io_pic_def_duth.design.xml
0,0 → 1,104
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_pic -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_pic</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_in</spirit:name>
<spirit:externalPortReference spirit:portRef="int_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>irq_out</spirit:name>
<spirit:externalPortReference spirit:portRef="irq_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="irq_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>nmi_out</spirit:name>
<spirit:externalPortReference spirit:portRef="nmi_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="nmi_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_pic" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_pic/sim/testbenches/xml/io_pic_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_pic"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_uart/rtl/xml/io_uart_def.xml
137,12 → 137,26
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/io_uart/rtl/xml/io_uart_rxtx.xml
137,12 → 137,26
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
167,7 → 181,7
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
<spirit:value>top.rxtx</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
207,7 → 221,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top</spirit:name>
<spirit:name>../verilog/common/top.rxtx</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/io_uart/rtl/xml/io_uart_rx.xml
137,12 → 137,28
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
167,7 → 183,7
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
<spirit:value>top.rx</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
208,7 → 224,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top</spirit:name>
<spirit:name>../verilog/common/top.rx</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/io_uart/rtl/xml/io_uart_tx.xml
137,12 → 137,27
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
167,7 → 182,7
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
<spirit:value>top.tx</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
208,7 → 223,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top</spirit:name>
<spirit:name>../verilog/common/top.tx</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/io_uart/sim/testbenches/xml/io_uart_rxtx_duth.design.xml
0,0 → 1,134
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version rxtx //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_uart</spirit:name>
<spirit:version>rxtx_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rxd_data_avail_IRQ</spirit:name>
<spirit:externalPortReference spirit:portRef="rxd_data_avail_IRQ" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rxd_data_avail_IRQ" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>txd_buffer_empty_NIRQ</spirit:name>
<spirit:externalPortReference spirit:portRef="txd_buffer_empty_NIRQ" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="txd_buffer_empty_NIRQ" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="rxtx" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_uart/sim/testbenches/xml/io_uart_rxtx_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_uart"
spirit:version="rxtx_dutg.design"/>
spirit:version="rxtx_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_uart/sim/testbenches/xml/io_uart_rx_lint.xml
40,11 → 40,48
<spirit:version>rx_lint</spirit:version>
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
/io_uart/sim/testbenches/xml/io_uart_tx_lint.xml
41,10 → 41,47
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BUS_ADDR_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
/io_uart/sim/testbenches/xml/io_uart_def_lint.xml
40,12 → 40,49
<spirit:version>def_lint</spirit:version>
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
 
<spirit:model>
 
<spirit:modelParameters>
/io_uart/sim/testbenches/xml/io_uart_rx_duth.design.xml
0,0 → 1,122
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version rx //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_uart</spirit:name>
<spirit:version>rx_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="rx" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_uart/sim/testbenches/xml/io_uart_tx_duth.design.xml
0,0 → 1,122
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version tx //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_uart</spirit:name>
<spirit:version>tx_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="tx" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_uart/sim/testbenches/xml/io_uart_rx_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_uart"
spirit:version="rx_dutg.design"/>
spirit:version="rx_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_uart/sim/testbenches/xml/io_uart_tx_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_uart"
spirit:version="tx_dutg.design"/>
spirit:version="tx_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_uart/sim/testbenches/xml/io_uart_def_duth.design.xml
0,0 → 1,134
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_uart</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rxd_data_avail_IRQ</spirit:name>
<spirit:externalPortReference spirit:portRef="rxd_data_avail_IRQ" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rxd_data_avail_IRQ" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>txd_buffer_empty_NIRQ</spirit:name>
<spirit:externalPortReference spirit:portRef="txd_buffer_empty_NIRQ" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="txd_buffer_empty_NIRQ" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_uart/sim/testbenches/xml/io_uart_rxtx_lint.xml
40,10 → 40,47
<spirit:version>rxtx_lint</spirit:version>
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
 
/io_uart/sim/testbenches/xml/io_uart_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_uart"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_vga/rtl/xml/io_vga_def.xml
135,14 → 135,28
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/io_vga/sim/testbenches/xml/io_vga_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_vga"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_vga/sim/testbenches/xml/io_vga_def_lint.xml
41,11 → 41,48
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
<spirit:views>
/io_vga/sim/testbenches/xml/io_vga_def_duth.design.xml
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_vga -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_vga</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_blue_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_blue_pad_out" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_blue_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_green_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_green_pad_out" spirit:left="2" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_green_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_hsync_n_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_hsync_n_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_hsync_n_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_red_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_red_pad_out" spirit:left="2" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_red_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_vsync_n_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_vsync_n_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_vsync_n_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_vga" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_ext_mem_interface/componentCfg.xml
25,10 → 25,23
</socgen:doc>
 
 
<socgen:configurations>
 
<socgen:configuration>
<socgen:name>default</socgen:name>
<socgen:parameters>
<socgen:parameter><socgen:name>BASE_ADDR</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>BASE_WIDTH</socgen:name><socgen:value>4</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>ADDR_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>MEM_WIDTH</socgen:name><socgen:value>23</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>MEM_FRAME</socgen:name><socgen:value>10</socgen:value></socgen:parameter>
</socgen:parameters>
</socgen:configuration>
 
</socgen:configurations>
 
 
 
<socgen:sim>
 
 
/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml
149,7 → 149,7
<spirit:logicalPort><spirit:name>addr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>mem_addr</spirit:name>
<spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
<spirit:wire><spirit:vector><spirit:left>13</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
 
302,13 → 302,33
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
501,13 → 521,6
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BASE_ADDR</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>MEM_WIDTH</spirit:name><spirit:value>23</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>MEM_FRAME</spirit:name><spirit:value>10</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
 
/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_ext_mem_interface"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_lint.xml
42,10 → 42,47
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
<spirit:views>
/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_duth.design.xml
0,0 → 1,200
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_ext_mem_interface -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_ext_mem_interface</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>bank</spirit:name>
<spirit:externalPortReference spirit:portRef="bank" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bank" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_add</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_add" spirit:left="23" spirit:right="1" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_add" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_cs" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_lb</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_lb" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_lb" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_stb</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_stb" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_stb" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_ub</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_ub" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_ub" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_wdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_addr</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_addr" spirit:left="13" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_wdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wait_st</spirit:name>
<spirit:externalPortReference spirit:portRef="wait_st" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wait_st" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_ext_mem_interface" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_gpio/rtl/xml/io_gpio_def.xml
145,7 → 145,7
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
161,7 → 161,26
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
238,15 → 257,8
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>Hierarchical</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_gpio"
spirit:version="def.design"/>
</spirit:view>
 
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
/io_gpio/sim/testbenches/xml/io_gpio_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_gpio"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_gpio/sim/testbenches/xml/io_gpio_def_lint.xml
40,10 → 40,47
<spirit:version>def_lint</spirit:version>
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
 
/io_gpio/sim/testbenches/xml/io_gpio_def_duth.design.xml
0,0 → 1,122
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_gpio -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_gpio</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_gpio" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_timer/rtl/xml/io_timer_def.xml
138,11 → 138,27
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
243,14 → 259,6
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>Hierarchical</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_timer"
spirit:version="def.design"/>
</spirit:view>
 
<spirit:view>
<spirit:name>verilog</spirit:name>
/io_timer/sim/testbenches/xml/io_timer_def_duth.design.xml
0,0 → 1,93
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_timer -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_timer</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>irq</spirit:name>
<spirit:externalPortReference spirit:portRef="irq" spirit:left="TIMERS-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_timer" spirit:version="def" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="TIMERS">TIMERS</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_timer/sim/testbenches/xml/io_timer_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_timer"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_timer/sim/testbenches/xml/io_timer_def_lint.xml
41,9 → 41,46
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:model>
 
 
/io_vic/rtl/xml/io_vic_def.xml
135,12 → 135,28
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/io_vic/sim/testbenches/xml/io_vic_def_duth.design.xml
0,0 → 1,104
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_vic -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_vic</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_in</spirit:name>
<spirit:externalPortReference spirit:portRef="int_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>irq_out</spirit:name>
<spirit:externalPortReference spirit:portRef="irq_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="irq_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vector</spirit:name>
<spirit:externalPortReference spirit:portRef="vector" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vector" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_vic" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_vic/sim/testbenches/xml/io_vic_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_vic"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_vic/sim/testbenches/xml/io_vic_def_lint.xml
42,11 → 42,48
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
<spirit:views>
/io_ps2/rtl/xml/io_ps2_mouse.xml
136,13 → 136,28
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/io_ps2/rtl/xml/io_ps2_def.xml
136,6 → 136,19
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
142,7 → 155,7
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/io_ps2/sim/testbenches/xml/io_ps2_mouse_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_ps2"
spirit:version="mouse_dutg.design"/>
spirit:version="mouse_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_ps2/sim/testbenches/xml/io_ps2_def_duth.design.xml
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_ps2 -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_ps2</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rcv_data_avail</spirit:name>
<spirit:externalPortReference spirit:portRef="rcv_data_avail" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rcv_data_avail" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_ps2" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_ps2/sim/testbenches/xml/io_ps2_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_ps2"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/io_ps2/sim/testbenches/xml/io_ps2_mouse_tb.xml
46,36 → 46,9
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>mb</spirit:value>
</spirit:parameter>
</spirit:parameters>
 
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
84,7 → 57,7
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.tb</spirit:value>
<spirit:value>top.mouse.tb</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
221,7 → 194,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb</spirit:name>
<spirit:name>../verilog/common/top.mouse.tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
236,7 → 209,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb</spirit:name>
<spirit:name>../verilog/common/top.mouse.tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/io_ps2/sim/testbenches/xml/io_ps2_mouse_lint.xml
41,10 → 41,47
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
 
/io_ps2/sim/testbenches/xml/io_ps2_def_tb.xml
48,39 → 48,8
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>mb</spirit:value>
</spirit:parameter>
</spirit:parameters>
 
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
/io_ps2/sim/testbenches/xml/io_ps2_def_lint.xml
42,12 → 42,49
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
 
<spirit:model>
 
 
/io_ps2/sim/testbenches/xml/io_ps2_mouse_duth.design.xml
0,0 → 1,152
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_ps2 -version mouse //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_ps2</spirit:name>
<spirit:version>mouse_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_left</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_left" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_left" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_mid</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_mid" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_mid" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_right</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_right" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_right" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>new_packet</spirit:name>
<spirit:externalPortReference spirit:portRef="new_packet" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="new_packet" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rcv_data_avail</spirit:name>
<spirit:externalPortReference spirit:portRef="rcv_data_avail" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rcv_data_avail" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>x_pos</spirit:name>
<spirit:externalPortReference spirit:portRef="x_pos" spirit:left="9" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="x_pos" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>y_pos</spirit:name>
<spirit:externalPortReference spirit:portRef="y_pos" spirit:left="9" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="y_pos" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_ps2" spirit:version="mouse" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_module/componentCfg.xml
54,7 → 54,32
 
 
 
<socgen:configurations>
 
 
 
 
 
<socgen:configuration>
<socgen:name>default</socgen:name>
<socgen:parameters>
<socgen:parameter><socgen:name>UART_PRESCALE</socgen:name><socgen:value>5'b01100</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>UART_PRE_SIZE</socgen:name><socgen:value>5</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>UART_DIV</socgen:name><socgen:value>0</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>BASE_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>ADDR_WIDTH</socgen:name><socgen:value>16</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>NMI_MODE</socgen:name><socgen:value>8'h00</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>IRQ_MODE</socgen:name><socgen:value>8'h00</socgen:value></socgen:parameter>
</socgen:parameters>
</socgen:configuration>
 
</socgen:configurations>
 
 
 
 
 
 
<socgen:sim>
 
 
/io_module/rtl/xml/io_module_mouse.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?>
<?xml version="1.0" encoding="utf-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
73,12 → 73,30
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
255,19 → 273,9
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
 
</spirit:modelParameters>
 
 
 
<spirit:ports>
 
 
/io_module/rtl/xml/io_module_def.xml
86,11 → 86,30
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
267,16 → 286,6
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
 
 
/io_module/rtl/xml/io_module_gpio.xml
73,11 → 73,30
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
256,21 → 275,10
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
 
</spirit:modelParameters>
 
 
 
 
 
<spirit:ports>
 
 
/io_module/sim/testbenches/xml/io_module_mouse_duth.design.xml
0,0 → 1,267
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_module -version mouse //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_module</spirit:name>
<spirit:version>mouse_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_left</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_left" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_left" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_mid</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_mid" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_mid" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_right</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_right" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_right" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>new_packet</spirit:name>
<spirit:externalPortReference spirit:portRef="new_packet" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="new_packet" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_irq_in</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_irq_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_nmi</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_nmi" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_nmi" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_avail</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_avail" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_avail" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_addr</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_addr" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>timer_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="timer_irq" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="timer_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wait_n</spirit:name>
<spirit:externalPortReference spirit:portRef="wait_n" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wait_n" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>x_pos</spirit:name>
<spirit:externalPortReference spirit:portRef="x_pos" spirit:left="9" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="x_pos" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>y_pos</spirit:name>
<spirit:externalPortReference spirit:portRef="y_pos" spirit:left="9" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="y_pos" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_module" spirit:version="mouse" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="ADDR_WIDTH">ADDR_WIDTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BASE_WIDTH">BASE_WIDTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="IRQ_MODE">IRQ_MODE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="NMI_MODE">NMI_MODE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="UART_DIV">UART_DIV</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="UART_PRESCALE">UART_PRESCALE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="UART_PRE_SIZE">UART_PRE_SIZE</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_module/sim/testbenches/xml/io_module_def_lint.xml
39,8 → 39,45
<spirit:name>io_module</spirit:name>
<spirit:version>def_lint</spirit:version>
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:model>
 
 
/io_module/sim/testbenches/xml/io_module_gpio_lint.xml
40,11 → 40,48
<spirit:version>gpio_lint</spirit:version>
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
 
/io_module/sim/testbenches/xml/io_module_mouse_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,17 → 26,8
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_module"
spirit:version="mouse_dutg.design"/>
spirit:version="mouse_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
</spirit:component>
/io_module/sim/testbenches/xml/io_module_def_duth.design.xml
0,0 → 1,404
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_module -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_module</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_addr</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_addr" spirit:left="23" spirit:right="1" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_cs" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_lb</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_lb" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_lb" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_stb</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_stb" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_stb" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_ub</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_ub" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_ub" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_wdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ext_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="ext_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_out</spirit:name>
<spirit:externalPortReference spirit:portRef="int_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_addr</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_addr" spirit:left="13" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_wdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mem_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="mem_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_left</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_left" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_left" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_mid</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_mid" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_mid" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ms_right</spirit:name>
<spirit:externalPortReference spirit:portRef="ms_right" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_right" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>new_packet</spirit:name>
<spirit:externalPortReference spirit:portRef="new_packet" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="new_packet" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_irq_in</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_irq_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_nmi</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_nmi" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_nmi" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_clk_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_avail</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_avail" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_avail" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ps2_data_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_addr</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_addr" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>timer_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="timer_irq" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="timer_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vector</spirit:name>
<spirit:externalPortReference spirit:portRef="vector" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vector" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_blue_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_blue_pad_out" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_blue_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_green_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_green_pad_out" spirit:left="2" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_green_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_hsync_n_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_hsync_n_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_hsync_n_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_red_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_red_pad_out" spirit:left="2" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_red_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vga_vsync_n_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="vga_vsync_n_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_vsync_n_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>vic_irq_in</spirit:name>
<spirit:externalPortReference spirit:portRef="vic_irq_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vic_irq_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>x_pos</spirit:name>
<spirit:externalPortReference spirit:portRef="x_pos" spirit:left="9" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="x_pos" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>y_pos</spirit:name>
<spirit:externalPortReference spirit:portRef="y_pos" spirit:left="9" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="y_pos" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_module" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_module/sim/testbenches/xml/io_module_gpio_duth.design.xml
0,0 → 1,201
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_module -version gpio //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_module</spirit:name>
<spirit:version>gpio_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_0_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_in</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>gpio_1_out</spirit:name>
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_irq_in</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_irq_in" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pic_nmi</spirit:name>
<spirit:externalPortReference spirit:portRef="pic_nmi" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_nmi" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_addr</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_addr" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_cs</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_rd</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_rdata" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wait</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wait" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wait" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reg_mb_wr</spirit:name>
<spirit:externalPortReference spirit:portRef="reg_mb_wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="rx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>timer_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="timer_irq" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="timer_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tx_irq</spirit:name>
<spirit:externalPortReference spirit:portRef="tx_irq" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_rxd_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>uart_txd_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wait_n</spirit:name>
<spirit:externalPortReference spirit:portRef="wait_n" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wait_n" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_module" spirit:version="gpio" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="ADDR_WIDTH">ADDR_WIDTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BASE_WIDTH">BASE_WIDTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="IRQ_MODE">IRQ_MODE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="NMI_MODE">NMI_MODE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="UART_DIV">UART_DIV</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="UART_PRESCALE">UART_PRESCALE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="UART_PRE_SIZE">UART_PRE_SIZE</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_module/sim/testbenches/xml/io_module_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,17 → 26,10
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_module"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>FONT</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>STARTUP</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
 
/io_module/sim/testbenches/xml/io_module_gpio_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,17 → 26,8
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_module"
spirit:version="gpio_dutg.design"/>
spirit:version="gpio_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
</spirit:component>
/io_module/sim/testbenches/xml/io_module_mouse_tb.xml
43,29 → 43,22
 
<spirit:componentGenerators>
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>reg_mb</spirit:value>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
73,6 → 66,7
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
81,6 → 75,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.mouse_tb</spirit:value>
</spirit:parameter>
/io_module/sim/testbenches/xml/io_module_mouse_lint.xml
39,10 → 39,47
<spirit:name>io_module</spirit:name>
<spirit:version>mouse_lint</spirit:version>
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
<spirit:views>
/io_module/sim/testbenches/xml/io_module_gpio_tb.xml
43,36 → 43,28
 
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>reg_mb</spirit:value>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
 
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
81,6 → 73,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.gpio_tb</spirit:value>
</spirit:parameter>
/io_module/sim/testbenches/xml/io_module_def_tb.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?>
<?xml version="1.0" encoding="utf-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
45,26 → 45,18
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>reg_mb</spirit:value>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
72,7 → 64,6
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
81,6 → 72,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.tb</spirit:value>
</spirit:parameter>
/io_utimer/rtl/xml/io_utimer_def.xml
134,13 → 134,27
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
254,14 → 268,6
 
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>Hierarchical</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_utimer"
spirit:version="def.design"/>
</spirit:view>
 
<spirit:view>
<spirit:name>verilog</spirit:name>
/io_utimer/sim/testbenches/xml/io_utimer_def_lint.xml
41,11 → 41,48
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
 
/io_utimer/sim/testbenches/xml/io_utimer_def_duth.design.xml
0,0 → 1,86
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_utimer -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>io</spirit:library>
<spirit:name>io_utimer</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>addr</spirit:name>
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cs</spirit:name>
<spirit:externalPortReference spirit:portRef="cs" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>enable</spirit:name>
<spirit:externalPortReference spirit:portRef="enable" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rd</spirit:name>
<spirit:externalPortReference spirit:portRef="rd" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rdata</spirit:name>
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wdata</spirit:name>
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wr</spirit:name>
<spirit:externalPortReference spirit:portRef="wr" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_utimer" spirit:version="def" />
<spirit:configurableElementValues>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/io_utimer/sim/testbenches/xml/io_utimer_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="io"
spirit:name="io_utimer"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>

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