URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/io
- from Rev 131 to Rev 133
- ↔ Reverse comparison
Rev 131 → Rev 133
/doc/Geda/html/io_ext_mem_interface_def.html
60,36 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">BASE_ADDR<br> </td> |
<td style="vertical-align: top;">4'h0<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">BASE_WIDTH<br> </td> |
<td style="vertical-align: top;">4<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">ADDR_WIDTH<br> </td> |
<td style="vertical-align: top;">8<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">MEM_WIDTH<br> </td> |
<td style="vertical-align: top;">23<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">MEM_FRAME<br> </td> |
<td style="vertical-align: top;">10<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
206,7 → 176,7
</tr> |
|
<tr> |
<td style="vertical-align: top;">mem_addr[15:0 ]<br> </td> |
<td style="vertical-align: top;">mem_addr[13:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
/doc/Geda/html/io_module_mouse.html
60,48 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">UART_PRESCALE<br> </td> |
<td style="vertical-align: top;">5'b01100<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">UART_PRE_SIZE<br> </td> |
<td style="vertical-align: top;">5<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">UART_DIV<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">BASE_WIDTH<br> </td> |
<td style="vertical-align: top;">8<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">ADDR_WIDTH<br> </td> |
<td style="vertical-align: top;">16<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">NMI_MODE<br> </td> |
<td style="vertical-align: top;">8'h00<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">IRQ_MODE<br> </td> |
<td style="vertical-align: top;">8'h00<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/doc/Geda/html/io_module_def.html
60,48 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">UART_PRESCALE<br> </td> |
<td style="vertical-align: top;">5'b01100<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">UART_PRE_SIZE<br> </td> |
<td style="vertical-align: top;">5<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">UART_DIV<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">BASE_WIDTH<br> </td> |
<td style="vertical-align: top;">8<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">ADDR_WIDTH<br> </td> |
<td style="vertical-align: top;">16<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">NMI_MODE<br> </td> |
<td style="vertical-align: top;">8'h00<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">IRQ_MODE<br> </td> |
<td style="vertical-align: top;">8'h00<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
248,7 → 206,7
</tr> |
|
<tr> |
<td style="vertical-align: top;">mem_addr[15:0 ]<br> </td> |
<td style="vertical-align: top;">mem_addr[13:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
/doc/Geda/html/io_module_gpio.html
60,48 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">UART_PRESCALE<br> </td> |
<td style="vertical-align: top;">5'b01100<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">UART_PRE_SIZE<br> </td> |
<td style="vertical-align: top;">5<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">UART_DIV<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">BASE_WIDTH<br> </td> |
<td style="vertical-align: top;">8<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">ADDR_WIDTH<br> </td> |
<td style="vertical-align: top;">16<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">NMI_MODE<br> </td> |
<td style="vertical-align: top;">8'h00<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">IRQ_MODE<br> </td> |
<td style="vertical-align: top;">8'h00<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/doc/Geda/src/io_uart_rx.v
37,9 → 37,9
module |
io_uart_rx |
#( parameter |
DIV=0, |
PRESCALE=5'b01100, |
PRE_SIZE=5, |
DIV=0, |
RX_FIFO_SIZE=3, |
RX_FIFO_WORDS=8) |
( |
65,38 → 65,38
wire [ 7 : 0] cntrl; |
wire [ 7 : 0] rcv_data; |
wire [ 7 : 0] status; |
//////////////////////////////////////////////////////////////// |
uart_rx |
#( .PRESCALE (PRESCALE), |
#( .DIV (DIV), |
.PRESCALE (PRESCALE), |
.PRE_SIZE (PRE_SIZE), |
.DIV (DIV), |
.RX_FIFO_SIZE (RX_FIFO_SIZE), |
.RX_FIFO_WORDS (RX_FIFO_WORDS)) |
uart |
( |
.clk (clk), |
.cts_out (status[4]), |
.cts_pad_in (cts_pad_in), |
.divider_in (4'b1011), |
.parity_enable (cntrl[4]), |
.reset (reset), |
.rts_in (cntrl[3]), |
.rts_pad_out (rts_pad_out), |
.rxd_data_avail (rxd_data_avail), |
.rxd_data_avail_stb (rxd_data_avail_stb), |
.rxd_data_out (rcv_data[7:0]), |
.rxd_force_parity (cntrl[1]), |
.rxd_pad_in (uart_rxd_pad_in), |
.rxd_parity (cntrl[0]), |
.rxd_parity_error (status[3]), |
.rxd_stop_error (status[1]), |
.txd_break (cntrl[2]), |
.txd_buffer_empty (status[5]), |
.txd_data_in (lat_wdata), |
.txd_force_parity (cntrl[1]), |
.txd_load (txd_load), |
.txd_pad_out (uart_txd_pad_out), |
.txd_parity (cntrl[0])); |
.rxd_pad_in ( uart_rxd_pad_in ), |
.txd_pad_out ( uart_txd_pad_out ), |
.clk ( clk ), |
.cts_out ( status[4:4] ), |
.cts_pad_in ( cts_pad_in ), |
.divider_in ( 4'b1011 ), |
.parity_enable ( cntrl[4:4] ), |
.reset ( reset ), |
.rts_in ( cntrl[3:3] ), |
.rts_pad_out ( rts_pad_out ), |
.rxd_data_avail ( rxd_data_avail ), |
.rxd_data_avail_IRQ ( ), |
.rxd_data_avail_stb ( rxd_data_avail_stb ), |
.rxd_data_out ( rcv_data[7:0] ), |
.rxd_force_parity ( cntrl[1:1] ), |
.rxd_parity ( cntrl[0:0] ), |
.rxd_parity_error ( status[3:3] ), |
.rxd_stop_error ( status[1:1] ), |
.txd_break ( cntrl[2:2] ), |
.txd_buffer_empty ( status[5:5] ), |
.txd_data_in ( lat_wdata ), |
.txd_force_parity ( cntrl[1:1] ), |
.txd_load ( txd_load ), |
.txd_parity ( cntrl[0:0] )); |
wire xmit_data_wr; |
wire rcv_data_rd; |
io_uart_rx_mb |
/doc/Geda/src/io_uart_tx.v
37,9 → 37,9
module |
io_uart_tx |
#( parameter |
DIV=0, |
PRESCALE=5'b01100, |
PRE_SIZE=5, |
DIV=0, |
TX_FIFO_SIZE=3, |
TX_FIFO_WORDS=8) |
( |
65,38 → 65,38
wire [ 7 : 0] cntrl; |
wire [ 7 : 0] rcv_data; |
wire [ 7 : 0] status; |
//////////////////////////////////////////////////////////////// |
uart_tx |
#( .PRESCALE (PRESCALE), |
#( .DIV (DIV), |
.PRESCALE (PRESCALE), |
.PRE_SIZE (PRE_SIZE), |
.DIV (DIV), |
.TX_FIFO_SIZE (TX_FIFO_SIZE), |
.TX_FIFO_WORDS (TX_FIFO_WORDS)) |
uart |
( |
.clk (clk), |
.cts_out (status[4]), |
.cts_pad_in (cts_pad_in), |
.divider_in (4'b1011), |
.parity_enable (cntrl[4]), |
.reset (reset), |
.rts_in (cntrl[3]), |
.rts_pad_out (rts_pad_out), |
.rxd_data_avail (rxd_data_avail), |
.rxd_data_avail_stb (rxd_data_avail_stb), |
.rxd_data_out (rcv_data[7:0]), |
.rxd_force_parity (cntrl[1]), |
.rxd_pad_in (uart_rxd_pad_in), |
.rxd_parity (cntrl[0]), |
.rxd_parity_error (status[3]), |
.rxd_stop_error (status[1]), |
.txd_break (cntrl[2]), |
.txd_buffer_empty (status[5]), |
.txd_data_in (lat_wdata), |
.txd_force_parity (cntrl[1]), |
.txd_load (txd_load), |
.txd_pad_out (uart_txd_pad_out), |
.txd_parity (cntrl[0])); |
.rxd_pad_in ( uart_rxd_pad_in ), |
.txd_pad_out ( uart_txd_pad_out ), |
.clk ( clk ), |
.cts_out ( status[4:4] ), |
.cts_pad_in ( cts_pad_in ), |
.divider_in ( 4'b1011 ), |
.parity_enable ( cntrl[4:4] ), |
.reset ( reset ), |
.rts_in ( cntrl[3:3] ), |
.rts_pad_out ( rts_pad_out ), |
.rxd_data_avail ( rxd_data_avail ), |
.rxd_data_avail_stb ( rxd_data_avail_stb ), |
.rxd_data_out ( rcv_data[7:0] ), |
.rxd_force_parity ( cntrl[1:1] ), |
.rxd_parity ( cntrl[0:0] ), |
.rxd_parity_error ( status[3:3] ), |
.rxd_stop_error ( status[1:1] ), |
.txd_break ( cntrl[2:2] ), |
.txd_buffer_empty ( status[5:5] ), |
.txd_buffer_empty_NIRQ ( ), |
.txd_data_in ( lat_wdata ), |
.txd_force_parity ( cntrl[1:1] ), |
.txd_load ( txd_load ), |
.txd_parity ( cntrl[0:0] )); |
wire xmit_data_wr; |
wire rcv_data_rd; |
io_uart_tx_mb |
/doc/Geda/src/io_uart_def.v
37,9 → 37,9
module |
io_uart_def |
#( parameter |
DIV=0, |
PRESCALE=5'b01100, |
PRE_SIZE=5, |
DIV=0) |
PRE_SIZE=5) |
( |
input wire clk, |
input wire cs, |
65,38 → 65,37
wire [ 7 : 0] cntrl; |
wire [ 7 : 0] rcv_data; |
wire [ 7 : 0] status; |
//////////////////////////////////////////////////////////////// |
uart_def |
#( .PRESCALE (PRESCALE), |
.PRE_SIZE (PRE_SIZE), |
.DIV (DIV)) |
#( .DIV (DIV), |
.PRESCALE (PRESCALE), |
.PRE_SIZE (PRE_SIZE)) |
uart |
( |
.clk (clk), |
.cts_out (status[4]), |
.cts_pad_in (cts_pad_in), |
.divider_in (4'b1011), |
.parity_enable (cntrl[4]), |
.reset (reset), |
.rts_in (cntrl[3]), |
.rts_pad_out (rts_pad_out), |
.rxd_data_avail (rxd_data_avail), |
.rxd_data_avail_IRQ (rxd_data_avail_IRQ), |
.rxd_data_avail_stb (rxd_data_avail_stb), |
.rxd_data_out (rcv_data[7:0]), |
.rxd_force_parity (cntrl[1]), |
.rxd_pad_in (uart_rxd_pad_in), |
.rxd_parity (cntrl[0]), |
.rxd_parity_error (status[3]), |
.rxd_stop_error (status[1]), |
.txd_break (cntrl[2]), |
.txd_buffer_empty (status[5]), |
.txd_buffer_empty_NIRQ (txd_buffer_empty_NIRQ), |
.txd_data_in (lat_wdata), |
.txd_force_parity (cntrl[1]), |
.txd_load (txd_load), |
.txd_pad_out (uart_txd_pad_out), |
.txd_parity (cntrl[0])); |
.rxd_data_avail_IRQ ( rxd_data_avail_IRQ ), |
.rxd_pad_in ( uart_rxd_pad_in ), |
.txd_buffer_empty_NIRQ ( txd_buffer_empty_NIRQ ), |
.txd_pad_out ( uart_txd_pad_out ), |
.clk ( clk ), |
.cts_out ( status[4:4] ), |
.cts_pad_in ( cts_pad_in ), |
.divider_in ( 4'b1011 ), |
.parity_enable ( cntrl[4:4] ), |
.reset ( reset ), |
.rts_in ( cntrl[3:3] ), |
.rts_pad_out ( rts_pad_out ), |
.rxd_data_avail ( rxd_data_avail ), |
.rxd_data_avail_stb ( rxd_data_avail_stb ), |
.rxd_data_out ( rcv_data[7:0] ), |
.rxd_force_parity ( cntrl[1:1] ), |
.rxd_parity ( cntrl[0:0] ), |
.rxd_parity_error ( status[3:3] ), |
.rxd_stop_error ( status[1:1] ), |
.txd_break ( cntrl[2:2] ), |
.txd_buffer_empty ( status[5:5] ), |
.txd_data_in ( lat_wdata ), |
.txd_force_parity ( cntrl[1:1] ), |
.txd_load ( txd_load ), |
.txd_parity ( cntrl[0:0] )); |
wire xmit_data_wr; |
wire rcv_data_rd; |
io_uart_def_mb |
/doc/Geda/src/io_vga_def.v
63,25 → 63,24
wire [ 7 : 0] char_color; |
wire [ 7 : 0] cntrl; |
wire [ 7 : 0] cursor_color; |
//////////////////////////////////////////////////////////////// |
vga_char_ctrl_def |
vga_char_ctrl |
( |
.add_h_load (add_h_load), |
.add_l_load (add_l_load), |
.address (vga_address[13:0]), |
.ascii_load (ascii_load), |
.back_color (back_color[7:0]), |
.blue_pad_out (vga_blue_pad_out[1:0]), |
.char_color (char_color[7:0]), |
.clk (clk), |
.cursor_color (cursor_color[7:0]), |
.green_pad_out (vga_green_pad_out[2:0]), |
.hsync_n_pad_out (vga_hsync_n_pad_out), |
.red_pad_out (vga_red_pad_out[2:0]), |
.reset (reset), |
.vsync_n_pad_out (vga_vsync_n_pad_out), |
.wdata (lat_wdata[7:0])); |
.blue_pad_out ( vga_blue_pad_out[1:0] ), |
.green_pad_out ( vga_green_pad_out[2:0] ), |
.hsync_n_pad_out ( vga_hsync_n_pad_out ), |
.red_pad_out ( vga_red_pad_out[2:0] ), |
.vsync_n_pad_out ( vga_vsync_n_pad_out ), |
.add_h_load ( add_h_load ), |
.add_l_load ( add_l_load ), |
.address ( vga_address[13:0] ), |
.ascii_load ( ascii_load ), |
.back_color ( back_color[7:0] ), |
.char_color ( char_color[7:0] ), |
.clk ( clk ), |
.cursor_color ( cursor_color[7:0] ), |
.reset ( reset ), |
.wdata ( lat_wdata[7:0] )); |
io_vga_def_mb |
#( .CNTRL_RST (8'b0), |
.CHAR_COLOR_RST (8'h1c), |
/doc/Geda/src/io_ext_mem_interface_def.v
37,11 → 37,11
module |
io_ext_mem_interface_def |
#( parameter |
ADDR_WIDTH=8, |
BASE_ADDR=4'h0, |
BASE_WIDTH=4, |
ADDR_WIDTH=8, |
MEM_WIDTH=23, |
MEM_FRAME=10) |
MEM_FRAME=10, |
MEM_WIDTH=23) |
( |
input wire clk, |
input wire cs, |
53,8 → 53,8
input wire rd, |
input wire reset, |
input wire wr, |
input wire [ 13 : 0] mem_addr, |
input wire [ 15 : 0] ext_rdata, |
input wire [ 15 : 0] mem_addr, |
input wire [ 15 : 0] mem_wdata, |
input wire [ 3 : 0] addr, |
input wire [ 7 : 0] wdata, |
71,7 → 71,6
output wire [ 7 : 0] bank, |
output wire [ 7 : 0] rdata, |
output wire [ 7 : 0] wait_st); |
//////////////////////////////////////////////////////////////// |
reg [3:0] enableY; |
reg wait_n; |
assign mem_rdata = ext_rdata; |
/doc/Geda/src/io_module_mouse.v
37,13 → 37,13
module |
io_module_mouse |
#( parameter |
UART_PRESCALE=5'b01100, |
UART_PRE_SIZE=5, |
UART_DIV=0, |
ADDR_WIDTH=16, |
BASE_WIDTH=8, |
ADDR_WIDTH=16, |
IRQ_MODE=8'h00, |
NMI_MODE=8'h00, |
IRQ_MODE=8'h00) |
UART_DIV=0, |
UART_PRESCALE=5'b01100, |
UART_PRE_SIZE=5) |
( |
input wire clk, |
input wire cts_pad_in, |
103,180 → 103,179
wire rxd_data_avail_IRQ; |
wire txd_buffer_empty_NIRQ; |
wire [ 0 : 0] mas_0_cs; |
wire [ 7 : 0] mas_0_addr; |
wire [ 3 : 0] mas_0_addr; |
wire [ 3 : 0] mas_1_addr; |
wire [ 3 : 0] mas_2_addr; |
wire [ 3 : 0] mas_3_addr; |
wire [ 3 : 0] mas_4_addr; |
wire [ 3 : 0] mas_5_addr; |
wire [ 7 : 0] mas_0_rdata; |
wire [ 7 : 0] mas_0_wdata; |
wire [ 7 : 0] mas_1_addr; |
wire [ 7 : 0] mas_1_rdata; |
wire [ 7 : 0] mas_1_wdata; |
wire [ 7 : 0] mas_2_addr; |
wire [ 7 : 0] mas_2_rdata; |
wire [ 7 : 0] mas_2_wdata; |
wire [ 7 : 0] mas_3_addr; |
wire [ 7 : 0] mas_3_rdata; |
wire [ 7 : 0] mas_3_wdata; |
wire [ 7 : 0] mas_4_addr; |
wire [ 7 : 0] mas_4_rdata; |
wire [ 7 : 0] mas_4_wdata; |
wire [ 7 : 0] mas_5_addr; |
wire [ 7 : 0] mas_5_rdata; |
wire [ 7 : 0] mas_5_wdata; |
//////////////////////////////////////////////////////////////// |
io_gpio_def |
gpio |
( |
.addr ( mas_0_addr[3:0] ), |
.cs ( mas_0_cs[0:0] ), |
.rd ( mas_0_rd ), |
.rdata ( mas_0_rdata[7:0] ), |
.wdata ( mas_0_wdata[7:0] ), |
.wr ( mas_0_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.gpio_0_in ( gpio_0_in ), |
.gpio_0_oe ( gpio_0_oe ), |
.gpio_0_out ( gpio_0_out ), |
.gpio_1_in ( gpio_1_in ), |
.gpio_1_oe ( gpio_1_oe ), |
.gpio_1_out ( gpio_1_out ), |
.reset ( reset )); |
micro_bus_exp6 |
mb_exp |
( |
.addr_in (reg_mb_addr[7:0]), |
.clk (clk), |
.cs_in (reg_mb_cs), |
.enable (enable), |
.mas_0_addr_out (mas_0_addr[7:0]), |
.mas_0_cs_out (mas_0_cs), |
.mas_0_rd_out (mas_0_rd), |
.mas_0_rdata_in (mas_0_rdata[7:0]), |
.mas_0_wdata_out (mas_0_wdata[7:0]), |
.mas_0_wr_out (mas_0_wr), |
.mas_1_addr_out (mas_1_addr[7:0]), |
.mas_1_cs_out (mas_1_cs), |
.mas_1_rd_out (mas_1_rd), |
.mas_1_rdata_in (mas_1_rdata[7:0]), |
.mas_1_wdata_out (mas_1_wdata[7:0]), |
.mas_1_wr_out (mas_1_wr), |
.mas_2_addr_out (mas_2_addr[7:0]), |
.mas_2_cs_out (mas_2_cs), |
.mas_2_rd_out (mas_2_rd), |
.mas_2_rdata_in (mas_2_rdata[7:0]), |
.mas_2_wdata_out (mas_2_wdata[7:0]), |
.mas_2_wr_out (mas_2_wr), |
.mas_3_addr_out (mas_3_addr[7:0]), |
.mas_3_cs_out (mas_3_cs), |
.mas_3_rd_out (mas_3_rd), |
.mas_3_rdata_in (mas_3_rdata[7:0]), |
.mas_3_wdata_out (mas_3_wdata[7:0]), |
.mas_3_wr_out (mas_3_wr), |
.mas_4_addr_out (mas_4_addr[7:0]), |
.mas_4_cs_out (mas_4_cs), |
.mas_4_rd_out (mas_4_rd), |
.mas_4_rdata_in (mas_4_rdata[7:0]), |
.mas_4_wdata_out (mas_4_wdata[7:0]), |
.mas_4_wr_out (mas_4_wr), |
.mas_5_addr_out (mas_5_addr[7:0]), |
.mas_5_cs_out (mas_5_cs), |
.mas_5_rd_out (mas_5_rd), |
.mas_5_rdata_in (mas_5_rdata[7:0]), |
.mas_5_wdata_out (mas_5_wdata[7:0]), |
.mas_5_wr_out (mas_5_wr), |
.rd_in (reg_mb_rd), |
.rdata_out (reg_mb_rdata[15:0]), |
.reset (reset), |
.wait_out (reg_mb_wait), |
.wdata_in (reg_mb_wdata[7:0]), |
.wr_in (reg_mb_wr)); |
io_gpio_def |
gpio |
.addr_in ( reg_mb_addr[7:0] ), |
.cs_in ( reg_mb_cs ), |
.mas_0_addr_out ( mas_0_addr[3:0] ), |
.mas_0_cs_out ( mas_0_cs[0:0] ), |
.mas_0_rd_out ( mas_0_rd ), |
.mas_0_rdata_in ( mas_0_rdata[7:0] ), |
.mas_0_wdata_out ( mas_0_wdata[7:0] ), |
.mas_0_wr_out ( mas_0_wr ), |
.mas_1_addr_out ( mas_1_addr[3:0] ), |
.mas_1_cs_out ( mas_1_cs ), |
.mas_1_rd_out ( mas_1_rd ), |
.mas_1_rdata_in ( mas_1_rdata[7:0] ), |
.mas_1_wdata_out ( mas_1_wdata[7:0] ), |
.mas_1_wr_out ( mas_1_wr ), |
.mas_2_addr_out ( mas_2_addr[3:0] ), |
.mas_2_cs_out ( mas_2_cs ), |
.mas_2_rd_out ( mas_2_rd ), |
.mas_2_rdata_in ( mas_2_rdata[7:0] ), |
.mas_2_wdata_out ( mas_2_wdata[7:0] ), |
.mas_2_wr_out ( mas_2_wr ), |
.mas_3_addr_out ( mas_3_addr[3:0] ), |
.mas_3_cs_out ( mas_3_cs ), |
.mas_3_rd_out ( mas_3_rd ), |
.mas_3_rdata_in ( mas_3_rdata[7:0] ), |
.mas_3_wdata_out ( mas_3_wdata[7:0] ), |
.mas_3_wr_out ( mas_3_wr ), |
.mas_4_addr_out ( mas_4_addr[3:0] ), |
.mas_4_cs_out ( mas_4_cs ), |
.mas_4_rd_out ( mas_4_rd ), |
.mas_4_rdata_in ( mas_4_rdata[7:0] ), |
.mas_4_wdata_out ( mas_4_wdata[7:0] ), |
.mas_4_wr_out ( mas_4_wr ), |
.mas_5_addr_out ( mas_5_addr[3:0] ), |
.mas_5_cs_out ( mas_5_cs ), |
.mas_5_rd_out ( mas_5_rd ), |
.mas_5_rdata_in ( mas_5_rdata[7:0] ), |
.mas_5_wdata_out ( mas_5_wdata[7:0] ), |
.mas_5_wr_out ( mas_5_wr ), |
.rd_in ( reg_mb_rd ), |
.rdata_out ( reg_mb_rdata[15:0] ), |
.wait_out ( reg_mb_wait ), |
.wdata_in ( reg_mb_wdata[7:0] ), |
.wr_in ( reg_mb_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
io_pic_def |
#( .IRQ_MODE (IRQ_MODE), |
.NMI_MODE (NMI_MODE)) |
pic |
( |
.addr (mas_0_addr[3:0]), |
.clk (clk), |
.cs (mas_0_cs[0]), |
.enable (enable), |
.gpio_0_in (gpio_0_in), |
.gpio_0_oe (gpio_0_oe), |
.gpio_0_out (gpio_0_out), |
.gpio_1_in (gpio_1_in), |
.gpio_1_oe (gpio_1_oe), |
.gpio_1_out (gpio_1_out), |
.rd (mas_0_rd), |
.rdata (mas_0_rdata[7:0]), |
.reset (reset), |
.wdata (mas_0_wdata[7:0]), |
.wr (mas_0_wr)); |
.addr ( mas_3_addr[3:0] ), |
.cs ( mas_3_cs ), |
.rd ( mas_3_rd ), |
.rdata ( mas_3_rdata[7:0] ), |
.wdata ( mas_3_wdata[7:0] ), |
.wr ( mas_3_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.int_in ( pic_irq_in ), |
.irq_out ( pic_irq ), |
.nmi_out ( pic_nmi ), |
.reset ( reset )); |
io_ps2_mouse |
ps2 |
( |
.addr ( mas_4_addr[3:0] ), |
.cs ( mas_4_cs ), |
.ps2_clk_pad_in ( ps2_clk_pad_in ), |
.ps2_clk_pad_oe ( ps2_clk_pad_oe ), |
.ps2_data_pad_in ( ps2_data_pad_in ), |
.ps2_data_pad_oe ( ps2_data_pad_oe ), |
.rd ( mas_4_rd ), |
.rdata ( mas_4_rdata[7:0] ), |
.wdata ( mas_4_wdata[7:0] ), |
.wr ( mas_4_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.ms_left ( ms_left ), |
.ms_mid ( ms_mid ), |
.ms_right ( ms_right ), |
.new_packet ( new_packet ), |
.rcv_data_avail ( ps2_data_avail ), |
.reset ( reset ), |
.x_pos ( x_pos ), |
.y_pos ( y_pos )); |
io_timer_def |
tim_0 |
( |
.addr (mas_1_addr[3:0]), |
.clk (clk), |
.cs (mas_1_cs), |
.enable (enable), |
.irq (timer_irq), |
.rd (mas_1_rd), |
.rdata (mas_1_rdata[7:0]), |
.reset (reset), |
.wdata (mas_1_wdata[7:0]), |
.wr (mas_1_wr)); |
.addr ( mas_1_addr[3:0] ), |
.cs ( mas_1_cs ), |
.rd ( mas_1_rd ), |
.rdata ( mas_1_rdata[7:0] ), |
.wdata ( mas_1_wdata[7:0] ), |
.wr ( mas_1_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.irq ( timer_irq ), |
.reset ( reset )); |
io_uart_def |
#( .PRESCALE (UART_PRESCALE), |
.PRE_SIZE (UART_PRE_SIZE), |
.DIV (UART_DIV)) |
#( .DIV (UART_DIV), |
.PRESCALE (UART_PRESCALE), |
.PRE_SIZE (UART_PRE_SIZE)) |
uart |
( |
.addr (mas_2_addr[3:0]), |
.clk (clk), |
.cs (mas_2_cs), |
.cts_pad_in (cts_pad_in), |
.enable (enable), |
.rd (mas_2_rd), |
.rdata (mas_2_rdata[7:0]), |
.reset (reset), |
.rts_pad_out (rts_pad_out), |
.rx_irq (rx_irq), |
.rxd_data_avail_IRQ (rxd_data_avail_IRQ), |
.tx_irq (tx_irq), |
.txd_buffer_empty_NIRQ (txd_buffer_empty_NIRQ), |
.uart_rxd_pad_in (uart_rxd_pad_in), |
.uart_txd_pad_out (uart_txd_pad_out), |
.wdata (mas_2_wdata[7:0]), |
.wr (mas_2_wr)); |
io_pic_def |
#( .NMI_MODE (NMI_MODE), |
.IRQ_MODE (IRQ_MODE)) |
pic |
( |
.addr (mas_3_addr[3:0]), |
.clk (clk), |
.cs (mas_3_cs), |
.enable (enable), |
.int_in (pic_irq_in), |
.irq_out (pic_irq), |
.nmi_out (pic_nmi), |
.rd (mas_3_rd), |
.rdata (mas_3_rdata[7:0]), |
.reset (reset), |
.wdata (mas_3_wdata[7:0]), |
.wr (mas_3_wr)); |
io_ps2_mouse |
ps2 |
( |
.addr (mas_4_addr[3:0]), |
.clk (clk), |
.cs (mas_4_cs), |
.enable (enable), |
.ms_left (ms_left), |
.ms_mid (ms_mid), |
.ms_right (ms_right), |
.new_packet (new_packet), |
.ps2_clk_pad_in (ps2_clk_pad_in), |
.ps2_clk_pad_oe (ps2_clk_pad_oe), |
.ps2_data_pad_in (ps2_data_pad_in), |
.ps2_data_pad_oe (ps2_data_pad_oe), |
.rcv_data_avail (ps2_data_avail), |
.rd (mas_4_rd), |
.rdata (mas_4_rdata[7:0]), |
.reset (reset), |
.wdata (mas_4_wdata[7:0]), |
.wr (mas_4_wr), |
.x_pos (x_pos), |
.y_pos (y_pos)); |
.addr ( mas_2_addr[3:0] ), |
.cs ( mas_2_cs ), |
.rd ( mas_2_rd ), |
.rdata ( mas_2_rdata[7:0] ), |
.rxd_data_avail_IRQ ( rxd_data_avail_IRQ ), |
.txd_buffer_empty_NIRQ ( txd_buffer_empty_NIRQ ), |
.uart_rxd_pad_in ( uart_rxd_pad_in ), |
.uart_txd_pad_out ( uart_txd_pad_out ), |
.wdata ( mas_2_wdata[7:0] ), |
.wr ( mas_2_wr ), |
.clk ( clk ), |
.cts_pad_in ( cts_pad_in ), |
.enable ( enable ), |
.reset ( reset ), |
.rts_pad_out ( rts_pad_out ), |
.rx_irq ( rx_irq ), |
.tx_irq ( tx_irq )); |
io_utimer_def |
utimer |
( |
.addr (mas_5_addr[3:0]), |
.clk (clk), |
.cs (mas_5_cs), |
.enable (enable), |
.rd (mas_5_rd), |
.rdata (mas_5_rdata[7:0]), |
.reset (reset), |
.wdata (mas_5_wdata[7:0]), |
.wr (mas_5_wr)); |
.addr ( mas_5_addr[3:0] ), |
.cs ( mas_5_cs ), |
.rd ( mas_5_rd ), |
.rdata ( mas_5_rdata[7:0] ), |
.wdata ( mas_5_wdata[7:0] ), |
.wr ( mas_5_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
reg wait_n_reg; |
always@(posedge clk) |
if(reset || enable) |
/doc/Geda/src/io_timer_def.v
49,7 → 49,6
input wire [ 7 : 0] wdata, |
output reg [ TIMERS-1 : 0] irq, |
output wire [ 7 : 0] rdata); |
//////////////////////////////////////////////////////////////// |
parameter TIMER_0_START = 4'h0; |
parameter TIMER_0_COUNT = 4'h2; |
parameter TIMER_0_END = 4'h4; |
/doc/Geda/src/io_vic_def.v
60,7 → 60,6
output reg irq_out, |
output reg [ 7 : 0] vector, |
output wire [ 7 : 0] rdata); |
//////////////////////////////////////////////////////////////// |
wire [7:0] irq_enable; |
reg [7:0] irq_act; |
io_vic_def_mb |
/doc/Geda/src/io_uart_rxtx.v
37,13 → 37,13
module |
io_uart_rxtx |
#( parameter |
DIV=0, |
PRESCALE=5'b01100, |
PRE_SIZE=5, |
DIV=0, |
RX_FIFO_SIZE=3, |
RX_FIFO_WORDS=8, |
TX_FIFO_SIZE=3, |
TX_FIFO_WORDS=8, |
RX_FIFO_SIZE=3, |
RX_FIFO_WORDS=8) |
TX_FIFO_WORDS=8) |
( |
input wire clk, |
input wire cs, |
69,42 → 69,41
wire [ 7 : 0] cntrl; |
wire [ 7 : 0] rcv_data; |
wire [ 7 : 0] status; |
//////////////////////////////////////////////////////////////// |
uart_rxtx |
#( .PRESCALE (PRESCALE), |
#( .DIV (DIV), |
.PRESCALE (PRESCALE), |
.PRE_SIZE (PRE_SIZE), |
.DIV (DIV), |
.RX_FIFO_SIZE (RX_FIFO_SIZE), |
.RX_FIFO_WORDS (RX_FIFO_WORDS), |
.TX_FIFO_SIZE (TX_FIFO_SIZE), |
.TX_FIFO_WORDS (TX_FIFO_WORDS), |
.RX_FIFO_SIZE (RX_FIFO_SIZE), |
.RX_FIFO_WORDS (RX_FIFO_WORDS)) |
.TX_FIFO_WORDS (TX_FIFO_WORDS)) |
uart |
( |
.clk (clk), |
.cts_out (status[4]), |
.cts_pad_in (cts_pad_in), |
.divider_in (4'b1011), |
.parity_enable (cntrl[4]), |
.reset (reset), |
.rts_in (cntrl[3]), |
.rts_pad_out (rts_pad_out), |
.rxd_data_avail (rxd_data_avail), |
.rxd_data_avail_IRQ (rxd_data_avail_IRQ), |
.rxd_data_avail_stb (rxd_data_avail_stb), |
.rxd_data_out (rcv_data[7:0]), |
.rxd_force_parity (cntrl[1]), |
.rxd_pad_in (uart_rxd_pad_in), |
.rxd_parity (cntrl[0]), |
.rxd_parity_error (status[3]), |
.rxd_stop_error (status[1]), |
.txd_break (cntrl[2]), |
.txd_buffer_empty (status[5]), |
.txd_buffer_empty_NIRQ (txd_buffer_empty_NIRQ), |
.txd_data_in (lat_wdata), |
.txd_force_parity (cntrl[1]), |
.txd_load (txd_load), |
.txd_pad_out (uart_txd_pad_out), |
.txd_parity (cntrl[0])); |
.rxd_data_avail_IRQ ( rxd_data_avail_IRQ ), |
.rxd_pad_in ( uart_rxd_pad_in ), |
.txd_buffer_empty_NIRQ ( txd_buffer_empty_NIRQ ), |
.txd_pad_out ( uart_txd_pad_out ), |
.clk ( clk ), |
.cts_out ( status[4:4] ), |
.cts_pad_in ( cts_pad_in ), |
.divider_in ( 4'b1011 ), |
.parity_enable ( cntrl[4:4] ), |
.reset ( reset ), |
.rts_in ( cntrl[3:3] ), |
.rts_pad_out ( rts_pad_out ), |
.rxd_data_avail ( rxd_data_avail ), |
.rxd_data_avail_stb ( rxd_data_avail_stb ), |
.rxd_data_out ( rcv_data[7:0] ), |
.rxd_force_parity ( cntrl[1:1] ), |
.rxd_parity ( cntrl[0:0] ), |
.rxd_parity_error ( status[3:3] ), |
.rxd_stop_error ( status[1:1] ), |
.txd_break ( cntrl[2:2] ), |
.txd_buffer_empty ( status[5:5] ), |
.txd_data_in ( lat_wdata ), |
.txd_force_parity ( cntrl[1:1] ), |
.txd_load ( txd_load ), |
.txd_parity ( cntrl[0:0] )); |
wire xmit_data_wr; |
wire rcv_data_rd; |
io_uart_rxtx_mb |
/doc/Geda/src/io_module_def.v
37,13 → 37,13
module |
io_module_def |
#( parameter |
UART_PRESCALE=5'b01100, |
UART_PRE_SIZE=5, |
UART_DIV=0, |
ADDR_WIDTH=16, |
BASE_WIDTH=8, |
ADDR_WIDTH=16, |
IRQ_MODE=8'h00, |
NMI_MODE=8'h00, |
IRQ_MODE=8'h00) |
UART_DIV=0, |
UART_PRESCALE=5'b01100, |
UART_PRE_SIZE=5) |
( |
input wire clk, |
input wire cts_pad_in, |
59,8 → 59,8
input wire reg_mb_wr, |
input wire reset, |
input wire uart_rxd_pad_in, |
input wire [ 13 : 0] mem_addr, |
input wire [ 15 : 0] ext_rdata, |
input wire [ 15 : 0] mem_addr, |
input wire [ 15 : 0] mem_wdata, |
input wire [ 7 : 0] gpio_0_in, |
input wire [ 7 : 0] gpio_1_in, |
134,267 → 134,270
wire mas_8_cs; |
wire mas_8_rd; |
wire mas_8_wr; |
wire [ 7 : 0] mas_0_addr; |
wire [ 3 : 0] mas_0_addr; |
wire [ 3 : 0] mas_1_addr; |
wire [ 3 : 0] mas_2_addr; |
wire [ 3 : 0] mas_3_addr; |
wire [ 3 : 0] mas_4_addr; |
wire [ 3 : 0] mas_5_addr; |
wire [ 3 : 0] mas_6_addr; |
wire [ 3 : 0] mas_7_addr; |
wire [ 3 : 0] mas_8_addr; |
wire [ 7 : 0] mas_0_rdata; |
wire [ 7 : 0] mas_0_wdata; |
wire [ 7 : 0] mas_1_addr; |
wire [ 7 : 0] mas_1_rdata; |
wire [ 7 : 0] mas_1_wdata; |
wire [ 7 : 0] mas_2_addr; |
wire [ 7 : 0] mas_2_rdata; |
wire [ 7 : 0] mas_2_wdata; |
wire [ 7 : 0] mas_3_addr; |
wire [ 7 : 0] mas_3_rdata; |
wire [ 7 : 0] mas_3_wdata; |
wire [ 7 : 0] mas_4_addr; |
wire [ 7 : 0] mas_4_rdata; |
wire [ 7 : 0] mas_4_wdata; |
wire [ 7 : 0] mas_5_addr; |
wire [ 7 : 0] mas_5_rdata; |
wire [ 7 : 0] mas_5_wdata; |
wire [ 7 : 0] mas_6_addr; |
wire [ 7 : 0] mas_6_rdata; |
wire [ 7 : 0] mas_6_wdata; |
wire [ 7 : 0] mas_7_addr; |
wire [ 7 : 0] mas_7_rdata; |
wire [ 7 : 0] mas_7_wdata; |
wire [ 7 : 0] mas_8_addr; |
wire [ 7 : 0] mas_8_rdata; |
wire [ 7 : 0] mas_8_wdata; |
//////////////////////////////////////////////////////////////// |
micro_bus_exp9 |
mb_exp |
( |
.addr_in (reg_mb_addr[7:0]), |
.clk (clk), |
.cs_in (reg_mb_cs), |
.enable (enable), |
.mas_0_addr_out (mas_0_addr[7:0]), |
.mas_0_cs_out (mas_0_cs), |
.mas_0_rd_out (mas_0_rd), |
.mas_0_rdata_in (mas_0_rdata[7:0]), |
.mas_0_wdata_out (mas_0_wdata[7:0]), |
.mas_0_wr_out (mas_0_wr), |
.mas_1_addr_out (mas_1_addr[7:0]), |
.mas_1_cs_out (mas_1_cs), |
.mas_1_rd_out (mas_1_rd), |
.mas_1_rdata_in (mas_1_rdata[7:0]), |
.mas_1_wdata_out (mas_1_wdata[7:0]), |
.mas_1_wr_out (mas_1_wr), |
.mas_2_addr_out (mas_2_addr[7:0]), |
.mas_2_cs_out (mas_2_cs), |
.mas_2_rd_out (mas_2_rd), |
.mas_2_rdata_in (mas_2_rdata[7:0]), |
.mas_2_wdata_out (mas_2_wdata[7:0]), |
.mas_2_wr_out (mas_2_wr), |
.mas_3_addr_out (mas_3_addr[7:0]), |
.mas_3_cs_out (mas_3_cs), |
.mas_3_rd_out (mas_3_rd), |
.mas_3_rdata_in (mas_3_rdata[7:0]), |
.mas_3_wdata_out (mas_3_wdata[7:0]), |
.mas_3_wr_out (mas_3_wr), |
.mas_4_addr_out (mas_4_addr[7:0]), |
.mas_4_cs_out (mas_4_cs), |
.mas_4_rd_out (mas_4_rd), |
.mas_4_rdata_in (mas_4_rdata[7:0]), |
.mas_4_wdata_out (mas_4_wdata[7:0]), |
.mas_4_wr_out (mas_4_wr), |
.mas_5_addr_out (mas_5_addr[7:0]), |
.mas_5_cs_out (mas_5_cs), |
.mas_5_rd_out (mas_5_rd), |
.mas_5_rdata_in (mas_5_rdata[7:0]), |
.mas_5_wdata_out (mas_5_wdata[7:0]), |
.mas_5_wr_out (mas_5_wr), |
.mas_6_addr_out (mas_6_addr[7:0]), |
.mas_6_cs_out (mas_6_cs), |
.mas_6_rd_out (mas_6_rd), |
.mas_6_rdata_in (mas_6_rdata[7:0]), |
.mas_6_wdata_out (mas_6_wdata[7:0]), |
.mas_6_wr_out (mas_6_wr), |
.mas_7_addr_out (mas_7_addr[7:0]), |
.mas_7_cs_out (mas_7_cs), |
.mas_7_rd_out (mas_7_rd), |
.mas_7_rdata_in (mas_7_rdata[7:0]), |
.mas_7_wdata_out (mas_7_wdata[7:0]), |
.mas_7_wr_out (mas_7_wr), |
.mas_8_addr_out (mas_8_addr[7:0]), |
.mas_8_cs_out (mas_8_cs), |
.mas_8_rd_out (mas_8_rd), |
.mas_8_rdata_in (mas_8_rdata[7:0]), |
.mas_8_wdata_out (mas_8_wdata[7:0]), |
.mas_8_wr_out (mas_8_wr), |
.rd_in (reg_mb_rd), |
.rdata_out (reg_mb_rdata[15:0]), |
.reset (reset), |
.wait_out (reg_mb_wait), |
.wdata_in (reg_mb_wdata[7:0]), |
.wr_in (reg_mb_wr)); |
io_gpio_def |
gpio |
( |
.addr (mas_0_addr[3:0]), |
.clk (clk), |
.cs (mas_0_cs), |
.enable (enable), |
.gpio_0_in (gpio_0_in), |
.gpio_0_oe (gpio_0_oe), |
.gpio_0_out (gpio_0_out), |
.gpio_1_in (gpio_1_in), |
.gpio_1_oe (gpio_1_oe), |
.gpio_1_out (gpio_1_out), |
.rd (mas_0_rd), |
.rdata (mas_0_rdata[7:0]), |
.reset (reset), |
.wdata (mas_0_wdata[7:0]), |
.wr (mas_0_wr)); |
io_timer_def |
tim_0 |
.addr ( mas_0_addr[3:0] ), |
.cs ( mas_0_cs ), |
.rd ( mas_0_rd ), |
.rdata ( mas_0_rdata[7:0] ), |
.wdata ( mas_0_wdata[7:0] ), |
.wr ( mas_0_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.gpio_0_in ( gpio_0_in ), |
.gpio_0_oe ( gpio_0_oe ), |
.gpio_0_out ( gpio_0_out ), |
.gpio_1_in ( gpio_1_in ), |
.gpio_1_oe ( gpio_1_oe ), |
.gpio_1_out ( gpio_1_out ), |
.reset ( reset )); |
micro_bus_exp9 |
mb_exp |
( |
.addr (mas_1_addr[3:0]), |
.clk (clk), |
.cs (mas_1_cs), |
.enable (enable), |
.irq (timer_irq), |
.rd (mas_1_rd), |
.rdata (mas_1_rdata[7:0]), |
.reset (reset), |
.wdata (mas_1_wdata[7:0]), |
.wr (mas_1_wr)); |
io_uart_def |
#( .PRESCALE (UART_PRESCALE), |
.PRE_SIZE (UART_PRE_SIZE), |
.DIV (UART_DIV)) |
uart |
.addr_in ( reg_mb_addr[7:0] ), |
.cs_in ( reg_mb_cs ), |
.mas_0_addr_out ( mas_0_addr[3:0] ), |
.mas_0_cs_out ( mas_0_cs ), |
.mas_0_rd_out ( mas_0_rd ), |
.mas_0_rdata_in ( mas_0_rdata[7:0] ), |
.mas_0_wdata_out ( mas_0_wdata[7:0] ), |
.mas_0_wr_out ( mas_0_wr ), |
.mas_1_addr_out ( mas_1_addr[3:0] ), |
.mas_1_cs_out ( mas_1_cs ), |
.mas_1_rd_out ( mas_1_rd ), |
.mas_1_rdata_in ( mas_1_rdata[7:0] ), |
.mas_1_wdata_out ( mas_1_wdata[7:0] ), |
.mas_1_wr_out ( mas_1_wr ), |
.mas_2_addr_out ( mas_2_addr[3:0] ), |
.mas_2_cs_out ( mas_2_cs ), |
.mas_2_rd_out ( mas_2_rd ), |
.mas_2_rdata_in ( mas_2_rdata[7:0] ), |
.mas_2_wdata_out ( mas_2_wdata[7:0] ), |
.mas_2_wr_out ( mas_2_wr ), |
.mas_3_addr_out ( mas_3_addr[3:0] ), |
.mas_3_cs_out ( mas_3_cs ), |
.mas_3_rd_out ( mas_3_rd ), |
.mas_3_rdata_in ( mas_3_rdata[7:0] ), |
.mas_3_wdata_out ( mas_3_wdata[7:0] ), |
.mas_3_wr_out ( mas_3_wr ), |
.mas_4_addr_out ( mas_4_addr[3:0] ), |
.mas_4_cs_out ( mas_4_cs ), |
.mas_4_rd_out ( mas_4_rd ), |
.mas_4_rdata_in ( mas_4_rdata[7:0] ), |
.mas_4_wdata_out ( mas_4_wdata[7:0] ), |
.mas_4_wr_out ( mas_4_wr ), |
.mas_5_addr_out ( mas_5_addr[3:0] ), |
.mas_5_cs_out ( mas_5_cs ), |
.mas_5_rd_out ( mas_5_rd ), |
.mas_5_rdata_in ( mas_5_rdata[7:0] ), |
.mas_5_wdata_out ( mas_5_wdata[7:0] ), |
.mas_5_wr_out ( mas_5_wr ), |
.mas_6_addr_out ( mas_6_addr[3:0] ), |
.mas_6_cs_out ( mas_6_cs ), |
.mas_6_rd_out ( mas_6_rd ), |
.mas_6_rdata_in ( mas_6_rdata[7:0] ), |
.mas_6_wdata_out ( mas_6_wdata[7:0] ), |
.mas_6_wr_out ( mas_6_wr ), |
.mas_7_addr_out ( mas_7_addr[3:0] ), |
.mas_7_cs_out ( mas_7_cs ), |
.mas_7_rd_out ( mas_7_rd ), |
.mas_7_rdata_in ( mas_7_rdata[7:0] ), |
.mas_7_wdata_out ( mas_7_wdata[7:0] ), |
.mas_7_wr_out ( mas_7_wr ), |
.mas_8_addr_out ( mas_8_addr[3:0] ), |
.mas_8_cs_out ( mas_8_cs ), |
.mas_8_rd_out ( mas_8_rd ), |
.mas_8_rdata_in ( mas_8_rdata[7:0] ), |
.mas_8_wdata_out ( mas_8_wdata[7:0] ), |
.mas_8_wr_out ( mas_8_wr ), |
.rd_in ( reg_mb_rd ), |
.rdata_out ( reg_mb_rdata[15:0] ), |
.wait_out ( reg_mb_wait ), |
.wdata_in ( reg_mb_wdata[7:0] ), |
.wr_in ( reg_mb_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
io_ext_mem_interface_def |
#( .ADDR_WIDTH (8), |
.BASE_ADDR (4'h7), |
.BASE_WIDTH (4)) |
mem |
( |
.addr (mas_2_addr[3:0]), |
.clk (clk), |
.cs (mas_2_cs), |
.cts_pad_in (cts_pad_in), |
.enable (enable), |
.rd (mas_2_rd), |
.rdata (mas_2_rdata[7:0]), |
.reset (reset), |
.rts_pad_out (rts_pad_out), |
.rx_irq (rx_irq), |
.tx_irq (tx_irq), |
.uart_rxd_pad_in (uart_rxd_pad_in), |
.uart_txd_pad_out (uart_txd_pad_out), |
.wdata (mas_2_wdata[7:0]), |
.wr (mas_2_wr)); |
.addr ( mas_7_addr[3:0] ), |
.cs ( mas_7_cs ), |
.ext_add ( ext_addr[23:1] ), |
.ext_cs ( ext_cs[1:0] ), |
.ext_rd ( ext_rd ), |
.ext_rdata ( ext_rdata[15:0] ), |
.ext_wait ( ext_wait ), |
.ext_wdata ( ext_wdata[15:0] ), |
.ext_wr ( ext_wr ), |
.mem_addr ( mem_addr[13:0] ), |
.mem_cs ( mem_cs ), |
.mem_rd ( mem_rd ), |
.mem_rdata ( mem_rdata[15:0] ), |
.mem_wait ( mem_wait ), |
.mem_wdata ( mem_wdata[15:0] ), |
.mem_wr ( mem_wr ), |
.rd ( mas_7_rd ), |
.rdata ( mas_7_rdata[7:0] ), |
.wdata ( mas_7_wdata[7:0] ), |
.wr ( mas_7_wr ), |
.bank ( ), |
.clk ( clk ), |
.enable ( enable ), |
.ext_lb ( ext_lb ), |
.ext_stb ( ext_stb ), |
.ext_ub ( ext_ub ), |
.reset ( reset ), |
.wait_st ( )); |
io_pic_def |
#( .NMI_MODE (NMI_MODE), |
.IRQ_MODE (IRQ_MODE)) |
#( .IRQ_MODE (IRQ_MODE), |
.NMI_MODE (NMI_MODE)) |
pic |
( |
.addr (mas_3_addr[3:0]), |
.clk (clk), |
.cs (mas_3_cs), |
.enable (enable), |
.int_in (pic_irq_in), |
.irq_out (pic_irq), |
.nmi_out (pic_nmi), |
.rd (mas_3_rd), |
.rdata (mas_3_rdata[7:0]), |
.reset (reset), |
.wdata (mas_3_wdata[7:0]), |
.wr (mas_3_wr)); |
.addr ( mas_3_addr[3:0] ), |
.cs ( mas_3_cs ), |
.rd ( mas_3_rd ), |
.rdata ( mas_3_rdata[7:0] ), |
.wdata ( mas_3_wdata[7:0] ), |
.wr ( mas_3_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.int_in ( pic_irq_in ), |
.irq_out ( pic_irq ), |
.nmi_out ( pic_nmi ), |
.reset ( reset )); |
io_ps2_mouse |
ps2 |
( |
.addr (mas_4_addr[3:0]), |
.clk (clk), |
.cs (mas_4_cs), |
.enable (enable), |
.ms_left (ms_left), |
.ms_mid (ms_mid), |
.ms_right (ms_right), |
.new_packet (new_packet), |
.ps2_clk_pad_in (ps2_clk_pad_in), |
.ps2_clk_pad_oe (ps2_clk_pad_oe), |
.ps2_data_pad_in (ps2_data_pad_in), |
.ps2_data_pad_oe (ps2_data_pad_oe), |
.rcv_data_avail (ps2_data_avail), |
.rd (mas_4_rd), |
.rdata (mas_4_rdata[7:0]), |
.reset (reset), |
.wdata (mas_4_wdata[7:0]), |
.wr (mas_4_wr), |
.x_pos (x_pos), |
.y_pos (y_pos)); |
.addr ( mas_4_addr[3:0] ), |
.cs ( mas_4_cs ), |
.ps2_clk_pad_in ( ps2_clk_pad_in ), |
.ps2_clk_pad_oe ( ps2_clk_pad_oe ), |
.ps2_data_pad_in ( ps2_data_pad_in ), |
.ps2_data_pad_oe ( ps2_data_pad_oe ), |
.rd ( mas_4_rd ), |
.rdata ( mas_4_rdata[7:0] ), |
.wdata ( mas_4_wdata[7:0] ), |
.wr ( mas_4_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.ms_left ( ms_left ), |
.ms_mid ( ms_mid ), |
.ms_right ( ms_right ), |
.new_packet ( new_packet ), |
.rcv_data_avail ( ps2_data_avail ), |
.reset ( reset ), |
.x_pos ( x_pos ), |
.y_pos ( y_pos )); |
io_timer_def |
tim_0 |
( |
.addr ( mas_1_addr[3:0] ), |
.cs ( mas_1_cs ), |
.rd ( mas_1_rd ), |
.rdata ( mas_1_rdata[7:0] ), |
.wdata ( mas_1_wdata[7:0] ), |
.wr ( mas_1_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.irq ( timer_irq ), |
.reset ( reset )); |
io_uart_def |
#( .DIV (UART_DIV), |
.PRESCALE (UART_PRESCALE), |
.PRE_SIZE (UART_PRE_SIZE)) |
uart |
( |
.addr ( mas_2_addr[3:0] ), |
.cs ( mas_2_cs ), |
.rd ( mas_2_rd ), |
.rdata ( mas_2_rdata[7:0] ), |
.uart_rxd_pad_in ( uart_rxd_pad_in ), |
.uart_txd_pad_out ( uart_txd_pad_out ), |
.wdata ( mas_2_wdata[7:0] ), |
.wr ( mas_2_wr ), |
.clk ( clk ), |
.cts_pad_in ( cts_pad_in ), |
.enable ( enable ), |
.reset ( reset ), |
.rts_pad_out ( rts_pad_out ), |
.rx_irq ( rx_irq ), |
.rxd_data_avail_IRQ ( ), |
.tx_irq ( tx_irq ), |
.txd_buffer_empty_NIRQ ( )); |
io_utimer_def |
utimer |
( |
.addr (mas_5_addr[3:0]), |
.clk (clk), |
.cs (mas_5_cs), |
.enable (enable), |
.rd (mas_5_rd), |
.rdata (mas_5_rdata[7:0]), |
.reset (reset), |
.wdata (mas_5_wdata[7:0]), |
.wr (mas_5_wr)); |
.addr ( mas_5_addr[3:0] ), |
.cs ( mas_5_cs ), |
.rd ( mas_5_rd ), |
.rdata ( mas_5_rdata[7:0] ), |
.wdata ( mas_5_wdata[7:0] ), |
.wr ( mas_5_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
io_vga_def |
vga |
( |
.addr (mas_6_addr[3:0]), |
.clk (clk), |
.cs (mas_6_cs), |
.enable (enable), |
.rd (mas_6_rd), |
.rdata (mas_6_rdata[7:0]), |
.reset (reset), |
.vga_blue_pad_out (vga_blue_pad_out[1:0]), |
.vga_green_pad_out (vga_green_pad_out[2:0]), |
.vga_hsync_n_pad_out (vga_hsync_n_pad_out), |
.vga_red_pad_out (vga_red_pad_out[2:0]), |
.vga_vsync_n_pad_out (vga_vsync_n_pad_out), |
.wdata (mas_6_wdata[7:0]), |
.wr (mas_6_wr)); |
io_ext_mem_interface_def |
#( .BASE_ADDR (4'h7), |
.BASE_WIDTH (4), |
.ADDR_WIDTH (8)) |
mem |
( |
.addr (mas_7_addr[3:0]), |
.clk (clk), |
.cs (mas_7_cs), |
.enable (enable), |
.ext_add (ext_addr[23:1]), |
.ext_cs (ext_cs[1:0]), |
.ext_lb (ext_lb), |
.ext_rd (ext_rd), |
.ext_rdata (ext_rdata[15:0]), |
.ext_stb (ext_stb), |
.ext_ub (ext_ub), |
.ext_wait (ext_wait), |
.ext_wdata (ext_wdata[15:0]), |
.ext_wr (ext_wr), |
.mem_addr (mem_addr[15:0]), |
.mem_cs (mem_cs), |
.mem_rd (mem_rd), |
.mem_rdata (mem_rdata[15:0]), |
.mem_wait (mem_wait), |
.mem_wdata (mem_wdata[15:0]), |
.mem_wr (mem_wr), |
.rd (mas_7_rd), |
.rdata (mas_7_rdata[7:0]), |
.reset (reset), |
.wdata (mas_7_wdata[7:0]), |
.wr (mas_7_wr)); |
.addr ( mas_6_addr[3:0] ), |
.cs ( mas_6_cs ), |
.rd ( mas_6_rd ), |
.rdata ( mas_6_rdata[7:0] ), |
.vga_blue_pad_out ( vga_blue_pad_out[1:0] ), |
.vga_green_pad_out ( vga_green_pad_out[2:0] ), |
.vga_hsync_n_pad_out ( vga_hsync_n_pad_out ), |
.vga_red_pad_out ( vga_red_pad_out[2:0] ), |
.vga_vsync_n_pad_out ( vga_vsync_n_pad_out ), |
.wdata ( mas_6_wdata[7:0] ), |
.wr ( mas_6_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
io_vic_def |
vic |
( |
.addr (mas_8_addr[3:0]), |
.clk (clk), |
.cs (mas_8_cs), |
.enable (enable), |
.int_in (vic_irq_in), |
.irq_out (int_out), |
.rd (mas_8_rd), |
.rdata (mas_8_rdata[7:0]), |
.reset (reset), |
.vector (vector), |
.wdata (mas_8_wdata[7:0]), |
.wr (mas_8_wr)); |
.addr ( mas_8_addr[3:0] ), |
.cs ( mas_8_cs ), |
.rd ( mas_8_rd ), |
.rdata ( mas_8_rdata[7:0] ), |
.wdata ( mas_8_wdata[7:0] ), |
.wr ( mas_8_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.int_in ( vic_irq_in ), |
.irq_out ( int_out ), |
.reset ( reset ), |
.vector ( vector )); |
endmodule |
/doc/Geda/src/io_module_gpio.v
37,13 → 37,13
module |
io_module_gpio |
#( parameter |
UART_PRESCALE=5'b01100, |
UART_PRE_SIZE=5, |
UART_DIV=0, |
ADDR_WIDTH=16, |
BASE_WIDTH=8, |
ADDR_WIDTH=16, |
IRQ_MODE=8'h00, |
NMI_MODE=8'h00, |
IRQ_MODE=8'h00) |
UART_DIV=0, |
UART_PRESCALE=5'b01100, |
UART_PRE_SIZE=5) |
( |
input wire clk, |
input wire cts_pad_in, |
87,146 → 87,147
wire mas_4_cs; |
wire mas_4_rd; |
wire mas_4_wr; |
wire [ 7 : 0] mas_0_addr; |
wire [ 3 : 0] mas_0_addr; |
wire [ 3 : 0] mas_1_addr; |
wire [ 3 : 0] mas_2_addr; |
wire [ 3 : 0] mas_3_addr; |
wire [ 3 : 0] mas_4_addr; |
wire [ 7 : 0] mas_0_rdata; |
wire [ 7 : 0] mas_0_wdata; |
wire [ 7 : 0] mas_1_addr; |
wire [ 7 : 0] mas_1_rdata; |
wire [ 7 : 0] mas_1_wdata; |
wire [ 7 : 0] mas_2_addr; |
wire [ 7 : 0] mas_2_rdata; |
wire [ 7 : 0] mas_2_wdata; |
wire [ 7 : 0] mas_3_addr; |
wire [ 7 : 0] mas_3_rdata; |
wire [ 7 : 0] mas_3_wdata; |
wire [ 7 : 0] mas_4_addr; |
wire [ 7 : 0] mas_4_rdata; |
wire [ 7 : 0] mas_4_wdata; |
//////////////////////////////////////////////////////////////// |
io_gpio_def |
gpio |
( |
.addr ( mas_0_addr[3:0] ), |
.cs ( mas_0_cs ), |
.rd ( mas_0_rd ), |
.rdata ( mas_0_rdata[7:0] ), |
.wdata ( mas_0_wdata[7:0] ), |
.wr ( mas_0_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.gpio_0_in ( gpio_0_in ), |
.gpio_0_oe ( gpio_0_oe ), |
.gpio_0_out ( gpio_0_out ), |
.gpio_1_in ( gpio_1_in ), |
.gpio_1_oe ( gpio_1_oe ), |
.gpio_1_out ( gpio_1_out ), |
.reset ( reset )); |
micro_bus_exp5 |
mb_exp |
( |
.addr_in (reg_mb_addr[7:0]), |
.clk (clk), |
.cs_in (reg_mb_cs), |
.enable (enable), |
.mas_0_addr_out (mas_0_addr[7:0]), |
.mas_0_cs_out (mas_0_cs), |
.mas_0_rd_out (mas_0_rd), |
.mas_0_rdata_in (mas_0_rdata[7:0]), |
.mas_0_wdata_out (mas_0_wdata[7:0]), |
.mas_0_wr_out (mas_0_wr), |
.mas_1_addr_out (mas_1_addr[7:0]), |
.mas_1_cs_out (mas_1_cs), |
.mas_1_rd_out (mas_1_rd), |
.mas_1_rdata_in (mas_1_rdata[7:0]), |
.mas_1_wdata_out (mas_1_wdata[7:0]), |
.mas_1_wr_out (mas_1_wr), |
.mas_2_addr_out (mas_2_addr[7:0]), |
.mas_2_cs_out (mas_2_cs), |
.mas_2_rd_out (mas_2_rd), |
.mas_2_rdata_in (mas_2_rdata[7:0]), |
.mas_2_wdata_out (mas_2_wdata[7:0]), |
.mas_2_wr_out (mas_2_wr), |
.mas_3_addr_out (mas_3_addr[7:0]), |
.mas_3_cs_out (mas_3_cs), |
.mas_3_rd_out (mas_3_rd), |
.mas_3_rdata_in (mas_3_rdata[7:0]), |
.mas_3_wdata_out (mas_3_wdata[7:0]), |
.mas_3_wr_out (mas_3_wr), |
.mas_4_addr_out (mas_4_addr[7:0]), |
.mas_4_cs_out (mas_4_cs), |
.mas_4_rd_out (mas_4_rd), |
.mas_4_rdata_in (mas_4_rdata[7:0]), |
.mas_4_wdata_out (mas_4_wdata[7:0]), |
.mas_4_wr_out (mas_4_wr), |
.rd_in (reg_mb_rd), |
.rdata_out (reg_mb_rdata[15:0]), |
.reset (reset), |
.wait_out (reg_mb_wait), |
.wdata_in (reg_mb_wdata[7:0]), |
.wr_in (reg_mb_wr)); |
io_gpio_def |
gpio |
.addr_in ( reg_mb_addr[7:0] ), |
.cs_in ( reg_mb_cs ), |
.mas_0_addr_out ( mas_0_addr[3:0] ), |
.mas_0_cs_out ( mas_0_cs ), |
.mas_0_rd_out ( mas_0_rd ), |
.mas_0_rdata_in ( mas_0_rdata[7:0] ), |
.mas_0_wdata_out ( mas_0_wdata[7:0] ), |
.mas_0_wr_out ( mas_0_wr ), |
.mas_1_addr_out ( mas_1_addr[3:0] ), |
.mas_1_cs_out ( mas_1_cs ), |
.mas_1_rd_out ( mas_1_rd ), |
.mas_1_rdata_in ( mas_1_rdata[7:0] ), |
.mas_1_wdata_out ( mas_1_wdata[7:0] ), |
.mas_1_wr_out ( mas_1_wr ), |
.mas_2_addr_out ( mas_2_addr[3:0] ), |
.mas_2_cs_out ( mas_2_cs ), |
.mas_2_rd_out ( mas_2_rd ), |
.mas_2_rdata_in ( mas_2_rdata[7:0] ), |
.mas_2_wdata_out ( mas_2_wdata[7:0] ), |
.mas_2_wr_out ( mas_2_wr ), |
.mas_3_addr_out ( mas_3_addr[3:0] ), |
.mas_3_cs_out ( mas_3_cs ), |
.mas_3_rd_out ( mas_3_rd ), |
.mas_3_rdata_in ( mas_3_rdata[7:0] ), |
.mas_3_wdata_out ( mas_3_wdata[7:0] ), |
.mas_3_wr_out ( mas_3_wr ), |
.mas_4_addr_out ( mas_4_addr[3:0] ), |
.mas_4_cs_out ( mas_4_cs ), |
.mas_4_rd_out ( mas_4_rd ), |
.mas_4_rdata_in ( mas_4_rdata[7:0] ), |
.mas_4_wdata_out ( mas_4_wdata[7:0] ), |
.mas_4_wr_out ( mas_4_wr ), |
.rd_in ( reg_mb_rd ), |
.rdata_out ( reg_mb_rdata[15:0] ), |
.wait_out ( reg_mb_wait ), |
.wdata_in ( reg_mb_wdata[7:0] ), |
.wr_in ( reg_mb_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
io_pic_def |
#( .IRQ_MODE (IRQ_MODE), |
.NMI_MODE (NMI_MODE)) |
pic |
( |
.addr (mas_0_addr[3:0]), |
.clk (clk), |
.cs (mas_0_cs), |
.enable (enable), |
.gpio_0_in (gpio_0_in), |
.gpio_0_oe (gpio_0_oe), |
.gpio_0_out (gpio_0_out), |
.gpio_1_in (gpio_1_in), |
.gpio_1_oe (gpio_1_oe), |
.gpio_1_out (gpio_1_out), |
.rd (mas_0_rd), |
.rdata (mas_0_rdata[7:0]), |
.reset (reset), |
.wdata (mas_0_wdata[7:0]), |
.wr (mas_0_wr)); |
.addr ( mas_3_addr[3:0] ), |
.cs ( mas_3_cs ), |
.rd ( mas_3_rd ), |
.rdata ( mas_3_rdata[7:0] ), |
.wdata ( mas_3_wdata[7:0] ), |
.wr ( mas_3_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.int_in ( pic_irq_in ), |
.irq_out ( pic_irq ), |
.nmi_out ( pic_nmi ), |
.reset ( reset )); |
io_timer_def |
tim_0 |
( |
.addr (mas_1_addr[3:0]), |
.clk (clk), |
.cs (mas_1_cs), |
.enable (enable), |
.irq (timer_irq), |
.rd (mas_1_rd), |
.rdata (mas_1_rdata[7:0]), |
.reset (reset), |
.wdata (mas_1_wdata[7:0]), |
.wr (mas_1_wr)); |
.addr ( mas_1_addr[3:0] ), |
.cs ( mas_1_cs ), |
.rd ( mas_1_rd ), |
.rdata ( mas_1_rdata[7:0] ), |
.wdata ( mas_1_wdata[7:0] ), |
.wr ( mas_1_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.irq ( timer_irq ), |
.reset ( reset )); |
io_uart_def |
#( .PRESCALE (UART_PRESCALE), |
.PRE_SIZE (UART_PRE_SIZE), |
.DIV (UART_DIV)) |
#( .DIV (UART_DIV), |
.PRESCALE (UART_PRESCALE), |
.PRE_SIZE (UART_PRE_SIZE)) |
uart |
( |
.addr (mas_2_addr[3:0]), |
.clk (clk), |
.cs (mas_2_cs), |
.cts_pad_in (cts_pad_in), |
.enable (enable), |
.rd (mas_2_rd), |
.rdata (mas_2_rdata[7:0]), |
.reset (reset), |
.rts_pad_out (rts_pad_out), |
.rx_irq (rx_irq), |
.tx_irq (tx_irq), |
.uart_rxd_pad_in (uart_rxd_pad_in), |
.uart_txd_pad_out (uart_txd_pad_out), |
.wdata (mas_2_wdata[7:0]), |
.wr (mas_2_wr)); |
io_pic_def |
#( .NMI_MODE (NMI_MODE), |
.IRQ_MODE (IRQ_MODE)) |
pic |
( |
.addr (mas_3_addr[3:0]), |
.clk (clk), |
.cs (mas_3_cs), |
.enable (enable), |
.int_in (pic_irq_in), |
.irq_out (pic_irq), |
.nmi_out (pic_nmi), |
.rd (mas_3_rd), |
.rdata (mas_3_rdata[7:0]), |
.reset (reset), |
.wdata (mas_3_wdata[7:0]), |
.wr (mas_3_wr)); |
.addr ( mas_2_addr[3:0] ), |
.cs ( mas_2_cs ), |
.rd ( mas_2_rd ), |
.rdata ( mas_2_rdata[7:0] ), |
.uart_rxd_pad_in ( uart_rxd_pad_in ), |
.uart_txd_pad_out ( uart_txd_pad_out ), |
.wdata ( mas_2_wdata[7:0] ), |
.wr ( mas_2_wr ), |
.clk ( clk ), |
.cts_pad_in ( cts_pad_in ), |
.enable ( enable ), |
.reset ( reset ), |
.rts_pad_out ( rts_pad_out ), |
.rx_irq ( rx_irq ), |
.rxd_data_avail_IRQ ( ), |
.tx_irq ( tx_irq ), |
.txd_buffer_empty_NIRQ ( )); |
io_utimer_def |
utimer |
( |
.addr (mas_4_addr[3:0]), |
.clk (clk), |
.cs (mas_4_cs), |
.enable (enable), |
.rd (mas_4_rd), |
.rdata (mas_4_rdata[7:0]), |
.reset (reset), |
.wdata (mas_4_wdata[7:0]), |
.wr (mas_4_wr)); |
.addr ( mas_4_addr[3:0] ), |
.cs ( mas_4_cs ), |
.rd ( mas_4_rd ), |
.rdata ( mas_4_rdata[7:0] ), |
.wdata ( mas_4_wdata[7:0] ), |
.wr ( mas_4_wr ), |
.clk ( clk ), |
.enable ( enable ), |
.reset ( reset )); |
reg wait_n_reg; |
always@(posedge clk) |
if(reset || enable) |
/doc/Geda/src/io_gpio_def.v
52,7 → 52,6
output wire [ 7 : 0] gpio_1_oe, |
output wire [ 7 : 0] gpio_1_out, |
output wire [ 7 : 0] rdata); |
//////////////////////////////////////////////////////////////// |
io_gpio_def_mb |
gpio_micro_reg |
( |
/doc/Geda/src/io_ps2_mouse.v
79,31 → 79,30
wire [ 7 : 0] rcv_data; |
wire [ 7 : 0] status; |
wire [ 7 : 0] wdata_buf; |
//////////////////////////////////////////////////////////////// |
ps2_interface_def |
#( .CLK_HOLD_DELAY (1), |
.DATA_SETUP_DELAY (14)) |
ps2 |
( |
.busy (busy), |
.clk (clk), |
.ps2_clk_pad_in (ps2_clk_pad_in), |
.ps2_clk_pad_oe (ps2_clk_pad_oe), |
.ps2_data_pad_in (ps2_data_pad_in), |
.ps2_data_pad_oe (ps2_data_pad_oe), |
.reset (reset), |
.rx_clear (ps2_rx_clear), |
.rx_data (rcv_data), |
.rx_frame_error (rx_frame_error), |
.rx_full (rcv_data_avail), |
.rx_parity_cal (rx_parity_cal), |
.rx_parity_error (rx_parity_error), |
.rx_parity_rcv (rx_parity_rcv), |
.rx_read (read), |
.tx_ack_error (tx_ack_error), |
.tx_buffer_empty (buffer_empty), |
.tx_data (wdata_buf), |
.tx_write (cntrl[1])); |
.ps2_clk_pad_in ( ps2_clk_pad_in ), |
.ps2_clk_pad_oe ( ps2_clk_pad_oe ), |
.ps2_data_pad_in ( ps2_data_pad_in ), |
.ps2_data_pad_oe ( ps2_data_pad_oe ), |
.busy ( busy ), |
.clk ( clk ), |
.reset ( reset ), |
.rx_clear ( ps2_rx_clear ), |
.rx_data ( rcv_data ), |
.rx_frame_error ( rx_frame_error ), |
.rx_full ( rcv_data_avail ), |
.rx_parity_cal ( rx_parity_cal ), |
.rx_parity_error ( rx_parity_error ), |
.rx_parity_rcv ( rx_parity_rcv ), |
.rx_read ( read ), |
.tx_ack_error ( tx_ack_error ), |
.tx_buffer_empty ( buffer_empty ), |
.tx_data ( wdata_buf ), |
.tx_write ( cntrl[1:1] )); |
parameter PS2_DATA = 4'h0; |
parameter STATUS = 4'h2; |
parameter CNTRL = 4'h4; |
/doc/Geda/src/io_ps2_def.v
67,31 → 67,30
wire [ 7 : 0] rcv_data; |
wire [ 7 : 0] status; |
wire [ 7 : 0] wdata_buf; |
//////////////////////////////////////////////////////////////// |
ps2_interface_def |
#( .CLK_HOLD_DELAY (1), |
.DATA_SETUP_DELAY (14)) |
ps2 |
( |
.busy (busy), |
.clk (clk), |
.ps2_clk_pad_in (ps2_clk_pad_in), |
.ps2_clk_pad_oe (ps2_clk_pad_oe), |
.ps2_data_pad_in (ps2_data_pad_in), |
.ps2_data_pad_oe (ps2_data_pad_oe), |
.reset (reset), |
.rx_clear (ps2_rx_clear), |
.rx_data (rcv_data), |
.rx_frame_error (rx_frame_error), |
.rx_full (rcv_data_avail), |
.rx_parity_cal (rx_parity_cal), |
.rx_parity_error (rx_parity_error), |
.rx_parity_rcv (rx_parity_rcv), |
.rx_read (read), |
.tx_ack_error (tx_ack_error), |
.tx_buffer_empty (buffer_empty), |
.tx_data (wdata_buf), |
.tx_write (cntrl[1])); |
.ps2_clk_pad_in ( ps2_clk_pad_in ), |
.ps2_clk_pad_oe ( ps2_clk_pad_oe ), |
.ps2_data_pad_in ( ps2_data_pad_in ), |
.ps2_data_pad_oe ( ps2_data_pad_oe ), |
.busy ( busy ), |
.clk ( clk ), |
.reset ( reset ), |
.rx_clear ( ps2_rx_clear ), |
.rx_data ( rcv_data ), |
.rx_frame_error ( rx_frame_error ), |
.rx_full ( rcv_data_avail ), |
.rx_parity_cal ( rx_parity_cal ), |
.rx_parity_error ( rx_parity_error ), |
.rx_parity_rcv ( rx_parity_rcv ), |
.rx_read ( read ), |
.tx_ack_error ( tx_ack_error ), |
.tx_buffer_empty ( buffer_empty ), |
.tx_data ( wdata_buf ), |
.tx_write ( cntrl[1:1] )); |
parameter PS2_DATA = 4'h0; |
parameter STATUS = 4'h2; |
parameter CNTRL = 4'h4; |
/doc/Geda/src/io_utimer_def.v
48,7 → 48,6
input wire [ 3 : 0] addr, |
input wire [ 7 : 0] wdata, |
output wire [ 7 : 0] rdata); |
//////////////////////////////////////////////////////////////// |
parameter TIMER_LATCH = 4'h0; |
parameter TIMER_COUNT = 4'h2; |
wire [7:0] count; |
/doc/Geda/sym/io_ext_mem_interface_def.sym
21,7 → 21,7
P 300 600 0 600 10 1 1 |
{ |
T 400 600 5 10 1 1 0 1 1 1 |
pinnumber=mem_addr[15:0] |
pinnumber=mem_addr[13:0] |
T 400 600 5 10 0 1 0 1 1 1 |
pinseq=3 |
} |
/doc/Geda/sym/io_module_def.sym
42,7 → 42,7
P 300 1200 0 1200 10 1 1 |
{ |
T 400 1200 5 10 1 1 0 1 1 1 |
pinnumber=mem_addr[15:0] |
pinnumber=mem_addr[13:0] |
T 400 1200 5 10 0 1 0 1 1 1 |
pinseq=6 |
} |
/doc/Geda/sch/io_ext_mem_interface_def.sch
12,7 → 12,7
C 1700 1100 1 0 0 in_port_v.sym |
{ |
T 1700 1100 5 10 1 1 0 6 1 1 |
refdes=mem_addr[15:0] |
refdes=mem_addr[13:0] |
} |
C 1700 1500 1 0 0 in_port_v.sym |
{ |
/doc/Geda/sch/io_module_def.sch
27,7 → 27,7
C 1900 2300 1 0 0 in_port_v.sym |
{ |
T 1900 2300 5 10 1 1 0 6 1 1 |
refdes=mem_addr[15:0] |
refdes=mem_addr[13:0] |
} |
C 1900 2700 1 0 0 in_port_v.sym |
{ |
/ip/io_pic/rtl/xml/io_pic_def.xml
142,14 → 142,26
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
/ip/io_pic/sim/testbenches/xml/io_pic_def_lint.xml
39,9 → 39,46
<spirit:name>io_pic</spirit:name> |
<spirit:version>def_lint</spirit:version> |
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
|
|
/ip/io_pic/sim/testbenches/xml/io_pic_def_duth.design.xml
0,0 → 1,104
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_pic -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_pic</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>int_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="int_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>irq_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="irq_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="irq_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>nmi_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="nmi_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="nmi_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_pic" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_pic/sim/testbenches/xml/io_pic_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_pic" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_uart/rtl/xml/io_uart_def.xml
137,12 → 137,26
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
/ip/io_uart/rtl/xml/io_uart_rxtx.xml
137,12 → 137,26
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
167,7 → 181,7
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>top.rxtx</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
207,7 → 221,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top</spirit:name> |
<spirit:name>../verilog/common/top.rxtx</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/ip/io_uart/rtl/xml/io_uart_rx.xml
137,12 → 137,28
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
167,7 → 183,7
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>top.rx</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
208,7 → 224,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top</spirit:name> |
<spirit:name>../verilog/common/top.rx</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/ip/io_uart/rtl/xml/io_uart_tx.xml
137,12 → 137,27
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
167,7 → 182,7
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>top.tx</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
208,7 → 223,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top</spirit:name> |
<spirit:name>../verilog/common/top.tx</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/ip/io_uart/sim/testbenches/xml/io_uart_rxtx_duth.design.xml
0,0 → 1,134
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version rxtx // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_uart</spirit:name> |
<spirit:version>rxtx_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_data_avail_IRQ</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_data_avail_IRQ" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rxd_data_avail_IRQ" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>txd_buffer_empty_NIRQ</spirit:name> |
<spirit:externalPortReference spirit:portRef="txd_buffer_empty_NIRQ" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="txd_buffer_empty_NIRQ" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="rxtx" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_uart/sim/testbenches/xml/io_uart_rxtx_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_uart" |
spirit:version="rxtx_dutg.design"/> |
spirit:version="rxtx_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_uart/sim/testbenches/xml/io_uart_rx_lint.xml
40,11 → 40,48
<spirit:version>rx_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
/ip/io_uart/sim/testbenches/xml/io_uart_tx_lint.xml
41,10 → 41,47
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BUS_ADDR_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
/ip/io_uart/sim/testbenches/xml/io_uart_def_lint.xml
40,12 → 40,49
<spirit:version>def_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:model> |
|
<spirit:modelParameters> |
/ip/io_uart/sim/testbenches/xml/io_uart_rx_duth.design.xml
0,0 → 1,122
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version rx // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_uart</spirit:name> |
<spirit:version>rx_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="rx" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_uart/sim/testbenches/xml/io_uart_tx_duth.design.xml
0,0 → 1,122
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version tx // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_uart</spirit:name> |
<spirit:version>tx_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="tx" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_uart/sim/testbenches/xml/io_uart_rx_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_uart" |
spirit:version="rx_dutg.design"/> |
spirit:version="rx_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_uart/sim/testbenches/xml/io_uart_tx_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_uart" |
spirit:version="tx_dutg.design"/> |
spirit:version="tx_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_uart/sim/testbenches/xml/io_uart_def_duth.design.xml
0,0 → 1,134
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_uart</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_data_avail_IRQ</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_data_avail_IRQ" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rxd_data_avail_IRQ" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>txd_buffer_empty_NIRQ</spirit:name> |
<spirit:externalPortReference spirit:portRef="txd_buffer_empty_NIRQ" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="txd_buffer_empty_NIRQ" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_uart" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_uart/sim/testbenches/xml/io_uart_rxtx_lint.xml
40,10 → 40,47
<spirit:version>rxtx_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
|
|
/ip/io_uart/sim/testbenches/xml/io_uart_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_uart" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_vga/rtl/xml/io_vga_def.xml
135,14 → 135,28
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
/ip/io_vga/sim/testbenches/xml/io_vga_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_vga" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_vga/sim/testbenches/xml/io_vga_def_lint.xml
41,11 → 41,48
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
<spirit:views> |
/ip/io_vga/sim/testbenches/xml/io_vga_def_duth.design.xml
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_vga -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_vga</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_blue_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_blue_pad_out" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_blue_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_green_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_green_pad_out" spirit:left="2" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_green_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_hsync_n_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_hsync_n_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_hsync_n_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_red_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_red_pad_out" spirit:left="2" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_red_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_vsync_n_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_vsync_n_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_vsync_n_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_vga" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_ext_mem_interface/componentCfg.xml
25,10 → 25,23
</socgen:doc> |
|
|
<socgen:configurations> |
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:parameters> |
<socgen:parameter><socgen:name>BASE_ADDR</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>BASE_WIDTH</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>ADDR_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>MEM_WIDTH</socgen:name><socgen:value>23</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>MEM_FRAME</socgen:name><socgen:value>10</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
</socgen:configurations> |
|
|
|
<socgen:sim> |
|
|
/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml
149,7 → 149,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mem_addr</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>13</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
302,13 → 302,33
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
501,13 → 521,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BASE_ADDR</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MEM_WIDTH</spirit:name><spirit:value>23</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MEM_FRAME</spirit:name><spirit:value>10</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_ext_mem_interface" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_lint.xml
42,10 → 42,47
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
|
<spirit:views> |
/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_duth.design.xml
0,0 → 1,200
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_ext_mem_interface -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_ext_mem_interface</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>bank</spirit:name> |
<spirit:externalPortReference spirit:portRef="bank" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bank" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_add</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_add" spirit:left="23" spirit:right="1" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_add" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_cs" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_lb</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_lb" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_lb" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_stb</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_stb" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_stb" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_ub</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_ub" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_ub" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_addr" spirit:left="13" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wait_st</spirit:name> |
<spirit:externalPortReference spirit:portRef="wait_st" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wait_st" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_ext_mem_interface" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_gpio/rtl/xml/io_gpio_def.xml
145,7 → 145,7
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
161,7 → 161,26
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
238,15 → 257,8
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_gpio" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
/ip/io_gpio/sim/testbenches/xml/io_gpio_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_gpio" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_gpio/sim/testbenches/xml/io_gpio_def_lint.xml
40,10 → 40,47
<spirit:version>def_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
|
|
/ip/io_gpio/sim/testbenches/xml/io_gpio_def_duth.design.xml
0,0 → 1,122
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_gpio -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_gpio</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_gpio" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_timer/rtl/xml/io_timer_def.xml
138,11 → 138,27
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
243,14 → 259,6
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_timer" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
/ip/io_timer/sim/testbenches/xml/io_timer_def_duth.design.xml
0,0 → 1,93
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_timer -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_timer</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="irq" spirit:left="TIMERS-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_timer" spirit:version="def" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="TIMERS">TIMERS</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_timer/sim/testbenches/xml/io_timer_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_timer" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_timer/sim/testbenches/xml/io_timer_def_lint.xml
41,9 → 41,46
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
|
|
/ip/io_vic/rtl/xml/io_vic_def.xml
135,12 → 135,28
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
/ip/io_vic/sim/testbenches/xml/io_vic_def_duth.design.xml
0,0 → 1,104
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_vic -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_vic</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>int_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="int_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>irq_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="irq_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="irq_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vector</spirit:name> |
<spirit:externalPortReference spirit:portRef="vector" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vector" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_vic" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_vic/sim/testbenches/xml/io_vic_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_vic" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_vic/sim/testbenches/xml/io_vic_def_lint.xml
42,11 → 42,48
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
<spirit:views> |
/ip/io_ps2/rtl/xml/io_ps2_mouse.xml
136,13 → 136,28
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
/ip/io_ps2/rtl/xml/io_ps2_def.xml
136,6 → 136,19
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
142,7 → 155,7
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
/ip/io_ps2/sim/testbenches/xml/io_ps2_mouse_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_ps2" |
spirit:version="mouse_dutg.design"/> |
spirit:version="mouse_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_ps2/sim/testbenches/xml/io_ps2_def_duth.design.xml
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_ps2 -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_ps2</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rcv_data_avail</spirit:name> |
<spirit:externalPortReference spirit:portRef="rcv_data_avail" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rcv_data_avail" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_ps2" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_ps2/sim/testbenches/xml/io_ps2_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_ps2" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
/ip/io_ps2/sim/testbenches/xml/io_ps2_mouse_tb.xml
46,36 → 46,9
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>trace_bus</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>path</spirit:name> |
<spirit:value>root.dut</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>bus_name</spirit:name> |
<spirit:value>mb</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
84,7 → 57,7
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
<spirit:value>top.mouse.tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
221,7 → 194,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/top.mouse.tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
236,7 → 209,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/top.mouse.tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/ip/io_ps2/sim/testbenches/xml/io_ps2_mouse_lint.xml
41,10 → 41,47
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
|
|
/ip/io_ps2/sim/testbenches/xml/io_ps2_def_tb.xml
48,39 → 48,8
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>trace_bus</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>path</spirit:name> |
<spirit:value>root.dut</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>bus_name</spirit:name> |
<spirit:value>mb</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
/ip/io_ps2/sim/testbenches/xml/io_ps2_def_lint.xml
42,12 → 42,49
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:model> |
|
|
/ip/io_ps2/sim/testbenches/xml/io_ps2_mouse_duth.design.xml
0,0 → 1,152
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_ps2 -version mouse // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_ps2</spirit:name> |
<spirit:version>mouse_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_left</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_left" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_left" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_mid</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_mid" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_mid" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_right</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_right" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_right" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>new_packet</spirit:name> |
<spirit:externalPortReference spirit:portRef="new_packet" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="new_packet" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rcv_data_avail</spirit:name> |
<spirit:externalPortReference spirit:portRef="rcv_data_avail" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rcv_data_avail" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>x_pos</spirit:name> |
<spirit:externalPortReference spirit:portRef="x_pos" spirit:left="9" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="x_pos" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>y_pos</spirit:name> |
<spirit:externalPortReference spirit:portRef="y_pos" spirit:left="9" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="y_pos" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_ps2" spirit:version="mouse" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_module/componentCfg.xml
54,7 → 54,32
|
|
|
<socgen:configurations> |
|
|
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:parameters> |
<socgen:parameter><socgen:name>UART_PRESCALE</socgen:name><socgen:value>5'b01100</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>UART_PRE_SIZE</socgen:name><socgen:value>5</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>UART_DIV</socgen:name><socgen:value>0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>BASE_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>ADDR_WIDTH</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>NMI_MODE</socgen:name><socgen:value>8'h00</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>IRQ_MODE</socgen:name><socgen:value>8'h00</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
</socgen:configurations> |
|
|
|
|
|
|
<socgen:sim> |
|
|
/ip/io_module/rtl/xml/io_module_mouse.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
73,12 → 73,30
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
255,19 → 273,9
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
|
</spirit:modelParameters> |
|
|
|
<spirit:ports> |
|
|
/ip/io_module/rtl/xml/io_module_def.xml
86,11 → 86,30
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
267,16 → 286,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
/ip/io_module/rtl/xml/io_module_gpio.xml
73,11 → 73,30
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
256,21 → 275,10
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
|
</spirit:modelParameters> |
|
|
|
|
|
<spirit:ports> |
|
|
/ip/io_module/sim/testbenches/xml/io_module_mouse_duth.design.xml
0,0 → 1,267
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_module -version mouse // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_module</spirit:name> |
<spirit:version>mouse_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_left</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_left" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_left" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_mid</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_mid" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_mid" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_right</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_right" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_right" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>new_packet</spirit:name> |
<spirit:externalPortReference spirit:portRef="new_packet" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="new_packet" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_irq_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_irq_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_nmi</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_nmi" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_nmi" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_avail</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_avail" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_avail" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_addr" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>timer_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="timer_irq" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="timer_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wait_n</spirit:name> |
<spirit:externalPortReference spirit:portRef="wait_n" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wait_n" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>x_pos</spirit:name> |
<spirit:externalPortReference spirit:portRef="x_pos" spirit:left="9" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="x_pos" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>y_pos</spirit:name> |
<spirit:externalPortReference spirit:portRef="y_pos" spirit:left="9" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="y_pos" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_module" spirit:version="mouse" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="ADDR_WIDTH">ADDR_WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="BASE_WIDTH">BASE_WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="IRQ_MODE">IRQ_MODE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="NMI_MODE">NMI_MODE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_DIV">UART_DIV</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_PRESCALE">UART_PRESCALE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_PRE_SIZE">UART_PRE_SIZE</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_module/sim/testbenches/xml/io_module_def_lint.xml
39,8 → 39,45
<spirit:name>io_module</spirit:name> |
<spirit:version>def_lint</spirit:version> |
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
<spirit:model> |
|
|
/ip/io_module/sim/testbenches/xml/io_module_gpio_lint.xml
40,11 → 40,48
<spirit:version>gpio_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
|
/ip/io_module/sim/testbenches/xml/io_module_mouse_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,17 → 26,8
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_module" |
spirit:version="mouse_dutg.design"/> |
spirit:version="mouse_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
</spirit:model> |
</spirit:component> |
/ip/io_module/sim/testbenches/xml/io_module_def_duth.design.xml
0,0 → 1,404
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_module -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_module</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_addr" spirit:left="23" spirit:right="1" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_cs" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_lb</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_lb" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_lb" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_stb</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_stb" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_stb" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_ub</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_ub" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_ub" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>int_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="int_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_addr" spirit:left="13" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_left</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_left" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_left" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_mid</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_mid" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_mid" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ms_right</spirit:name> |
<spirit:externalPortReference spirit:portRef="ms_right" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ms_right" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>new_packet</spirit:name> |
<spirit:externalPortReference spirit:portRef="new_packet" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="new_packet" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_irq_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_irq_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_nmi</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_nmi" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_nmi" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_clk_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_clk_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_clk_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_avail</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_avail" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_avail" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ps2_data_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="ps2_data_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ps2_data_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_addr" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>timer_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="timer_irq" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="timer_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vector</spirit:name> |
<spirit:externalPortReference spirit:portRef="vector" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vector" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_blue_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_blue_pad_out" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_blue_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_green_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_green_pad_out" spirit:left="2" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_green_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_hsync_n_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_hsync_n_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_hsync_n_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_red_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_red_pad_out" spirit:left="2" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_red_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vga_vsync_n_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="vga_vsync_n_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vga_vsync_n_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>vic_irq_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="vic_irq_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="vic_irq_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>x_pos</spirit:name> |
<spirit:externalPortReference spirit:portRef="x_pos" spirit:left="9" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="x_pos" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>y_pos</spirit:name> |
<spirit:externalPortReference spirit:portRef="y_pos" spirit:left="9" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="y_pos" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_module" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_module/sim/testbenches/xml/io_module_gpio_duth.design.xml
0,0 → 1,201
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_module -version gpio // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_module</spirit:name> |
<spirit:version>gpio_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cts_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="cts_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_0_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_0_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_0_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_oe" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>gpio_1_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="gpio_1_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="gpio_1_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_irq_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_irq_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_irq_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pic_nmi</spirit:name> |
<spirit:externalPortReference spirit:portRef="pic_nmi" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pic_nmi" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_addr" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reg_mb_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="reg_mb_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reg_mb_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rts_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rts_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>timer_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="timer_irq" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="timer_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_irq</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_irq" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tx_irq" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_rxd_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_rxd_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_rxd_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>uart_txd_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="uart_txd_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="uart_txd_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wait_n</spirit:name> |
<spirit:externalPortReference spirit:portRef="wait_n" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wait_n" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_module" spirit:version="gpio" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="ADDR_WIDTH">ADDR_WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="BASE_WIDTH">BASE_WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="IRQ_MODE">IRQ_MODE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="NMI_MODE">NMI_MODE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_DIV">UART_DIV</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_PRESCALE">UART_PRESCALE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UART_PRE_SIZE">UART_PRE_SIZE</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_module/sim/testbenches/xml/io_module_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,17 → 26,10
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_module" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>FONT</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>STARTUP</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter> |
|
/ip/io_module/sim/testbenches/xml/io_module_gpio_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,17 → 26,8
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_module" |
spirit:version="gpio_dutg.design"/> |
spirit:version="gpio_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BASE_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NMI_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>IRQ_MODE</spirit:name><spirit:value>8'h00</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
</spirit:model> |
</spirit:component> |
/ip/io_module/sim/testbenches/xml/io_module_mouse_tb.xml
43,29 → 43,22
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>trace_bus</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>path</spirit:name> |
<spirit:value>root.dut</spirit:value> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>bus_name</spirit:name> |
<spirit:value>reg_mb</spirit:value> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
73,6 → 66,7
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
81,6 → 75,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.mouse_tb</spirit:value> |
</spirit:parameter> |
/ip/io_module/sim/testbenches/xml/io_module_mouse_lint.xml
39,10 → 39,47
<spirit:name>io_module</spirit:name> |
<spirit:version>mouse_lint</spirit:version> |
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
|
<spirit:views> |
/ip/io_module/sim/testbenches/xml/io_module_gpio_tb.xml
43,36 → 43,28
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>trace_bus</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>path</spirit:name> |
<spirit:value>root.dut</spirit:value> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>bus_name</spirit:name> |
<spirit:value>reg_mb</spirit:value> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
81,6 → 73,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.gpio_tb</spirit:value> |
</spirit:parameter> |
/ip/io_module/sim/testbenches/xml/io_module_def_tb.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
45,26 → 45,18
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>trace_bus</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>path</spirit:name> |
<spirit:value>root.dut</spirit:value> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>bus_name</spirit:name> |
<spirit:value>reg_mb</spirit:value> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
72,7 → 64,6
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
81,6 → 72,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
</spirit:parameter> |
/ip/io_utimer/rtl/xml/io_utimer_def.xml
134,13 → 134,27
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_registers</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:phase>102.1</spirit:phase> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:apiType>none</spirit:apiType> |
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe> |
254,14 → 268,6
|
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_utimer" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
/ip/io_utimer/sim/testbenches/xml/io_utimer_def_lint.xml
41,11 → 41,48
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
|
/ip/io_utimer/sim/testbenches/xml/io_utimer_def_duth.design.xml
0,0 → 1,86
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_utimer -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>io</spirit:library> |
<spirit:name>io_utimer</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr" spirit:left="3" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="io" spirit:name="io_utimer" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/ip/io_utimer/sim/testbenches/xml/io_utimer_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="io" |
spirit:name="io_utimer" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |