URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/logic/ip/micro_bus
- from Rev 131 to Rev 133
- ↔ Reverse comparison
Rev 131 → Rev 133
/componentCfg.xml
25,10 → 25,43
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</socgen:doc> |
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<socgen:configurations> |
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<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:parameters> |
<socgen:parameter><socgen:name>ADD</socgen:name><socgen:value>0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH2_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH2_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH3_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH3_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH4_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH4_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH5_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH5_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
|
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<socgen:configuration> |
<socgen:name>exp_default</socgen:name> |
<socgen:parameters> |
<socgen:parameter><socgen:name>SLA_ADD_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SLA_DATA_WIDTH</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>MAS_ADD_WIDTH</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>MAS_DATA_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
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</socgen:parameters> |
</socgen:configuration> |
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</socgen:configurations> |
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<socgen:sim> |
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|
45,6 → 78,7
<socgen:testbench> |
<socgen:variant>micro_bus_def_tb</socgen:variant> |
<socgen:version>def_tb</socgen:version> |
<socgen:configuration>default</socgen:configuration> |
<socgen:parameters> |
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>100000</socgen:value></socgen:parameter> |
64,6 → 98,7
<socgen:name>micro_bus</socgen:name> |
<socgen:variant>micro_bus_def_lint</socgen:variant> |
<socgen:version>def_lint</socgen:version> |
<socgen:configuration>default</socgen:configuration> |
<socgen:tools> |
<socgen:tool>rtl_check</socgen:tool> |
</socgen:tools> |
71,9 → 106,6
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</socgen:testbenches> |
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/rtl/xml/micro_bus_def.xml
277,7 → 277,7
<spirit:portMap> |
<spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>io_reg_addr</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>11</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
509,8 → 509,26
<spirit:componentGenerators> |
|
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
533,6 → 551,9
</spirit:componentGenerators> |
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<spirit:fileSets> |
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<spirit:fileSet> |
/rtl/xml/micro_bus_exp5.xml
129,7 → 129,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_0_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
190,7 → 190,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_1_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
253,7 → 253,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_2_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
312,7 → 312,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_3_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
373,7 → 373,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_4_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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429,10 → 429,25
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>exp_default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
592,15 → 607,6
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>SLA_ADDR_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SLA_DATA_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MAS_ADDR_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MAS_DATA_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
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<spirit:ports> |
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<spirit:port><spirit:name>clk</spirit:name> |
/rtl/xml/micro_bus_exp6.xml
130,7 → 130,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_0_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
191,7 → 191,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_1_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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254,7 → 254,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_2_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
313,7 → 313,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_3_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
374,7 → 374,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_4_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
433,7 → 433,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_5_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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491,7 → 491,26
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>exp_default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
651,15 → 670,8
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>SLA_ADDR_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SLA_DATA_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MAS_ADDR_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MAS_DATA_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
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<spirit:ports> |
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<spirit:port><spirit:name>clk</spirit:name> |
/rtl/xml/micro_bus_byte.xml
205,6 → 205,19
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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/rtl/xml/micro_bus_exp9.xml
133,7 → 133,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_0_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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194,7 → 194,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_1_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
257,7 → 257,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_2_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
316,7 → 316,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_3_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
377,7 → 377,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_4_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
436,7 → 436,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_5_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
496,7 → 496,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_6_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
557,7 → 557,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_7_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
617,7 → 617,7
<spirit:logicalPort><spirit:name>addr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>mas_8_addr_out</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
678,6 → 678,23
<spirit:componentGenerators> |
|
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>exp_default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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842,15 → 859,7
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>SLA_ADDR_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SLA_DATA_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MAS_ADDR_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MAS_DATA_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
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<spirit:ports> |
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<spirit:port><spirit:name>clk</spirit:name> |
/rtl/verilog/top.body.exp6
31,12 → 31,12
assign mas_4_wdata_out = wdata_in; |
assign mas_5_wdata_out = wdata_in; |
|
assign mas_0_addr_out = addr_in[7:0]; |
assign mas_1_addr_out = addr_in[7:0]; |
assign mas_2_addr_out = addr_in[7:0]; |
assign mas_3_addr_out = addr_in[7:0]; |
assign mas_4_addr_out = addr_in[7:0]; |
assign mas_5_addr_out = addr_in[7:0]; |
assign mas_0_addr_out = addr_in[3:0]; |
assign mas_1_addr_out = addr_in[3:0]; |
assign mas_2_addr_out = addr_in[3:0]; |
assign mas_3_addr_out = addr_in[3:0]; |
assign mas_4_addr_out = addr_in[3:0]; |
assign mas_5_addr_out = addr_in[3:0]; |
|
assign mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in; |
assign mas_1_cs_out = (addr_in[7:4] == 4'h1) && cs_in; |
/rtl/verilog/top.body.exp9
43,15 → 43,15
assign mas_7_wdata_out = wdata_in; |
assign mas_8_wdata_out = wdata_in; |
|
assign mas_0_addr_out = addr_in[7:0]; |
assign mas_1_addr_out = addr_in[7:0]; |
assign mas_2_addr_out = addr_in[7:0]; |
assign mas_3_addr_out = addr_in[7:0]; |
assign mas_4_addr_out = addr_in[7:0]; |
assign mas_5_addr_out = addr_in[7:0]; |
assign mas_6_addr_out = addr_in[7:0]; |
assign mas_7_addr_out = addr_in[7:0]; |
assign mas_8_addr_out = addr_in[7:0]; |
assign mas_0_addr_out = addr_in[3:0]; |
assign mas_1_addr_out = addr_in[3:0]; |
assign mas_2_addr_out = addr_in[3:0]; |
assign mas_3_addr_out = addr_in[3:0]; |
assign mas_4_addr_out = addr_in[3:0]; |
assign mas_5_addr_out = addr_in[3:0]; |
assign mas_6_addr_out = addr_in[3:0]; |
assign mas_7_addr_out = addr_in[3:0]; |
assign mas_8_addr_out = addr_in[3:0]; |
|
assign mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in; |
assign mas_1_cs_out = (addr_in[7:4] == 4'h1) && cs_in; |
/rtl/verilog/top.body
1,184 → 1,142
reg mem_cs_r; |
|
|
always@(*) |
begin |
if(addr_in[15:8] == 8'h00) mem_cs = 1'b1; |
if(addr_in[15:8] == 8'h00) mem_cs = 1'b1; |
else mem_cs = 1'b0; |
end |
|
reg CS0_r; |
|
|
|
always@(posedge clk) |
|
begin |
CS0_r <= mem_cs; |
mem_cs_r <= mem_cs; |
end |
|
|
assign mem_addr = addr_in; |
assign mem_rd = rd_in; |
assign mem_wr = wr_in; |
assign mem_wdata = {wdata_in,wdata_in}; |
assign enable = ~( ext_mem_wait || io_reg_wait ); |
|
|
|
|
|
reg mem_cs2; |
reg CSP_r; |
|
reg data_cs_r; |
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b1111) mem_cs2 = 1'b1; |
else mem_cs2 = 1'b0; |
if(addr_in[15:12] == 4'b0000) data_cs = 1'b1; |
else data_cs = 1'b0; |
end |
|
always@(posedge clk) |
begin |
CSP_r <= mem_cs2; |
end |
|
begin |
data_cs_r <= data_cs; |
end |
|
assign data_addr = addr_in[11:1]; |
assign data_rd = rd_in; |
assign data_wr = wr_in; |
assign data_wdata = {wdata_in,wdata_in}; |
assign data_be[0] = !addr_in[0]; |
assign data_be[1] = addr_in[0]; |
|
|
|
reg mem_cs3; |
reg CSI_r; |
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b1000) mem_cs3 = 1'b1; |
else mem_cs3 = 1'b0; |
end |
|
always@(posedge clk) |
|
begin |
CSI_r <= mem_cs3 ; |
end |
|
reg io_reg_cs_r; |
|
|
|
reg mem_cs4; |
reg CSB_r; |
|
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b1100) mem_cs4 = 1'b1; |
else mem_cs4 = 1'b0; |
end |
if(addr_in[15:8] == 8'b10000000) io_reg_cs = 1'b1; |
else io_reg_cs = 1'b0; |
end |
|
always@(posedge clk) |
|
begin |
CSB_r <= mem_cs4; |
io_reg_cs_r <= io_reg_cs; |
end |
|
|
assign io_reg_addr = addr_in[7:0]; |
assign io_reg_rd = rd_in; |
assign io_reg_wr = wr_in; |
assign io_reg_wdata = wdata_in; |
|
|
|
|
|
reg mem_cs5; |
reg CSE_r; |
|
|
reg ext_mem_cs_r; |
|
always@(*) |
begin |
if(addr_in[15:14] == 2'b01) mem_cs5 = 1'b1; |
else mem_cs5 = 1'b0; |
if(addr_in[15:14] == 2'b01) ext_mem_cs = 1'b1; |
else ext_mem_cs = 1'b0; |
end |
|
|
|
|
always@(posedge clk) |
|
begin |
CSE_r <= mem_cs5; |
ext_mem_cs_r <= ext_mem_cs; |
end |
|
|
|
assign ext_mem_addr = addr_in[13:0]; |
assign ext_mem_rd = rd_in; |
assign ext_mem_wr = wr_in; |
assign ext_mem_wdata = {wdata_in,wdata_in}; |
|
|
|
|
|
|
|
reg prog_rom_mem_cs_r; |
|
|
|
assign mem_addr = addr_in; |
assign mem_rd = rd_in; |
assign mem_wr = wr_in; |
assign mem_wdata = {wdata_in,wdata_in}; |
assign enable = ~( ext_mem_wait || io_reg_wait ); |
|
|
|
reg data_cs_r; |
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b0000) data_cs = 1'b1; |
else data_cs = 1'b0; |
end |
if(addr_in[15:12] == 4'b1100) prog_rom_mem_cs = 1'b1; |
else prog_rom_mem_cs = 1'b0; |
end |
|
always@(posedge clk) |
|
begin |
data_cs_r <= data_cs; |
prog_rom_mem_cs_r <= prog_rom_mem_cs; |
end |
|
assign data_addr = addr_in[11:1]; |
assign data_rd = rd_in; |
assign data_wr = wr_in; |
assign data_wdata = {wdata_in,wdata_in}; |
assign data_be[0] = !addr_in[0]; |
assign data_be[1] = addr_in[0]; |
|
assign prog_rom_mem_addr = addr_in[11:0]; |
assign prog_rom_mem_rd = rd_in; |
assign prog_rom_mem_wr = wr_in; |
assign prog_rom_mem_wdata = {wdata_in,wdata_in}; |
|
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b1000) io_reg_cs = 1'b1; |
else io_reg_cs = 1'b0; |
end |
assign io_reg_addr = addr_in[11:0]; |
assign io_reg_rd = rd_in; |
assign io_reg_wr = wr_in; |
assign io_reg_wdata = wdata_in; |
|
|
always@(*) |
begin |
if(addr_in[15:14] == 2'b01) ext_mem_cs = 1'b1; |
else ext_mem_cs = 1'b0; |
end |
|
assign ext_mem_addr = addr_in[13:0]; |
assign ext_mem_rd = rd_in; |
assign ext_mem_wr = wr_in; |
assign ext_mem_wdata = {wdata_in,wdata_in}; |
|
|
|
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b1100) prog_rom_mem_cs = 1'b1; |
else prog_rom_mem_cs = 1'b0; |
end |
reg sh_prog_rom_mem_cs_r; |
|
|
assign prog_rom_mem_addr = addr_in[11:0]; |
assign prog_rom_mem_rd = rd_in; |
assign prog_rom_mem_wr = wr_in; |
assign prog_rom_mem_wdata = {wdata_in,wdata_in}; |
|
|
|
always@(*) |
begin |
if(addr_in[15:12] == 4'b1111) sh_prog_rom_mem_cs = 1'b1; |
186,6 → 144,12
end |
|
|
always@(posedge clk) |
|
begin |
sh_prog_rom_mem_cs_r <= sh_prog_rom_mem_cs; |
end |
|
assign sh_prog_rom_mem_addr = addr_in[11:0]; |
assign sh_prog_rom_mem_rd = rd_in; |
assign sh_prog_rom_mem_wr = wr_in; |
194,14 → 158,18
|
|
|
|
|
|
|
always@(*) |
if ( CS0_r ) rdata_out = mem_rdata; |
if ( mem_cs_r ) rdata_out = mem_rdata; |
else |
if ( data_cs_r ) rdata_out = data_rdata; |
if ( data_cs_r ) rdata_out = data_rdata; |
else |
if ( CSB_r ) rdata_out = prog_rom_mem_rdata; |
if ( prog_rom_mem_cs_r ) rdata_out = prog_rom_mem_rdata; |
else |
if ( CSI_r ) rdata_out = io_reg_rdata; |
if ( io_reg_cs_r ) rdata_out = io_reg_rdata; |
else |
if ( CSP_r ) rdata_out = sh_prog_rom_mem_rdata; |
else rdata_out = ext_mem_rdata; |
if ( sh_prog_rom_mem_cs_r ) rdata_out = sh_prog_rom_mem_rdata; |
else rdata_out = ext_mem_rdata; |
/rtl/verilog/top.body.exp5
30,11 → 30,11
assign mas_4_wdata_out = wdata_in; |
|
|
assign mas_0_addr_out = addr_in[7:0]; |
assign mas_1_addr_out = addr_in[7:0]; |
assign mas_2_addr_out = addr_in[7:0]; |
assign mas_3_addr_out = addr_in[7:0]; |
assign mas_4_addr_out = addr_in[7:0]; |
assign mas_0_addr_out = addr_in[3:0]; |
assign mas_1_addr_out = addr_in[3:0]; |
assign mas_2_addr_out = addr_in[3:0]; |
assign mas_3_addr_out = addr_in[3:0]; |
assign mas_4_addr_out = addr_in[3:0]; |
|
|
assign mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in; |
/sim/testbenches/xml/micro_bus_def_tb.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
53,6 → 53,10
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
</spirit:parameter> |
80,7 → 84,7
<spirit:model> |
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR_WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>addr_width</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
|
/sim/testbenches/xml/micro_bus_def_lint.xml
42,9 → 42,46
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
/sim/testbenches/xml/micro_bus_def_duth.design.xml
0,0 → 1,320
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component micro_bus -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>logic</spirit:library> |
<spirit:name>micro_bus</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>addr_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="addr_in" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="addr_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_addr" spirit:left="11" spirit:right="1" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_be</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_be" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_be" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>data_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="data_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="data_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>enable</spirit:name> |
<spirit:externalPortReference spirit:portRef="enable" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="enable" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_addr" spirit:left="13" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>ext_mem_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="ext_mem_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ext_mem_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_addr" spirit:left="11" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_wait" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_wdata" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>io_reg_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_addr" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wait</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wait" spirit:left="1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wait" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mem_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="mem_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mem_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>prog_rom_mem_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="prog_rom_mem_addr" spirit:left="11" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="prog_rom_mem_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>prog_rom_mem_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="prog_rom_mem_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="prog_rom_mem_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>prog_rom_mem_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="prog_rom_mem_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="prog_rom_mem_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>prog_rom_mem_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="prog_rom_mem_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="prog_rom_mem_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>prog_rom_mem_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="prog_rom_mem_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="prog_rom_mem_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>prog_rom_mem_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="prog_rom_mem_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="prog_rom_mem_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rd_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="rd_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rd_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rdata_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata_out" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rdata_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>sh_prog_rom_mem_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="sh_prog_rom_mem_addr" spirit:left="11" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="sh_prog_rom_mem_addr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>sh_prog_rom_mem_cs</spirit:name> |
<spirit:externalPortReference spirit:portRef="sh_prog_rom_mem_cs" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="sh_prog_rom_mem_cs" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>sh_prog_rom_mem_rd</spirit:name> |
<spirit:externalPortReference spirit:portRef="sh_prog_rom_mem_rd" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="sh_prog_rom_mem_rd" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>sh_prog_rom_mem_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="sh_prog_rom_mem_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="sh_prog_rom_mem_rdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>sh_prog_rom_mem_wdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="sh_prog_rom_mem_wdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="sh_prog_rom_mem_wdata" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>sh_prog_rom_mem_wr</spirit:name> |
<spirit:externalPortReference spirit:portRef="sh_prog_rom_mem_wr" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="sh_prog_rom_mem_wr" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wdata_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="wdata_in" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wdata_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>wr_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="wr_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wr_in" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="logic" spirit:name="micro_bus" spirit:version="def" /> |
<spirit:configurableElementValues> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/sim/testbenches/xml/micro_bus_bfm.design.xml
100,7 → 100,7
<spirit:instanceName>bus</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="micro_bus_model" spirit:version="def" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="addr_width">ADDR_WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="addr_width">addr_width</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
/sim/testbenches/xml/micro_bus_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// // |
// regen by adding -tb to gen_verilog script // |
// // |
// // |
--> |
<spirit:component |
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="logic" |
spirit:name="micro_bus" |
spirit:version="def_dutg.design"/> |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |