URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
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- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/logic/ip/micro_bus
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/componentCfg.xml
29,8 → 29,9
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>ADD</socgen:name><socgen:value>0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>ADD</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
51,6 → 52,9
|
<socgen:configuration> |
<socgen:name>exp_default</socgen:name> |
<socgen:version>exp5</socgen:version> |
<socgen:version>exp6</socgen:version> |
<socgen:version>exp9</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>SLA_ADD_WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SLA_DATA_WIDTH</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
118,6 → 122,21
<socgen:lint> |
<socgen:name>default</socgen:name> |
<socgen:variant>micro_bus_def_lint</socgen:variant> |
<socgen:parameters> |
<socgen:parameter><socgen:name>ADD</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_MATCH</socgen:name><socgen:value>4'h2</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH2_BITS</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH2_MATCH</socgen:name><socgen:value>8'h03</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH3_BITS</socgen:name><socgen:value>2</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH3_MATCH</socgen:name><socgen:value>2'b10</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH4_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH4_MATCH</socgen:name><socgen:value>4'h9</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH5_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH5_MATCH</socgen:name><socgen:value>4'hf</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:lint> |
|
</socgen:rtl_check> |
130,7 → 149,19
<socgen:name>default</socgen:name> |
<socgen:variant>micro_bus_def_tb</socgen:variant> |
<socgen:parameters> |
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>20</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>ADD</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH0_MATCH</socgen:name><socgen:value>4'h0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH1_MATCH</socgen:name><socgen:value>4'h2</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH2_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH2_MATCH</socgen:name><socgen:value>4'h3</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH3_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH3_MATCH</socgen:name><socgen:value>4'h8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH4_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH4_MATCH</socgen:name><socgen:value>4'h9</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH5_BITS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>CH5_MATCH</socgen:name><socgen:value>4'hf</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:test> |
|
/rtl/xml/micro_bus_def.xml
509,26 → 509,7
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
538,12 → 519,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>micro_bus_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
579,7 → 556,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top</spirit:name> |
<spirit:name>../verilog/common/micro_bus_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
598,7 → 575,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top</spirit:name> |
<spirit:name>../verilog/common/micro_bus_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/rtl/xml/micro_bus_exp5.xml
430,25 → 430,6
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>exp_default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
457,12 → 438,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.exp5</spirit:value> |
<spirit:value>micro_bus_exp5</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
496,7 → 473,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.exp5</spirit:name> |
<spirit:name>../verilog/common/micro_bus_exp5</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
519,7 → 496,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.exp5</spirit:name> |
<spirit:name>../verilog/common/micro_bus_exp5</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/rtl/xml/micro_bus_exp6.xml
477,41 → 477,11
</spirit:portMaps> |
</spirit:busInterface> |
|
|
|
|
</spirit:busInterfaces> |
|
|
|
<spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>exp_default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
520,12 → 490,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.exp6</spirit:value> |
<spirit:value>micro_bus_exp6</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
559,7 → 525,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.exp6</spirit:name> |
<spirit:name>../verilog/common/micro_bus_exp6</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
582,7 → 548,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.exp6</spirit:name> |
<spirit:name>../verilog/common/micro_bus_exp6</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/rtl/xml/micro_bus_byte.xml
205,24 → 205,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
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|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
232,7 → 215,7
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.byte</spirit:value> |
<spirit:value>micro_bus_byte</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
273,7 → 256,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.byte</spirit:name> |
<spirit:name>../verilog/common/micro_bus_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
294,7 → 277,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.byte</spirit:name> |
<spirit:name>../verilog/common/micro_bus_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/rtl/xml/micro_bus_exp9.xml
678,28 → 678,10
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>exp_default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
|
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|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
709,12 → 691,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.exp9</spirit:value> |
<spirit:value>micro_bus_exp9</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
748,7 → 726,7
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.exp9</spirit:name> |
<spirit:name>../verilog/common/micro_bus_exp9</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
771,7 → 749,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.exp9</spirit:name> |
<spirit:name>../verilog/common/micro_bus_exp9</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/rtl/verilog/top.body.safe
File deleted
/rtl/verilog/top.body
1,10 → 1,18
reg mem_cs_r; |
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|
assign enable = ~( ext_mem_wait || io_reg_wait ); |
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/* CH0 */ |
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reg mem_cs_r; |
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always@(*) |
always@(addr_in) |
begin |
if(addr_in[15:8] == 8'h00) mem_cs = 1'b1; |
else mem_cs = 1'b0; |
if(addr_in[ADD-1:ADD-CH0_BITS] == CH0_MATCH) mem_cs = 1'b1; |
else mem_cs = 1'b0; |
end |
|
|
19,7 → 27,6
assign mem_rd = rd_in; |
assign mem_wr = wr_in; |
assign mem_wdata = {wdata_in,wdata_in}; |
assign enable = ~( ext_mem_wait || io_reg_wait ); |
|
|
|
26,21 → 33,22
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/* CH1 */ |
|
reg data_cs_r; |
|
always@(*) |
always@(addr_in) |
begin |
if(addr_in[15:12] == 4'b0000) data_cs = 1'b1; |
else data_cs = 1'b0; |
if(addr_in[ADD-1:ADD-CH1_BITS] == CH1_MATCH) data_cs = 1'b1; |
else data_cs = 1'b0; |
end |
|
always@(posedge clk) |
|
begin |
data_cs_r <= data_cs; |
end |
|
assign data_addr = addr_in[11:1]; |
assign data_addr = addr_in[ADD-CH1_BITS-1:1]; |
assign data_rd = rd_in; |
assign data_wr = wr_in; |
assign data_wdata = {wdata_in,wdata_in}; |
48,16 → 56,12
assign data_be[1] = addr_in[0]; |
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/* CH2 */ |
reg io_reg_cs_r; |
|
always@(*) |
always@(addr_in) |
begin |
if(addr_in[15:8] == 8'b10000000) io_reg_cs = 1'b1; |
if(addr_in[ADD-1:ADD-CH2_BITS] == CH2_MATCH) io_reg_cs = 1'b1; |
else io_reg_cs = 1'b0; |
end |
|
68,23 → 72,19
end |
|
|
assign io_reg_addr = addr_in[7:0]; |
assign io_reg_addr = addr_in[ADD-CH2_BITS-1:0]; |
assign io_reg_rd = rd_in; |
assign io_reg_wr = wr_in; |
assign io_reg_wdata = wdata_in; |
|
/* CH3 */ |
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reg ext_mem_cs_r; |
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always@(*) |
always@(addr_in) |
begin |
if(addr_in[15:14] == 2'b01) ext_mem_cs = 1'b1; |
else ext_mem_cs = 1'b0; |
if(addr_in[ADD-1:ADD-CH3_BITS] == CH3_MATCH) ext_mem_cs = 1'b1; |
else ext_mem_cs = 1'b0; |
end |
|
|
94,24 → 94,21
ext_mem_cs_r <= ext_mem_cs; |
end |
|
|
|
assign ext_mem_addr = addr_in[13:0]; |
assign ext_mem_addr = addr_in[ADD-CH3_BITS-1:0]; |
assign ext_mem_rd = rd_in; |
assign ext_mem_wr = wr_in; |
assign ext_mem_wdata = {wdata_in,wdata_in}; |
|
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/* CH4 */ |
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reg prog_rom_mem_cs_r; |
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always@(*) |
always@(addr_in) |
begin |
if(addr_in[15:12] == 4'b1100) prog_rom_mem_cs = 1'b1; |
else prog_rom_mem_cs = 1'b0; |
if(addr_in[ADD-1:ADD-CH4_BITS] == CH4_MATCH) prog_rom_mem_cs = 1'b1; |
else prog_rom_mem_cs = 1'b0; |
end |
|
always@(posedge clk) |
119,28 → 116,20
begin |
prog_rom_mem_cs_r <= prog_rom_mem_cs; |
end |
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assign prog_rom_mem_addr = addr_in[11:0]; |
assign prog_rom_mem_addr = addr_in[ADD-CH4_BITS-1:0]; |
assign prog_rom_mem_rd = rd_in; |
assign prog_rom_mem_wr = wr_in; |
assign prog_rom_mem_wdata = {wdata_in,wdata_in}; |
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/* CH5 */ |
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reg sh_prog_rom_mem_cs_r; |
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always@(*) |
always@(addr_in) |
begin |
if(addr_in[15:12] == 4'b1111) sh_prog_rom_mem_cs = 1'b1; |
else sh_prog_rom_mem_cs = 1'b0; |
if(addr_in[ADD-1:ADD-CH5_BITS] == CH5_MATCH) sh_prog_rom_mem_cs = 1'b1; |
else sh_prog_rom_mem_cs = 1'b0; |
end |
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|
150,7 → 139,7
sh_prog_rom_mem_cs_r <= sh_prog_rom_mem_cs; |
end |
|
assign sh_prog_rom_mem_addr = addr_in[11:0]; |
assign sh_prog_rom_mem_addr = addr_in[ADD-CH5_BITS-1:0]; |
assign sh_prog_rom_mem_rd = rd_in; |
assign sh_prog_rom_mem_wr = wr_in; |
assign sh_prog_rom_mem_wdata = {wdata_in,wdata_in}; |
/sim/testbenches/xml/micro_bus_byte_dutg.design.xml
File deleted
/sim/testbenches/xml/micro_bus_def_dutg.design.xml
File deleted
/sim/testbenches/xml/micro_bus_exp5_dut.params.xml
File deleted
/sim/testbenches/xml/micro_bus_exp6_dut.params.xml
File deleted
/sim/testbenches/xml/micro_bus_exp9_dut.params.xml
File deleted
/sim/testbenches/xml/micro_bus_byte_dut.params.xml
File deleted
/sim/testbenches/xml/micro_bus_exp5_dutg.design.xml
File deleted
/sim/testbenches/xml/micro_bus_exp6_dutg.design.xml
File deleted
/sim/testbenches/xml/micro_bus_exp9_dutg.design.xml
File deleted
/sim/testbenches/xml/micro_bus_def_tb.xml
53,20 → 53,9
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
<spirit:value>micro_bus_def_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
188,7 → 177,7
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/micro_bus_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
204,7 → 193,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/micro_bus_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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/sim/testbenches/xml/micro_bus_def_lint.xml
42,46 → 42,6
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:model> |
/sim/testbenches/xml/micro_bus_def_duth.design.xml
122,7 → 122,7
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<spirit:adHocConnection> |
<spirit:name>io_reg_addr</spirit:name> |
<spirit:externalPortReference spirit:portRef="io_reg_addr" spirit:left="11" spirit:right="0" /> |
<spirit:externalPortReference spirit:portRef="io_reg_addr" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="io_reg_addr" /> |
</spirit:adHocConnection> |
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314,6 → 314,19
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="logic" spirit:name="micro_bus" spirit:version="def" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="ADD">ADD</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH0_BITS">CH0_BITS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH0_MATCH">CH0_MATCH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH1_BITS">CH1_BITS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH1_MATCH">CH1_MATCH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH2_BITS">CH2_BITS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH2_MATCH">CH2_MATCH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH3_BITS">CH3_BITS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH3_MATCH">CH3_MATCH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH4_BITS">CH4_BITS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH4_MATCH">CH4_MATCH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH5_BITS">CH5_BITS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CH5_MATCH">CH5_MATCH</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
/sim/testbenches/xml/micro_bus_def_dut.params.xml
30,6 → 30,19
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADD</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH0_BITS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH0_MATCH</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH1_BITS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH1_MATCH</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH2_BITS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH2_MATCH</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH3_BITS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH3_MATCH</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH4_BITS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH4_MATCH</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH5_BITS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CH6_MATCH</spirit:name><spirit:value>4'h0</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
</spirit:model> |
</spirit:component> |