OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/Projects/opencores.org/logic/ip/usb_epp/rtl
    from Rev 133 to Rev 134
    ↔ Reverse comparison
  •

Rev 133 → Rev 134

/xml/usb_epp_def.design.xml File deleted
/xml/usb_epp_def.xml
73,24 → 73,7
 
<spirit:componentGenerators>
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
99,12 → 82,8
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
<spirit:value>usb_epp_def</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
114,74 → 93,6
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
426,5 → 337,90
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/usb_epp_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/usb_epp_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
</spirit:component>
/verilog/copyright
0,0 → 1,44
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / COMPONENT \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* usb io interface for Digilent FPGA boards */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 

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