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  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/Projects/opencores.org/wishbone/ip/model/rtl/verilog
    from Rev 131 to Rev 134
    ↔ Reverse comparison
  •

Rev 131 → Rev 134

/monitor_copyright
0,0 → 1,42
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's simulation monitor ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// wishbone protocal monitor ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
/slave_copyright
0,0 → 1,43
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_slave_model ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot (simons@opencores.org) ////
//// ////
//// Based on: ////
//// - i2c/bench/verilog/wb_master_model.v ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
/master_copyright
0,0 → 1,43
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_master_model ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot (simons@opencores.org) ////
//// ////
//// Based on: ////
//// - i2c/bench/verilog/wb_master_model.v ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
/sim/master.tasks
0,0 → 1,90
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
 
 
 
// Wishbone write cycle
task wb_write;
input [awidth -1:0] a;
input [(dwidth/8) -1:0] s;
input [dwidth -1:0] d;
begin
$display("%t %m cycle %h %h",$realtime,a,d );
// assert wishbone signal
adr <= a;
dout <= d;
cyc <= 1'b1;
stb <= 1'b1;
we <= 1'b1;
sel <= s;
next(1);
// wait for acknowledge from slave
while(~ack) next(1);
// negate wishbone signals
cyc <= 1'b0;
stb <= 1'b0;
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
end
endtask
// Wishbone read cycle
task wb_read;
input [awidth -1:0] a;
output [dwidth -1:0] d;
begin
// assert wishbone signals
adr <= a;
dout <= {dwidth{1'b0}};
cyc <= 1'b1;
stb <= 1'b1;
we <= 1'b0;
sel <= {dwidth/8{1'b1}};
next(1);
// wait for acknowledge from slave
while(~ack) next(1);
$display("%t %m cycle %h %h",$realtime,a,din );
// negate wishbone signals
cyc <= 1'b0;
stb <= 1'b0;
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
d <= din;
end
endtask
// Wishbone compare cycle (read data from location and compare with expected data)
task wb_cmp;
input [awidth-1:0] a;
input [(dwidth/8) -1:0] s;
input [dwidth-1:0] d_exp;
begin
// assert wishbone signals
adr <= a;
dout <= {dwidth{1'b0}};
cyc <= 1'b1;
stb <= 1'b1;
we <= 1'b0;
sel <= s;
next(1);
// wait for acknowledge from slave
while(~ack) next(1);
$display("%t %m check %h %h %h",$realtime,a,din,d_exp );
if (!(d_exp === din)) cg.fail(" Data compare error");
// negate wishbone signals
cyc <= 1'b0;
stb <= 1'b0;
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
end
endtask
 
 
/sim/monitor
0,0 → 1,129
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's simulation monitor ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// wishbone protocal monitor ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module model_monitor
#(parameter TEST_NAME="unspecified",
parameter INSTANCE="none",
parameter ADD_WIDTH=32,
parameter DATA_WIDTH=32
)
(
input wire clk,
input wire reset,
input wire [ADD_WIDTH-1:0] wb_adr,
input wire wb_ack,
input wire wb_err,
input wire wb_cyc,
input wire wb_stb,
input wire wb_we,
input wire [DATA_WIDTH-1:0] wb_read,
input wire [DATA_WIDTH-1:0] wb_write,
input wire [3:0] wb_sel
);
integer fgeneral;
//
// Initialization
//
initial
begin
fgeneral = $fopen({TEST_NAME,"_",INSTANCE,"_wishbone.log"});
end
always @(posedge clk)
begin
if (wb_stb && wb_cyc && wb_ack)
begin
$fdisplay(fgeneral, "%t %m WB access %x %x %x %x %x", $realtime, wb_adr, wb_we, wb_sel, wb_read, wb_write, );
end
end
integer wb_progress;
reg [ADD_WIDTH-1:0] wb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge clk)
if (reset)
begin
wb_progress = 0;
wb_progress_addr = wb_adr;
end
else
begin
if (wb_cyc && (wb_progress != 2))
begin
wb_progress = 1;
end
if (wb_stb)
begin
if (wb_progress >= 1)
begin
if (wb_progress == 1) wb_progress_addr = wb_adr;
wb_progress = 2;
end
else
begin
$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_stb_i raised without wb_cyc_i", $realtime);
end
end
if (wb_ack & wb_err)
begin
$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_ack_i and wb_err_i raised at the same time", $realtime);
end
if ((wb_progress == 2) && (wb_progress_addr != wb_adr))
begin
$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_adr changed while waiting for wb_err_i/wb_ack_i", $realtime);
end
if (wb_ack | wb_err)
if (wb_progress == 2)
begin
wb_progress = 0;
wb_progress_addr = wb_adr;
end
else
begin
$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_ack_i/wb_err_i raised without wb_cyc_i/wb_stb_i", $realtime);
end
if ((wb_progress == 2) && !wb_stb)
begin
$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_stb lowered without wb_err_i/wb_ack_i", $realtime);
end
end
endmodule
/sim/slave
0,0 → 1,124
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_slave_model ////
//// ////
 
module model_slave
#( parameter dwidth = 32,
parameter awidth = 32
)(
input wire clk,
input wire reset,
 
input wire [awidth -1:0] adr,
input wire [dwidth -1:0] dout,
input wire cyc,
input wire stb,
input wire we,
input wire [dwidth/8 -1:0] sel,
 
output reg [dwidth -1:0] din,
output reg ack,
output reg err,
output reg rty
);
 
 
 
 
 
 
 
always@(posedge clk)
if(reset)
begin
din <= {dwidth{1'b0}};
ack <= (cyc && stb);
err <= 1'b0;
rty <= 1'b0;
end
 
 
 
 
 
// Wishbone write cycle
task wb_write;
input [awidth -1:0] a;
input [(dwidth/8) -1:0] s;
input [dwidth -1:0] d;
begin
$display("%t %m cycle %h %h",$realtime,a,d );
// assert wishbone signal
adr <= a;
dout <= d;
cyc <= 1'b1;
stb <= 1'b1;
we <= 1'b1;
sel <= s;
next(1);
// wait for acknowledge from slave
while(~ack) next(1);
// negate wishbone signals
cyc <= 1'b0;
stb <= 1'b0;
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
end
endtask
// Wishbone read cycle
task wb_read;
input [awidth -1:0] a;
output [dwidth -1:0] d;
begin
// assert wishbone signals
adr <= a;
dout <= {dwidth{1'b0}};
cyc <= 1'b1;
stb <= 1'b1;
we <= 1'b0;
sel <= {dwidth/8{1'b1}};
next(1);
// wait for acknowledge from slave
while(~ack) next(1);
$display("%t %m cycle %h %h",$realtime,a,din );
// negate wishbone signals
cyc <= 1'b0;
stb <= 1'b0;
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
d <= din;
end
endtask
// Wishbone compare cycle (read data from location and compare with expected data)
task wb_cmp;
input [awidth-1:0] a;
input [(dwidth/8) -1:0] s;
input [dwidth-1:0] d_exp;
begin
// assert wishbone signals
adr <= a;
dout <= {dwidth{1'b0}};
cyc <= 1'b1;
stb <= 1'b1;
we <= 1'b0;
sel <= s;
next(1);
// wait for acknowledge from slave
while(~ack) next(1);
$display("%t %m check %h %h %h",$realtime,a,din,d_exp );
if (!(d_exp === din)) cg.fail(" Data compare error");
// negate wishbone signals
cyc <= 1'b0;
stb <= 1'b0;
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
end
endtask
endmodule
/sim/master
0,0 → 1,16
 
// Internal signals
reg [dwidth -1:0] q;
always@(posedge clk)
if(reset)
begin
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
cyc <= 1'b0;
stb <= 1'b0;
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
end
 
 
 

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