URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/wishbone/ip/model/rtl/xml
- from Rev 131 to Rev 134
- ↔ Reverse comparison
Rev 131 → Rev 134
/model_master.xml
54,7 → 54,7
<spirit:logicalPort><spirit:name>adr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>adr</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>wb_addr_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>awidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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63,7 → 63,7
<spirit:logicalPort><spirit:name>wdata</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>dout</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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72,7 → 72,7
<spirit:logicalPort><spirit:name>rdata</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>din</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:wire><spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
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132,47 → 132,123
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<spirit:componentGenerators> |
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<spirit:fileSets> |
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>model_master</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>model_master</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
</spirit:componentGenerators> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
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<spirit:model> |
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<spirit:views> |
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<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
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</spirit:views> |
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>dwidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>awidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
258,7 → 334,104
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/master_copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/model_master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/master_copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/model_master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |