URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/wishbone/ip/model/rtl/xml
- from Rev 134 to Rev 135
- ↔ Reverse comparison
Rev 134 → Rev 135
/model_master.xml
27,95 → 27,96
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
<ipxact:component |
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014 |
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>wishbone</spirit:library> |
<spirit:name>model</spirit:name> |
<spirit:version>master</spirit:version> <spirit:configuration>default</spirit:configuration> |
<ipxact:vendor>opencores.org</ipxact:vendor> |
<ipxact:library>wishbone</ipxact:library> |
<ipxact:name>model</ipxact:name> |
<ipxact:version>master</ipxact:version> |
|
|
|
<spirit:busInterfaces> |
<ipxact:busInterfaces> |
|
|
<spirit:busInterface><spirit:name>wb</spirit:name> |
<spirit:busType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="def"/> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="rtl"/> |
<spirit:master/> |
<spirit:portMaps> |
<ipxact:busInterface><ipxact:name>wb</ipxact:name> |
<ipxact:busType vendor="opencores.org" library="wishbone" name="wishbone" version="def"/> |
<ipxact:abstractionTypes> |
<ipxact:abstractionType> |
<ipxact:abstractionRef vendor="opencores.org" library="wishbone" name="wishbone" version="rtl"/> |
<ipxact:portMaps> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>adr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>adr</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>awidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>adr</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>adr</ipxact:name> |
<ipxact:wire><ipxact:vectors><ipxact:vector><ipxact:left>awidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>wdata</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>dout</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>wdata</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>dout</ipxact:name> |
<ipxact:wire><ipxact:vectors><ipxact:vector><ipxact:left>dwidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>rdata</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>din</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>rdata</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>din</ipxact:name> |
<ipxact:wire><ipxact:vectors><ipxact:vector><ipxact:left>dwidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>sel</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>sel</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>sel</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>sel</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>ack</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>ack</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>ack</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>ack</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>cyc</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>cyc</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>cyc</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>cyc</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>stb</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>stb</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>stb</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>stb</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>we</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>we</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>we</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>we</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
|
123,124 → 124,155
|
|
|
</spirit:portMaps> |
</ipxact:portMaps> |
|
</ipxact:abstractionType> |
</ipxact:abstractionTypes> |
<ipxact:master/> |
|
</spirit:busInterface> |
|
</spirit:busInterfaces> |
</ipxact:busInterface> |
|
</ipxact:busInterfaces> |
|
|
|
<spirit:componentGenerators> |
|
<ipxact:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>model_master</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<ipxact:componentGenerator> |
<ipxact:name>gen_verilog_sim</ipxact:name> |
<ipxact:phase>104.0</ipxact:phase> |
<ipxact:apiType>none</ipxact:apiType> |
<ipxact:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></ipxact:vendorExtensions> |
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe> |
<ipxact:parameters> |
<ipxact:parameter> |
<ipxact:name>destination</ipxact:name> |
<ipxact:value>model_master</ipxact:value> |
</ipxact:parameter> |
</ipxact:parameters> |
</ipxact:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>model_master</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<ipxact:componentGenerator> |
<ipxact:name>gen_verilog_syn</ipxact:name> |
<ipxact:phase>104.0</ipxact:phase> |
<ipxact:apiType>none</ipxact:apiType> |
<ipxact:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></ipxact:vendorExtensions> |
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe> |
<ipxact:parameters> |
<ipxact:parameter> |
<ipxact:name>destination</ipxact:name> |
<ipxact:value>model_master</ipxact:value> |
</ipxact:parameter> |
</ipxact:parameters> |
</ipxact:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
</ipxact:componentGenerators> |
|
|
|
|
<spirit:model> |
|
<ipxact:model> |
|
|
<ipxact:instantiations> |
<ipxact:componentInstantiation> |
<ipxact:name>verilog</ipxact:name> |
<ipxact:language>verilog</ipxact:language> |
<ipxact:moduleName>model_master</ipxact:moduleName> |
<ipxact:moduleParameters> |
<ipxact:moduleParameter parameterId="awidth" usageCount="1" usageType="nontyped"> |
<ipxact:name>awidth</ipxact:name> |
<ipxact:value>32</ipxact:value> |
</ipxact:moduleParameter> |
<ipxact:moduleParameter parameterId="dwidth" usageCount="2" usageType="nontyped"> |
<ipxact:name>dwidth</ipxact:name> |
<ipxact:value>32</ipxact:value> |
</ipxact:moduleParameter> |
</ipxact:moduleParameters> |
<ipxact:fileSetRef> |
<ipxact:localName>fs-sim</ipxact:localName> |
</ipxact:fileSetRef> |
</ipxact:componentInstantiation> |
</ipxact:instantiations> |
|
|
|
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
<ipxact:views> |
|
|
<ipxact:view> |
<ipxact:name>rtl</ipxact:name> |
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier> |
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef> |
</ipxact:view> |
|
|
<ipxact:view> |
<ipxact:name>verilog</ipxact:name> |
<ipxact:vendorExtensions> |
<ipxact:componentRef ipxact:vendor="opencores.org" |
ipxact:library="Testbench" |
ipxact:name="toolflow" |
ipxact:version="verilog"/> |
</ipxact:vendorExtensions> |
</ipxact:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<ipxact:view> |
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier> |
<ipxact:language>Verilog</ipxact:language> |
<ipxact:modelName></ipxact:modelName> |
<ipxact:fileSetRef> |
<ipxact:localName>fs-sim</ipxact:localName> |
</ipxact:fileSetRef> |
</ipxact:view> |
|
<ipxact:view> |
<ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier> |
<ipxact:language>Verilog</ipxact:language> |
<ipxact:modelName></ipxact:modelName> |
<ipxact:fileSetRef> |
<ipxact:localName>fs-syn</ipxact:localName> |
</ipxact:fileSetRef> |
</ipxact:view> |
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
|
|
|
<ipxact:view> |
<ipxact:name>doc</ipxact:name> |
<ipxact:vendorExtensions> |
<ipxact:componentRef ipxact:vendor="opencores.org" |
ipxact:library="Testbench" |
ipxact:name="toolflow" |
ipxact:version="documentation"/> |
</ipxact:vendorExtensions> |
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier> |
<ipxact:language>Verilog</ipxact:language> |
</ipxact:view> |
|
|
|
</spirit:views> |
|
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|
</ipxact:views> |
|
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249,184 → 281,184
|
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|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>dwidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>awidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:modelParameters> |
<ipxact:modelParameter><ipxact:name>dwidth</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter> |
<ipxact:modelParameter><ipxact:name>awidth</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter> |
</ipxact:modelParameters> |
|
<spirit:port><spirit:name>adr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>awidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
<ipxact:ports> |
|
<ipxact:port><ipxact:name>clk</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>dout</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>dwidth</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>reset</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>adr</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>awidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>cyc</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>stb</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>dout</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>dwidth</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>we</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<ipxact:port><ipxact:name>cyc</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>sel</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>dwidth/8-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>stb</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>we</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>din</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
<ipxact:port><ipxact:name>sel</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>dwidth/8-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>ack</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>err</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>din</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>dwidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>rty</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<ipxact:port><ipxact:name>ack</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
</spirit:ports> |
<ipxact:port><ipxact:name>err</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
</spirit:model> |
<ipxact:port><ipxact:name>rty</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
|
</ipxact:ports> |
|
</ipxact:model> |
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<ipxact:fileSets> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<ipxact:fileSet> |
<ipxact:name>fs-sim</ipxact:name> |
|
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/sim/master</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/master_copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/sim/master.tasks</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/model_master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/master_copyright</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/sim/model_master</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType> |
</ipxact:file> |
|
|
<ipxact:file> |
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/sim/</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
</ipxact:fileSet> |
|
|
|
<ipxact:fileSet> |
<ipxact:name>fs-syn</ipxact:name> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/master.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/sim/master</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/master_copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/sim/master.tasks</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/model_master</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/master_copyright</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
<ipxact:file> |
<ipxact:logicalName></ipxact:logicalName> |
<ipxact:name>../verilog/sim/model_master</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType> |
</ipxact:file> |
|
|
</spirit:fileSets> |
<ipxact:file> |
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/sim/</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType> |
</ipxact:file> |
|
</ipxact:fileSet> |
|
|
</ipxact:fileSets> |
|
|
|
434,4 → 466,7
|
|
|
</spirit:component> |
|
|
|
</ipxact:component> |
/model_monitor.xml
27,17 → 27,17
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
<ipxact:component |
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014 |
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>wishbone</spirit:library> |
<spirit:name>model</spirit:name> |
<spirit:version>monitor</spirit:version> <spirit:configuration>default</spirit:configuration> |
<ipxact:vendor>opencores.org</ipxact:vendor> |
<ipxact:library>wishbone</ipxact:library> |
<ipxact:name>model</ipxact:name> |
<ipxact:version>monitor</ipxact:version> |
|
|
|
47,129 → 47,166
|
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<ipxact:model> |
|
|
|
|
</spirit:fileSet> |
|
<ipxact:instantiations> |
<ipxact:componentInstantiation> |
<ipxact:name>verilog</ipxact:name> |
<ipxact:language>verilog</ipxact:language> |
<ipxact:moduleName>model_monitor</ipxact:moduleName> |
<ipxact:moduleParameters> |
<ipxact:moduleParameter parameterId="ADD_WIDTH" usageCount="1" usageType="nontyped"> |
<ipxact:name>ADD_WIDTH</ipxact:name> |
<ipxact:value>8</ipxact:value> |
</ipxact:moduleParameter> |
<ipxact:moduleParameter parameterId="DATA_WIDTH" usageCount="2" usageType="nontyped"> |
<ipxact:name>DATAWIDTH</ipxact:name> |
<ipxact:value>32</ipxact:value> |
</ipxact:moduleParameter> |
</ipxact:moduleParameters> |
<ipxact:fileSetRef> |
<ipxact:localName>fs-sim</ipxact:localName> |
</ipxact:fileSetRef> |
</ipxact:componentInstantiation> |
</ipxact:instantiations> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<ipxact:views> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<ipxact:view> |
<ipxact:name>rtl</ipxact:name> |
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier> |
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef> |
</ipxact:view> |
|
</ipxact:views> |
|
|
|
</spirit:fileSet> |
<ipxact:modelParameters> |
<ipxact:modelParameter><ipxact:name>TEST_NAME</ipxact:name><ipxact:value>"unspecified"</ipxact:value></ipxact:modelParameter> |
<ipxact:modelParameter><ipxact:name>INSTANCE</ipxact:name><ipxact:value>"none"</ipxact:value></ipxact:modelParameter> |
<ipxact:modelParameter><ipxact:name>ADD_WIDTH</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter> |
<ipxact:modelParameter><ipxact:name>DATA_WIDTH</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter> |
</ipxact:modelParameters> |
|
<ipxact:ports> |
|
<ipxact:port><ipxact:name>clk</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
</spirit:fileSets> |
<ipxact:port><ipxact:name>reset</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>wb_adr</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>ADD_WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>wb_ack</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>wb_err</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>wb_cyc</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>wb_stb</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<spirit:model> |
<ipxact:port><ipxact:name>wb_we</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
|
<ipxact:port><ipxact:name>wb_read</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>DATA_WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>TEST_NAME</spirit:name><spirit:value>"unspecified"</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INSTANCE</spirit:name><spirit:value>"none"</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>ADD_WIDTH</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DATA_WIDTH</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
<ipxact:port><ipxact:name>wb_write</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>DATA_WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>wb_sel</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>3</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
</ipxact:ports> |
|
<spirit:port><spirit:name>wb_adr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>ADD_WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
</ipxact:model> |
|
<spirit:port><spirit:name>wb_ack</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:fileSets> |
|
<spirit:port><spirit:name>wb_err</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>wb_cyc</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:fileSet> |
<ipxact:name>fs-sim</ipxact:name> |
|
<spirit:port><spirit:name>wb_stb</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:file> |
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../verilog/sim/</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType> |
</ipxact:file> |
|
<spirit:port><spirit:name>wb_we</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>wb_read</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>DATA_WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>wb_write</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>DATA_WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
</ipxact:fileSet> |
|
|
<spirit:port><spirit:name>wb_sel</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
<ipxact:fileSet> |
<ipxact:name>fs-syn</ipxact:name> |
|
</spirit:ports> |
|
</spirit:model> |
<ipxact:file> |
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../verilog/syn/</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType> |
</ipxact:file> |
|
|
</ipxact:fileSet> |
|
|
|
</ipxact:fileSets> |
|
|
|
|
|
</spirit:component> |
|
|
|
|
|
|
|
</ipxact:component> |
/model_slave.xml
27,107 → 27,112
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
<ipxact:component |
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014 |
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>wishbone</spirit:library> |
<spirit:name>model</spirit:name> |
<spirit:version>slave</spirit:version> <spirit:configuration>default</spirit:configuration> |
<ipxact:vendor>opencores.org</ipxact:vendor> |
<ipxact:library>wishbone</ipxact:library> |
<ipxact:name>model</ipxact:name> |
<ipxact:version>slave</ipxact:version> |
|
|
|
<spirit:busInterfaces> |
<ipxact:busInterfaces> |
|
|
<spirit:busInterface><spirit:name>wb</spirit:name> |
<spirit:busType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="def"/> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="rtl"/> |
<spirit:slave/> |
<spirit:portMaps> |
<ipxact:busInterface><ipxact:name>wb</ipxact:name> |
<ipxact:busType vendor="opencores.org" library="wishbone" name="wishbone" version="def"/> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>adr</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>adr</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>wb_addr_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
|
<ipxact:abstractionTypes> |
<ipxact:abstractionType> |
<ipxact:abstractionRef vendor="opencores.org" library="wishbone" name="wishbone" version="rtl"/> |
<ipxact:portMaps> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>wdata</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>dout</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>adr</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>adr</ipxact:name> |
<ipxact:wire><ipxact:vectors><ipxact:vector><ipxact:left>wb_addr_width-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>rdata</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>din</spirit:name> |
<spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>wdata</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>dout</ipxact:name> |
<ipxact:wire><ipxact:vectors><ipxact:vector><ipxact:left>wb_data_width-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>sel</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>sel</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>rdata</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>din</ipxact:name> |
<ipxact:wire><ipxact:vectors><ipxact:vector><ipxact:left>wb_data_width-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>ack</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>ack</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>sel</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>sel</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>cyc</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>cyc</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>ack</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>ack</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>cyc</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>cyc</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>stb</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>stb</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>we</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort><spirit:name>we</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>stb</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>stb</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
<ipxact:portMap> |
<ipxact:logicalPort><ipxact:name>we</ipxact:name> |
</ipxact:logicalPort> |
<ipxact:physicalPort><ipxact:name>we</ipxact:name> |
</ipxact:physicalPort> |
</ipxact:portMap> |
|
|
</ipxact:portMaps> |
|
|
</ipxact:abstractionType> |
</ipxact:abstractionTypes> |
<ipxact:slave/> |
|
|
</spirit:portMaps> |
</ipxact:busInterface> |
|
</spirit:busInterface> |
</ipxact:busInterfaces> |
|
</spirit:busInterfaces> |
|
|
|
136,129 → 141,162
|
|
|
<spirit:fileSets> |
<ipxact:model> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<ipxact:instantiations> |
<ipxact:componentInstantiation> |
<ipxact:name>verilog</ipxact:name> |
<ipxact:language>verilog</ipxact:language> |
<ipxact:moduleName>cde_sram_def</ipxact:moduleName> |
<ipxact:moduleParameters> |
<ipxact:moduleParameter parameterId="awidth" usageCount="1" usageType="nontyped"> |
<ipxact:name>awidth</ipxact:name> |
<ipxact:value>32</ipxact:value> |
</ipxact:moduleParameter> |
<ipxact:moduleParameter parameterId="awidth" usageCount="2" usageType="nontyped"> |
<ipxact:name>awidth</ipxact:name> |
<ipxact:value>32</ipxact:value> |
</ipxact:moduleParameter> |
</ipxact:moduleParameters> |
<ipxact:fileSetRef> |
<ipxact:localName>fs-sim</ipxact:localName> |
</ipxact:fileSetRef> |
</ipxact:componentInstantiation> |
</ipxact:instantiations> |
|
</spirit:fileSet> |
|
<ipxact:views> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<ipxact:view> |
<ipxact:name>rtl</ipxact:name> |
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier> |
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef> |
</ipxact:view> |
|
</ipxact:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
<ipxact:modelParameters> |
<ipxact:modelParameter><ipxact:name>dwidth</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter> |
<ipxact:modelParameter><ipxact:name>awidth</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter> |
</ipxact:modelParameters> |
|
</spirit:fileSet> |
<ipxact:ports> |
|
<ipxact:port><ipxact:name>clk</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
</spirit:fileSets> |
<ipxact:port><ipxact:name>reset</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>adr</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>awidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
|
<ipxact:port><ipxact:name>dout</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>dwidth</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
|
<spirit:model> |
<ipxact:port><ipxact:name>cyc</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>stb</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>we</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>dwidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>awidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
<ipxact:port><ipxact:name>sel</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>out</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>dwidth/8-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>din</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction> |
<ipxact:vectors><ipxact:vector><ipxact:left>dwidth-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>adr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>awidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>ack</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<ipxact:port><ipxact:name>err</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
<spirit:port><spirit:name>dout</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>dwidth</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
<ipxact:port><ipxact:name>rty</ipxact:name> |
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs> |
<ipxact:direction>in</ipxact:direction></ipxact:wire> |
</ipxact:port> |
|
|
<spirit:port><spirit:name>cyc</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
</ipxact:ports> |
|
<spirit:port><spirit:name>stb</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
</ipxact:model> |
|
<spirit:port><spirit:name>we</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>sel</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>dwidth/8-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>din</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>ack</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:fileSets> |
|
<spirit:port><spirit:name>err</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rty</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<ipxact:fileSet> |
<ipxact:name>fs-sim</ipxact:name> |
|
<ipxact:file> |
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../verilog/sim/</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType> |
</ipxact:file> |
|
</spirit:ports> |
</ipxact:fileSet> |
|
</spirit:model> |
<ipxact:fileSet> |
<ipxact:name>fs-syn</ipxact:name> |
|
|
<ipxact:file> |
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../verilog/syn/</ipxact:name> |
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType> |
</ipxact:file> |
|
|
</ipxact:fileSet> |
|
|
</ipxact:fileSets> |
|
|
</spirit:component> |
|
|
|
</ipxact:component> |