URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/Projects/opencores.org/wishbone/ip/wb_memory/sim/testbenches/xml
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/wb_memory_def_dutg.design.xml
File deleted
/wb_memory_def_tb.xml
57,15 → 57,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
<spirit:value>wb_memory_def_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
176,7 → 169,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/wb_memory_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
193,7 → 186,7
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/wb_memory_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/wb_memory_def_lint.xml
40,49 → 40,8
<spirit:version>def_lint</spirit:version> |
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:model> |
|
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/wb_memory_def_dut.params.xml
34,7 → 34,7
<spirit:modelParameter><spirit:name>wb_data_width</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>wb_byte_lanes</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>dat_width</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>adr_width</spirit:name><spirit:value>12</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>adr_width</spirit:name><spirit:value>14</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>mem_size</spirit:name><spirit:value>16384</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SRAM_MEM_0_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SRAM_MEM_1_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter> |