OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550
    from Rev 131 to Rev 133
    Reverse comparison

Rev 131 → Rev 133

/rtl/xml/wb_uart16550_def.xml
166,10 → 166,26
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/rtl/xml/wb_uart16550_bus32_big.xml
167,9 → 167,30
<spirit:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/rtl/xml/wb_uart16550_bus16_big.xml
167,8 → 167,25
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/rtl/xml/wb_uart16550_bus32_lit.xml
166,9 → 166,27
 
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/rtl/xml/wb_uart16550_bus16_lit.xml
166,9 → 166,27
 
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_registers</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_registers</spirit:generatorExe>
/sim/testbenches/xml/wb_uart16550_def_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="wishbone"
spirit:name="wb_uart16550"
spirit:version="def_dutg.design"/>
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/sim/testbenches/xml/wb_uart16550_bus32_lit_lint.xml
39,10 → 39,47
<spirit:name>wb_uart16550</spirit:name>
<spirit:version>bus32_lit_lint</spirit:version>
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
 
/sim/testbenches/xml/wb_uart16550_bus16_lit_tb.xml
49,37 → 49,6
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
 
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>wb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
/sim/testbenches/xml/wb_uart16550_bus16_lit_lint.xml
43,9 → 43,46
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:model>
 
 
/sim/testbenches/xml/wb_uart16550_bus32_lit_duth.design.xml
0,0 → 1,156
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_uart16550 -version bus32_lit //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>wb_uart16550</spirit:name>
<spirit:version>bus32_lit_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>baud_o</spirit:name>
<spirit:externalPortReference spirit:portRef="baud_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="baud_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dcd_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dcd_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dcd_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dsr_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dsr_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dsr_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dtr_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="dtr_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dtr_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_o</spirit:name>
<spirit:externalPortReference spirit:portRef="int_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ri_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="ri_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ri_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>srx_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="srx_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="srx_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>stx_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="stx_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="stx_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_ack_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_ack_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_ack_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_adr_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_adr_i" spirit:left="7" spirit:right="2" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_adr_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_clk_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_clk_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_clk_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_cyc_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_cyc_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_cyc_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_i" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_o" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_rst_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_rst_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_rst_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_sel_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_sel_i" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_sel_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_stb_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_stb_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_stb_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_we_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_we_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_we_i" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wb_uart16550" spirit:version="bus32_lit" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PRESCALER_PRESET">PRESCALER_PRESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_addr_width">wb_addr_width</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_byte_lanes">wb_byte_lanes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_data_width">wb_data_width</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/testbenches/xml/wb_uart16550_bus16_lit_duth.design.xml
0,0 → 1,156
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_uart16550 -version bus16_lit //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>wb_uart16550</spirit:name>
<spirit:version>bus16_lit_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>baud_o</spirit:name>
<spirit:externalPortReference spirit:portRef="baud_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="baud_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dcd_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dcd_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dcd_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dsr_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dsr_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dsr_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dtr_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="dtr_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dtr_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_o</spirit:name>
<spirit:externalPortReference spirit:portRef="int_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ri_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="ri_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ri_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>srx_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="srx_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="srx_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>stx_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="stx_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="stx_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_ack_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_ack_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_ack_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_adr_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_adr_i" spirit:left="7" spirit:right="1" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_adr_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_clk_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_clk_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_clk_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_cyc_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_cyc_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_cyc_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_i" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_o" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_rst_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_rst_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_rst_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_sel_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_sel_i" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_sel_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_stb_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_stb_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_stb_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_we_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_we_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_we_i" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wb_uart16550" spirit:version="bus16_lit" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PRESCALER_PRESET">PRESCALER_PRESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_addr_width">wb_addr_width</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_byte_lanes">wb_byte_lanes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_data_width">wb_data_width</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/testbenches/xml/wb_uart16550_bus32_big_tb.xml
48,36 → 48,8
<spirit:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>wb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
/sim/testbenches/xml/wb_uart16550_bus32_lit_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="wishbone"
spirit:name="wb_uart16550"
spirit:version="bus32_lit_dutg.design"/>
spirit:version="bus32_lit_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/sim/testbenches/xml/wb_uart16550_bus32_big_lint.xml
41,11 → 41,48
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
 
/sim/testbenches/xml/wb_uart16550_bus16_big_tb.xml
50,37 → 50,8
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>wb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
/sim/testbenches/xml/wb_uart16550_bus16_lit_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="wishbone"
spirit:name="wb_uart16550"
spirit:version="bus16_lit_dutg.design"/>
spirit:version="bus16_lit_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/sim/testbenches/xml/wb_uart16550_bus16_big_lint.xml
41,10 → 41,47
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
 
 
/sim/testbenches/xml/wb_uart16550_bus32_big_duth.design.xml
0,0 → 1,156
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_uart16550 -version bus32_big //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>wb_uart16550</spirit:name>
<spirit:version>bus32_big_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>baud_o</spirit:name>
<spirit:externalPortReference spirit:portRef="baud_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="baud_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dcd_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dcd_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dcd_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dsr_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dsr_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dsr_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dtr_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="dtr_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dtr_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_o</spirit:name>
<spirit:externalPortReference spirit:portRef="int_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ri_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="ri_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ri_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>srx_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="srx_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="srx_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>stx_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="stx_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="stx_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_ack_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_ack_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_ack_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_adr_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_adr_i" spirit:left="7" spirit:right="2" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_adr_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_clk_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_clk_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_clk_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_cyc_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_cyc_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_cyc_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_i" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_o" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_rst_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_rst_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_rst_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_sel_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_sel_i" spirit:left="3" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_sel_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_stb_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_stb_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_stb_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_we_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_we_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_we_i" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wb_uart16550" spirit:version="bus32_big" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PRESCALER_PRESET">PRESCALER_PRESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_addr_width">wb_addr_width</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_byte_lanes">wb_byte_lanes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_data_width">wb_data_width</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/testbenches/xml/wb_uart16550_bus32_big_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="wishbone"
spirit:name="wb_uart16550"
spirit:version="bus32_big_dutg.design"/>
spirit:version="bus32_big_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/sim/testbenches/xml/wb_uart16550_bus16_big_duth.design.xml
0,0 → 1,156
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_uart16550 -version bus16_big //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>wb_uart16550</spirit:name>
<spirit:version>bus16_big_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>baud_o</spirit:name>
<spirit:externalPortReference spirit:portRef="baud_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="baud_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dcd_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dcd_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dcd_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dsr_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dsr_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dsr_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dtr_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="dtr_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dtr_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_o</spirit:name>
<spirit:externalPortReference spirit:portRef="int_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ri_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="ri_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ri_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>srx_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="srx_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="srx_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>stx_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="stx_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="stx_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_ack_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_ack_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_ack_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_adr_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_adr_i" spirit:left="7" spirit:right="1" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_adr_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_clk_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_clk_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_clk_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_cyc_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_cyc_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_cyc_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_i" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_o" spirit:left="15" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_rst_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_rst_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_rst_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_sel_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_sel_i" spirit:left="1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_sel_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_stb_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_stb_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_stb_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_we_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_we_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_we_i" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wb_uart16550" spirit:version="bus16_big" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PRESCALER_PRESET">PRESCALER_PRESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_addr_width">wb_addr_width</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_byte_lanes">wb_byte_lanes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_data_width">wb_data_width</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/testbenches/xml/wb_uart16550_bus16_big_dut.params.xml
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// //
// regen by adding -tb to gen_verilog script //
// //
// //
-->
<spirit:component
26,7 → 26,7
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="wishbone"
spirit:name="wb_uart16550"
spirit:version="bus16_big_dutg.design"/>
spirit:version="bus16_big_duth.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
/sim/testbenches/xml/wb_uart16550_def_tb.xml
48,56 → 48,6
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>wb</spirit:value>
</spirit:parameter>
</spirit:parameters>
 
</spirit:componentGenerator>
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_header</spirit:name>
<spirit:phase>102.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>headers</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/regtool/gen_header</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>inst_path</spirit:name>
<spirit:value>dut.wb</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../../../sw/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
/sim/testbenches/xml/wb_uart16550_def_lint.xml
41,11 → 41,48
 
 
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
 
/sim/testbenches/xml/wb_uart16550_def_duth.design.xml
0,0 → 1,156
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_uart16550 -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>wb_uart16550</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>baud_o</spirit:name>
<spirit:externalPortReference spirit:portRef="baud_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="baud_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>cts_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="cts_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="cts_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dcd_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dcd_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dcd_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dsr_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="dsr_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dsr_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dtr_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="dtr_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dtr_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>int_o</spirit:name>
<spirit:externalPortReference spirit:portRef="int_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="int_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>ri_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="ri_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ri_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>rts_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="rts_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="rts_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>srx_pad_i</spirit:name>
<spirit:externalPortReference spirit:portRef="srx_pad_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="srx_pad_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>stx_pad_o</spirit:name>
<spirit:externalPortReference spirit:portRef="stx_pad_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="stx_pad_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_ack_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_ack_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_ack_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_adr_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_adr_i" spirit:left="wb_addr_width-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_adr_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_clk_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_clk_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_clk_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_cyc_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_cyc_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_cyc_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_i" spirit:left="wb_data_width-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_dat_o</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_dat_o" spirit:left="wb_data_width-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_dat_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_rst_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_rst_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_rst_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_sel_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_sel_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_sel_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_stb_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_stb_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_stb_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>wb_we_i</spirit:name>
<spirit:externalPortReference spirit:portRef="wb_we_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="wb_we_i" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wb_uart16550" spirit:version="def" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PRESCALER_PRESET">PRESCALER_PRESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_addr_width">wb_addr_width</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_byte_lanes">wb_byte_lanes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="wb_data_width">wb_data_width</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/testbenches/xml/wb_uart16550_bus32_lit_tb.xml
50,37 → 50,9
 
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>trace_bus</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/trace_bus</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>path</spirit:name>
<spirit:value>root.dut</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bus_name</spirit:name>
<spirit:value>wb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>

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