URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/Testbench/bfms/clock_gen/rtl/xml
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/clock_gen_def.xml
52,7 → 52,7
<spirit:portMap> |
<spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
</spirit:physicalPort> |
</spirit:portMap> |
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87,38 → 87,36
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<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gen_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
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</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gen_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
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</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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132,39 → 130,24
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:model> |
<spirit:views> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
245,11 → 228,87
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gen_sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/clock_gen_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gen_syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/clock_gen_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |
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