OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/Testbench/bfms/clock_gen/rtl
    from Rev 133 to Rev 134
    ↔ Reverse comparison
  •

Rev 133 → Rev 134

/xml/clock_gen_def.xml
52,7 → 52,7
<spirit:portMap>
<spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
</spirit:physicalPort>
</spirit:portMap>
 
87,38 → 87,36
 
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:name>gen_verilog_sim</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
<spirit:name>destination</spirit:name>
<spirit:value>clock_gen_def</spirit:value>
</spirit:parameter>
</spirit:parameters>
 
</spirit:componentGenerator>
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:name>gen_verilog_syn</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
<spirit:name>destination</spirit:name>
<spirit:value>clock_gen_def</spirit:value>
</spirit:parameter>
</spirit:parameters>
 
</spirit:componentGenerator>
 
 
 
</spirit:componentGenerators>
 
 
132,39 → 130,24
 
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:model>
<spirit:views>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
245,11 → 228,87
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/clock_gen_sim</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/clock_gen_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/clock_gen_syn</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/clock_gen_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
</spirit:component>
 
 
/verilog/sim/clock_gen_def.v File deleted
/verilog/syn/clock_gen_def.v File deleted
/verilog/copyright
0,0 → 1,43
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Clock and Reset generator for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
/verilog/clock_gen_sim
0,0 → 1,80
reg task_reset;
reg task_FAIL;
reg task_FINISH;
 
always@(posedge clk or negedge START)
if(!START) FINISH <= 0;
else FINISH <= (|STOP) || FINISH || task_FINISH;
 
 
 
always@(posedge clk or negedge START)
if(!START) FAIL <= 0;
else FAIL <= task_FAIL || (|BAD);
 
always@(posedge clk or negedge START)
if(!START) reset <= 1'b1;
else reset <= task_reset;
 
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
 
 
 
 
 
initial
begin
task_FINISH <= 0;
task_FAIL <= 0;
task_reset <= 0;
end
 
task reset_on;
task_reset = 1;
endtask // reset_on
 
task reset_off;
begin
task_reset = 0;
end
endtask // reset_off
 
 
task automatic fail;
input [799:0] message;
begin
task_FAIL <= 1;
$display("%t Simulation FAILURE: %s ",$realtime,message );
@(posedge clk);
task_FAIL <= 0;
end
endtask
 
task exit;
begin
@(posedge clk);
task_FINISH <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask
 
 
 
/verilog/clock_gen_syn
0,0 → 1,16
always@(posedge clk or negedge START)
if(!START) FINISH <= 0;
else FINISH <= (|STOP) || FINISH;
 
 
 
always@(posedge clk or negedge START)
if(!START) FAIL <= 0;
else FAIL <= (|BAD);
 
always@(posedge clk or negedge START)
if(!START) reset <= 1'b1;
else reset <= 1'b0;

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