URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/Testbench/bfms/uart_host/rtl
- from Rev 131 to Rev 134
- ↔ Reverse comparison
Rev 131 → Rev 134
/xml/uart_host_def.xml
41,7 → 41,44
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>uart_host_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>uart_host_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
80,75 → 117,22
</spirit:componentGenerators> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
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<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:name="uart_host" |
spirit:version="def.design"/> |
</spirit:view> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
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199,6 → 183,28
</spirit:port> |
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<spirit:port><spirit:name>txd_data_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire> |
<spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector> |
</spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>rxd_data_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector> |
</spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>parity_enable</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
219,6 → 225,38
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>txd_load</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>txd_break</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>rxd_parity</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>rxd_force_parity</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>rxd_data_avail_stb</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>rxd_data_avail</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
236,22 → 274,95
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output reg [7:0] txd_data_in, |
output reg txd_load, |
output reg txd_break, |
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
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</spirit:ports> |
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</spirit:model> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/code</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/uart_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/code</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/uart_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |
/xml/uart_host_def.design.xml
0,0 → 1,209
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>uart_host</spirit:name> |
<spirit:version>def.design</spirit:version> |
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<spirit:vendorExtensions> |
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<socgen:nodes> |
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<socgen:node><spirit:name>exp_rxd_data_out</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
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<socgen:node><spirit:name>mask_rxd_data_out</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
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<socgen:node><spirit:name>exp_rxd_parity_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
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<socgen:node><spirit:name>mask_rxd_parity_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
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<socgen:node><spirit:name>exp_rxd_stop_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
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<socgen:node><spirit:name>mask_rxd_stop_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
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</socgen:nodes> |
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</spirit:vendorExtensions> |
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<spirit:adHocConnections> |
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<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="clk"/> |
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</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>exp_rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>exp_rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>exp_rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>mask_rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>mask_rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>mask_rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
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<spirit:adHocConnection> |
<spirit:name>rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
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</spirit:adHocConnections> |
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<spirit:componentInstances> |
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<spirit:componentInstance> |
<spirit:instanceName>rxd_data_out_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
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<spirit:componentInstance> |
<spirit:instanceName>rxd_stop_error_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host stop Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
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<spirit:componentInstance> |
<spirit:instanceName>rxd_parity_error_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host parity Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
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</spirit:componentInstances> |
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</spirit:design> |
/verilog/copyright.v
File deleted
/verilog/tasks
0,0 → 1,60
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task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
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task clear_rx_host; |
begin |
next(1); |
end |
endtask |
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task send_byte; |
input [7:0] byte_out; |
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begin |
while(!txd_buffer_empty) next(1); |
$display("%t %m %2h",$realtime ,byte_out); |
txd_data_in <= byte_out; |
next(1); |
txd_load <= 1'b1; |
next(1); |
txd_load <= 1'b0; |
next(1); |
end |
endtask // send_byte |
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task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rxd_data_out <= byte_in; |
while(!rxd_data_avail) next(1); |
$display("%t %m checking %h",$realtime,byte_in); |
mask_rxd_stop_error <= 1'b1; |
mask_rxd_parity_error <= 1'b1; |
mask_rxd_data_out <= 8'hff; |
next(1); |
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
rxd_data_avail_stb <= 1'b1; |
next(1); |
rxd_data_avail_stb <= 1'b0; |
next(1); |
end |
endtask |
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/verilog/copyright
0,0 → 1,43
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/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* uart host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/verilog/top.sim
47,40 → 47,70
module uart_host_def ( |
input wire clk, |
input wire reset, |
output reg parity_enable, |
output reg txd_parity, |
input wire rxd_data_avail, |
input wire rxd_stop_error, |
input wire rxd_parity_error, |
input wire txd_buffer_empty, |
input wire [7:0] rxd_data_out, |
output reg parity_enable, |
output reg rxd_data_avail_stb, |
output reg rxd_force_parity, |
output reg rxd_parity, |
output reg txd_break, |
output reg txd_force_parity, |
output reg [7:0] txd_data_in, |
input wire txd_buffer_empty, |
output reg txd_load, |
output reg txd_break, |
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
input wire rxd_data_avail, |
inout wire rxd_stop_error, |
inout wire rxd_parity_error |
output reg txd_parity, |
output reg [7:0] txd_data_in |
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); |
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reg exp_rxd_stop_error; |
reg exp_rxd_parity_error; |
reg exp_rxd_stop_error; |
reg exp_rxd_parity_error; |
reg [7:0] exp_rxd_data_out; |
|
reg mask_rxd_stop_error; |
reg mask_rxd_parity_error; |
reg mask_rxd_stop_error; |
reg mask_rxd_parity_error; |
reg [7:0] mask_rxd_data_out; |
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task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
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io_probe_in |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
); |
|
io_probe_in |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
); |
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io_probe_in |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
|
|
); |
|
|
always@(posedge clk) |
if(reset) |
106,6 → 136,17
end |
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|
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|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
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|
|
task clear_rx_host; |
begin |
next(1); |
152,60 → 193,6
end |
endtask |
|
|
io_probe_def |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
|
|
); |
|
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|
|
|
|
io_probe_def |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
|
|
); |
|
|
|
|
io_probe_def |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
|
|
); |
|
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|
endmodule |
|
/verilog/top.syn
57,10 → 57,10
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
input wire [7:0] rxd_data_out, |
input wire rxd_data_avail, |
inout wire rxd_stop_error, |
inout wire rxd_parity_error |
input wire rxd_stop_error, |
input wire rxd_parity_error |
); |
|
reg exp_rxd_stop_error; |
73,44 → 73,12
|
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|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
|
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
|
|
end |
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
123,12 → 91,11
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
139,12 → 106,11
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.clk ( clk ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
152,8 → 118,34
|
); |
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
|
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
|
|
end |
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|
/verilog/code
0,0 → 1,26
assign drive_8 = 8'bzzzzzzzz; |
assign drive_1 = 1'bz; |
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
end |
|