OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

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Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/Testbench/bfms/uart_model
    from Rev 133 to Rev 134
    ↔ Reverse comparison
  •

Rev 133 → Rev 134

/rtl/xml/uart_model_def.xml
46,23 → 46,7
 
 
<spirit:componentGenerators>
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog_sim</spirit:name>
<spirit:phase>104.0</spirit:phase>
72,12 → 56,8
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.out.sim</spirit:value>
<spirit:value>uart_model_def</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
91,57 → 71,121
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.out.syn</spirit:value>
<spirit:value>uart_model_def</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
</spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>Hierarchical</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="uart_model"
spirit:version="def.design"/>
</spirit:view>
 
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
</spirit:views>
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>CLKCNT</spirit:name><spirit:value>4'h5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>txd_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>rxd_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
</spirit:ports>
 
</spirit:model>
 
 
 
 
 
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
149,31 → 193,32
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright.v</spirit:name>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.out.sim</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:name>../verilog/top.tasks</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.tasks</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
<spirit:name>../verilog/sim/uart_model_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_rcvr</spirit:name>
216,30 → 261,34
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright.v</spirit:name>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.out.syn</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
<spirit:name>../verilog/serial_rcvr</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_rcvr</spirit:name>
<spirit:name>../verilog/syn/uart_model_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_xmit</spirit:name>
273,101 → 322,10
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>Hierarchical</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="uart_model"
spirit:version="def.design"/>
</spirit:view>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
</spirit:views>
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>CLKCNT</spirit:name><spirit:value>4'h5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>txd_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>rxd_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
</spirit:ports>
 
</spirit:model>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
</spirit:component>
/rtl/verilog/copyright.v File deleted
/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Clock and Reset generator for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 

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