URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/Testbench/bfms
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/mt45w8mw12/rtl/xml/mt45w8mw12_def.xml
48,40 → 48,32
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>mt45w8mw12_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>mt45w8mw12_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
88,68 → 80,25
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
268,10 → 217,80
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/mt45w8mw12_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/mt45w8mw12_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |
/mt45w8mw12/rtl/verilog/copyright.v
File deleted
/mt45w8mw12/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* psram behavioral model for sims */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/mt45w8mw12/rtl/verilog/top.sim
1,26 → 1,5
|
|
module mt45w8mw12_def |
#( |
parameter ADDR_BITS = 23, |
parameter DQ_BITS = 16, |
parameter MEM_BITS = 16 |
) |
|
( |
input wire clk, |
input wire adv_n, |
input wire cre, |
output wire o_wait, |
input wire ce_n, |
input wire oe_n, |
input wire we_n, |
input wire lb_n, |
input wire ub_n, |
input wire [ADDR_BITS-1 : 0] addr, |
inout wire [DQ_BITS-1 : 0] dq |
); |
|
reg [7:0] memoryl [1<<MEM_BITS-1:0]; |
reg [7:0] memoryu [1<<MEM_BITS-1:0]; |
|
49,6 → 28,5
|
|
|
endmodule |
|
|
/mt45w8mw12/rtl/verilog/top.syn
1,27 → 1,4
|
|
module mt45w8mw12_def |
#( |
parameter ADDR_BITS = 23, |
parameter DQ_BITS = 16, |
parameter MEM_BITS = 16 |
|
) |
|
( |
input wire clk, |
input wire adv_n, |
input wire cre, |
output wire o_wait, |
input wire ce_n, |
input wire oe_n, |
input wire we_n, |
input wire lb_n, |
input wire ub_n, |
input wire [ADDR_BITS-1 : 0] addr, |
inout wire [DQ_BITS-1 : 0] dq |
); |
|
reg [7:0] memoryl [1<<MEM_BITS-1:0]; |
reg [7:0] memoryu [1<<MEM_BITS-1:0]; |
|
44,6 → 21,3
|
|
|
endmodule |
|
|
/or1200_dbg_model/rtl/xml/or1200_dbg_model_def.xml
320,14 → 320,6
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:version="in.design"/> |
</spirit:view> |
|
|
|
/ps2_host/componentCfg.xml
26,6 → 26,6
</socgen:doc> |
|
|
</socgen:componentConfiguration> |
|
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</socgen:componentConfiguration> |
|
/ps2_host/rtl/xml/ps2_host_def.design.xml
0,0 → 1,168
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>ps2_host</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
<socgen:node><spirit:name>exp_rcv_byte</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
|
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|
<socgen:node><spirit:name>mask_rcv_byte</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
|
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<socgen:node><spirit:name>exp_tx_ack_err</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
<socgen:node><spirit:name>mask_tx_ack_err</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
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|
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
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|
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<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>exp_rcv_byte</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rcv_byte" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_tx_ack_err</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_tx_ack_err" /> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>mask_rcv_byte</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rcv_byte" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mask_tx_ack_err</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_tx_ack_err" /> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_ack_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_ack_error" /> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
|
<spirit:componentInstances> |
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|
<spirit:componentInstance> |
<spirit:instanceName>tx_ack_err_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2_host tx_ack Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>rcv_byte_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2_host receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/ps2_host/rtl/xml/ps2_host_def.xml
41,119 → 41,78
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>ps2_host_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>ps2_host_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="ps2_host" |
spirit:version="def.design"/> |
</spirit:view> |
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
163,7 → 122,6
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
231,6 → 189,11
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>tx_ack_error</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rx_frame_error</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
237,31 → 200,108
</spirit:port> |
|
<spirit:port><spirit:name>rx_clr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>tx_write</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>tx_write</spirit:name> |
<spirit:port> |
<spirit:name>tx_data</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port> |
<spirit:name>rx_data</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
<spirit:wire><spirit:direction>in</spirit:direction><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
|
</spirit:ports> |
|
</spirit:model> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/ps2_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/ps2_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
</spirit:component> |
/ps2_host/rtl/verilog/copyright.v
File deleted
/ps2_host/rtl/verilog/tasks
0,0 → 1,53
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
task clear_rx_host; |
begin |
rx_clr <= 1'b1; |
next(1); |
rx_clr <= 1'b0; |
end |
endtask |
|
|
|
|
task send_byte; |
input [7:0] byte_out; |
begin |
$display("%t %m %2h",$realtime ,byte_out ); |
tx_data <= byte_out; |
next(1); |
tx_write <= 1'b1; |
next(1); |
tx_write <= 1'b0; |
next(1); |
while(busy) next(1); |
mask_tx_ack_err <= 1'b1; |
next(1); |
mask_tx_ack_err <= 1'b0; |
end |
endtask // send_byte |
|
|
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rcv_byte <= byte_in; |
|
while(!rx_read) next(1); |
$display("%t checking %h",$realtime,byte_in); |
mask_rcv_byte <= 8'hff; |
next(1); |
mask_rcv_byte <= 8'h00; |
end |
endtask |
|
|
|
/ps2_host/rtl/verilog/copyright
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* ps2 host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/ps2_host/rtl/verilog/top.sim
1,49 → 1,3
|
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* ps2 host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
module ps2_host_def |
|
( |
51,7 → 5,7
input wire reset, |
input wire busy, |
|
inout wire [7:0] rx_data, |
input wire [7:0] rx_data, |
input wire rx_read, |
input wire rx_full, |
input wire rx_parity_error, |
65,21 → 19,53
output reg tx_write |
); |
|
|
reg exp_tx_ack_err; |
reg mask_tx_ack_err; |
|
reg [7:0] exp_rcv_byte; |
reg [7:0] mask_rcv_byte; |
|
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
io_probe_in |
#( .MESG("ps2_host tx_ack error") |
) |
tx_ack_err_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_tx_ack_err ), |
.mask ( mask_tx_ack_err ), |
.signal ( tx_ack_error ) |
); |
|
|
|
|
|
|
|
|
|
io_probe_in |
#( .MESG("ps2_host receive error"), |
.WIDTH (8) |
) |
rcv_byte_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_rcv_byte ), |
.mask ( mask_rcv_byte ), |
.signal ( rx_data ) |
); |
|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
90,12 → 76,19
mask_tx_ack_err <= 1'b0; |
exp_rcv_byte <= 8'h00; |
mask_rcv_byte <= 8'h00; |
end |
|
|
|
end |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
task clear_rx_host; |
begin |
rx_clr <= 1'b1; |
105,7 → 98,19
endtask |
|
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rcv_byte <= byte_in; |
|
while(!rx_read) next(1); |
$display("%t checking %h",$realtime,byte_in); |
mask_rcv_byte <= 8'hff; |
next(1); |
mask_rcv_byte <= 8'h00; |
end |
endtask |
|
task send_byte; |
input [7:0] byte_out; |
127,53 → 132,6
|
|
|
io_probe_def |
#( .MESG("ps2_host tx_ack error") |
) |
tx_ack_err_tpb |
( |
.clk ( clk ), |
.drive_value ( 1'bz ), |
.expected_value ( exp_tx_ack_err ), |
.mask ( mask_tx_ack_err ), |
.signal ( tx_ack_error ) |
); |
|
|
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rcv_byte <= byte_in; |
|
while(!rx_read) next(1); |
$display("%t checking %h",$realtime,byte_in); |
mask_rcv_byte <= 8'hff; |
next(1); |
mask_rcv_byte <= 8'h00; |
end |
endtask |
|
|
|
|
io_probe_def |
#( .MESG("ps2_host receive error"), |
.WIDTH (8) |
) |
rcv_byte_tpb |
( |
.clk ( clk ), |
.drive_value ( {8{1'bz}} ), |
.expected_value ( exp_rcv_byte ), |
.mask ( mask_rcv_byte ), |
.signal ( rx_data ) |
); |
|
|
|
|
endmodule |
|
/ps2_host/rtl/verilog/top.syn
1,49 → 1,3
|
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* ps2 host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
module ps2_host_def |
|
( |
51,7 → 5,7
input wire reset, |
input wire busy, |
|
inout wire [7:0] rx_data, |
input wire [7:0] rx_data, |
input wire rx_read, |
input wire rx_full, |
input wire rx_parity_error, |
73,9 → 27,6
reg [7:0] mask_rcv_byte; |
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
/ps2_host/rtl/verilog/logic
0,0 → 1,14
always@(posedge clk) |
if(reset) |
begin |
tx_data <= 8'h00; |
tx_write <= 1'b0; |
rx_clr <= 1'b0; |
exp_tx_ack_err <= 1'b0; |
mask_tx_ack_err <= 1'b0; |
exp_rcv_byte <= 8'h00; |
mask_rcv_byte <= 8'h00; |
end |
|
|
|
/micro_bus_model/rtl/xml/micro_bus_model_def.xml
99,30 → 99,9
|
</spirit:busInterfaces> |
|
|
|
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
131,12 → 110,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>micro_bus_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
152,57 → 127,12
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>micro_bus_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
|
226,7 → 156,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top</spirit:name> |
<spirit:name>../verilog/sim/micro_bus_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
259,7 → 189,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top</spirit:name> |
<spirit:name>../verilog/syn/micro_bus_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
293,6 → 223,23
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
/clock_gen/rtl/xml/clock_gen_def.xml
52,7 → 52,7
<spirit:portMap> |
<spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
</spirit:physicalPort> |
</spirit:portMap> |
|
87,38 → 87,36
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gen_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gen_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
132,39 → 130,24
|
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
245,11 → 228,87
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gen_sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/clock_gen_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gen_syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/clock_gen_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
</spirit:fileSets> |
|
|
|
|
|
|
</spirit:component> |
|
|
/clock_gen/rtl/verilog/sim/clock_gen_def.v
File deleted
/clock_gen/rtl/verilog/syn/clock_gen_def.v
File deleted
/clock_gen/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/clock_gen/rtl/verilog/clock_gen_sim
0,0 → 1,80
reg task_reset; |
reg task_FAIL; |
reg task_FINISH; |
|
|
always@(posedge clk or negedge START) |
if(!START) FINISH <= 0; |
else FINISH <= (|STOP) || FINISH || task_FINISH; |
|
|
|
always@(posedge clk or negedge START) |
if(!START) FAIL <= 0; |
else FAIL <= task_FAIL || (|BAD); |
|
|
always@(posedge clk or negedge START) |
if(!START) reset <= 1'b1; |
else reset <= task_reset; |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask // next |
|
|
|
|
|
initial |
begin |
task_FINISH <= 0; |
task_FAIL <= 0; |
task_reset <= 0; |
end |
|
|
|
task reset_on; |
task_reset = 1; |
endtask // reset_on |
|
task reset_off; |
begin |
task_reset = 0; |
end |
endtask // reset_off |
|
|
|
|
task automatic fail; |
input [799:0] message; |
begin |
task_FAIL <= 1; |
$display("%t Simulation FAILURE: %s ",$realtime,message ); |
@(posedge clk); |
task_FAIL <= 0; |
end |
endtask |
|
task exit; |
begin |
@(posedge clk); |
task_FINISH <= 1; |
@(posedge clk); |
@(posedge clk); |
@(posedge clk); |
@(posedge clk); |
end |
endtask |
|
|
|
|
|
/clock_gen/rtl/verilog/clock_gen_syn
0,0 → 1,16
|
always@(posedge clk or negedge START) |
if(!START) FINISH <= 0; |
else FINISH <= (|STOP) || FINISH; |
|
|
|
always@(posedge clk or negedge START) |
if(!START) FAIL <= 0; |
else FAIL <= (|BAD); |
|
|
always@(posedge clk or negedge START) |
if(!START) reset <= 1'b1; |
else reset <= 1'b0; |
|
/ps2_model/componentCfg.xml
27,4 → 27,21
|
|
|
<socgen:configurations> |
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>CLKCNT</socgen:name><socgen:value>10'h1f0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>10</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
</socgen:configurations> |
|
|
|
|
</socgen:componentConfiguration> |
/ps2_model/rtl/xml/ps2_model_def.xml
39,29 → 39,8
<spirit:name>ps2_model</spirit:name> |
<spirit:version>def</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
|
<spirit:componentGenerators> |
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
71,12 → 50,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>ps2_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
90,54 → 65,13
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>ps2_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
|
149,13 → 83,13
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:name>../verilog/sim/ps2_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
191,7 → 125,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
198,7 → 132,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:name>../verilog/syn/ps2_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
240,6 → 174,24
spirit:version="def.design"/> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
/ps2_model/rtl/verilog/copyright.v
File deleted
/ps2_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/display_model/componentCfg.xml
27,4 → 27,5
|
|
|
|
</socgen:componentConfiguration> |
/display_model/rtl/xml/display_model_def.xml
39,184 → 39,57
<spirit:name>display_model</spirit:name> |
<spirit:version>def</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>display_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
<spirit:model> |
<spirit:views> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
309,11 → 182,93
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/display_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/display_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/display_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/jtag_model/componentCfg.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
28,6 → 28,20
</socgen:doc> |
|
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>DIVCNT</socgen:name><socgen:value>4'h1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
</socgen:configurations> |
|
|
</socgen:componentConfiguration> |
/jtag_model/rtl/xml/jtag_model_def.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
46,9 → 46,23
|
|
<spirit:componentGenerators> |
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_model_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
100,9 → 114,24
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_model</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_model_def.v</spirit:name> |
<spirit:name>../verilog/sim/jtag_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
126,7 → 155,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_model_def.v</spirit:name> |
<spirit:name>../verilog/sim/jtag_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
152,8 → 181,21
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
/jtag_model/rtl/verilog/jtag_model
0,0 → 1,172
reg tclk_enable; |
reg [SIZE-1:0] tclk_counter; |
wire next_tclk_edge; |
wire next_tclk_pos_edge; |
wire next_tclk_neg_edge; |
assign next_tclk_edge = (tclk_counter == 4'h0); |
assign next_tclk_pos_edge = next_tclk_edge && (!tclk) ; |
assign next_tclk_neg_edge = next_tclk_edge && ( tclk) ; |
always@(posedge clk) |
if(reset) tclk_counter <= DIVCNT; |
else |
if(|tclk_counter) tclk_counter <= tclk_counter-4'h1; |
else tclk_counter <= DIVCNT; |
always@(posedge clk) |
if(reset) tclk <= 1'b0; |
else |
if(!tclk_enable) tclk <= tclk; |
else |
if( next_tclk_pos_edge ) tclk <= 1'b1; |
else |
if( next_tclk_neg_edge ) tclk <= 1'b0; |
else tclk <= tclk; |
|
reg actual; |
initial |
begin |
tclk_enable <= 1'b0; |
tclk <= 1'b0; |
tdo <= 1'b1; |
tms <= 1'b1; |
trst_n <= 1'b0; |
end |
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
task enable_tclk; |
begin |
tclk_enable <= 1'b1; |
end |
endtask |
task enable_trst_n; |
begin |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
trst_n <= 1'b1; |
Clk_bit(1,1,actual); |
end |
endtask |
task enable_reset; |
begin |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
end |
endtask |
task init; |
begin |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
end |
endtask |
|
task Clk_bit; |
input TMS; |
input TDO; |
output ACT; |
begin |
while (next_tclk_neg_edge != 1) |
begin |
next(1); |
end |
if(TMS) tms <= 1'b1; |
else tms <= 1'b0; |
if ( TDO == 1 ) tdo <= 1'b1; |
else if( TDO == 0 ) tdo <= 1'b0; |
else tdo <= 1'bx; |
while (next_tclk_pos_edge != 1) |
begin |
next(1); |
end |
ACT = tdi; |
end |
endtask |
/******************************************************************************/ |
/* LoadTapInst (<Inst>); */ |
/******************************************************************************/ |
task LoadTapInst; // Load a Tap Instruction that uses the Boundary Register |
parameter [15:0] JTAG_INST_LENGTH = 4; |
input [JTAG_INST_LENGTH:1] Inst; // This task starts & ends with the Tap in the RT_IDLE state |
input [JTAG_INST_LENGTH:1] Inst_Return; // |
integer i; |
reg [JTAG_INST_LENGTH:1] Ack; |
begin |
Clk_bit(1'b1,1'b0,actual); // Transition from RT_IDLE to SELECT_DR |
Clk_bit(1'b1,1'b0,actual); // Transition from SELECT_DR to SELECT_IR |
Clk_bit(1'b0,1'b0,actual); // Transition from SELECT_IR to CAPTURE_IR |
Clk_bit(1'b0,1'b0,actual); // Transition from CAPTURE_IR to SHIFT_IR |
for (i = 1; i <= JTAG_INST_LENGTH; i = i+1) // Shift in Inst |
begin |
Clk_bit(( i == JTAG_INST_LENGTH),Inst[i],Ack[i]); |
end |
$display ("%t %m LoadTapInst %b Expected %b Received %b " ,$realtime,Inst, Inst_Return, Ack ); |
if (Ack !== Inst_Return) |
begin |
cg.fail (" LoadTapInst receive error "); |
end |
Clk_bit(1'b1,1'b0,actual); // Transition from EXIT1_IR to UPDATE_IR |
Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE_IR to RT_IDLE |
end |
endtask // LoadTapInst |
//***************************************************************************/ |
//* Shift Register |
//***************************************************************************/ |
task automatic Shift_Register; // Initialize boundary register with outputs disabled |
// This tasks starts at RT_IDLE and ends at SHIFT_DR |
parameter [15:0] LENGTH = 100; |
input length; |
input [LENGTH:1] Dataout; |
integer length; |
integer i; |
reg [LENGTH:1] DataBack; |
begin |
Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR |
for (i = 1; i <= length; i = i+1) |
Clk_bit((i==length),Dataout[i],DataBack[i]); |
$display ("%t %m Shift_data -%d wr-%h rd-%h ",$realtime,length,Dataout[LENGTH:1],DataBack[LENGTH:1]); |
Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR |
Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE |
end |
endtask // ShiftRegister |
task automatic Shift_Cmp_32; // Initialize boundary register with outputs disabled |
// This tasks starts at RT_IDLE and ends at SHIFT_DR |
parameter [15:0] LENGTH = 32; |
input [LENGTH:1] Dataout; |
input [LENGTH:1] DataExp; |
integer i; |
reg [LENGTH:1] DataBack; |
begin |
Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR |
for (i = 1; i <= LENGTH; i = i+1) |
Clk_bit((i==LENGTH),Dataout[i],DataBack[i]); |
$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack ); |
if (DataBack !== DataExp ) |
begin |
cg.fail (" Shift_cmp receive error "); |
end |
Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR |
Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE |
end |
endtask // ShiftRegister |
|
|
|
/jtag_model/rtl/verilog/copyright.v
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* JTAG Hoset model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010-2015> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/uart_host/rtl/xml/uart_host_def.xml
41,7 → 41,44
|
<spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>uart_host_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>uart_host_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
80,75 → 117,22
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:name="uart_host" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
199,6 → 183,28
</spirit:port> |
|
|
|
|
<spirit:port><spirit:name>txd_data_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire> |
<spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector> |
</spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_data_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector> |
</spirit:wire> |
</spirit:port> |
|
|
|
|
<spirit:port><spirit:name>parity_enable</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
219,6 → 225,38
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>txd_load</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>txd_break</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_parity</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_force_parity</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_data_avail_stb</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
|
|
<spirit:port><spirit:name>rxd_data_avail</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
236,22 → 274,95
|
|
|
output reg [7:0] txd_data_in, |
output reg txd_load, |
output reg txd_break, |
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
|
|
</spirit:ports> |
|
</spirit:model> |
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/code</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/uart_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/code</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/uart_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
</spirit:component> |
/uart_host/rtl/xml/uart_host_def.design.xml
0,0 → 1,209
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>uart_host</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>exp_rxd_data_out</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>mask_rxd_data_out</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>exp_rxd_parity_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
<socgen:node><spirit:name>mask_rxd_parity_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
<socgen:node><spirit:name>exp_rxd_stop_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
<socgen:node><spirit:name>mask_rxd_stop_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
|
|
|
|
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="clk"/> |
|
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>mask_rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mask_rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mask_rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
</spirit:adHocConnections> |
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>rxd_data_out_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>rxd_stop_error_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host stop Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>rxd_parity_error_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host parity Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/uart_host/rtl/verilog/copyright.v
File deleted
/uart_host/rtl/verilog/tasks
0,0 → 1,60
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
|
|
task clear_rx_host; |
begin |
next(1); |
end |
endtask |
|
|
|
|
task send_byte; |
input [7:0] byte_out; |
|
begin |
while(!txd_buffer_empty) next(1); |
$display("%t %m %2h",$realtime ,byte_out); |
txd_data_in <= byte_out; |
next(1); |
txd_load <= 1'b1; |
next(1); |
txd_load <= 1'b0; |
next(1); |
end |
endtask // send_byte |
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rxd_data_out <= byte_in; |
while(!rxd_data_avail) next(1); |
$display("%t %m checking %h",$realtime,byte_in); |
mask_rxd_stop_error <= 1'b1; |
mask_rxd_parity_error <= 1'b1; |
mask_rxd_data_out <= 8'hff; |
next(1); |
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
rxd_data_avail_stb <= 1'b1; |
next(1); |
rxd_data_avail_stb <= 1'b0; |
next(1); |
end |
endtask |
|
|
|
|
/uart_host/rtl/verilog/copyright
0,0 → 1,43
|
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* uart host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/uart_host/rtl/verilog/top.sim
47,40 → 47,70
module uart_host_def ( |
input wire clk, |
input wire reset, |
output reg parity_enable, |
output reg txd_parity, |
input wire rxd_data_avail, |
input wire rxd_stop_error, |
input wire rxd_parity_error, |
input wire txd_buffer_empty, |
input wire [7:0] rxd_data_out, |
output reg parity_enable, |
output reg rxd_data_avail_stb, |
output reg rxd_force_parity, |
output reg rxd_parity, |
output reg txd_break, |
output reg txd_force_parity, |
output reg [7:0] txd_data_in, |
input wire txd_buffer_empty, |
output reg txd_load, |
output reg txd_break, |
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
input wire rxd_data_avail, |
inout wire rxd_stop_error, |
inout wire rxd_parity_error |
output reg txd_parity, |
output reg [7:0] txd_data_in |
|
); |
|
reg exp_rxd_stop_error; |
reg exp_rxd_parity_error; |
reg exp_rxd_stop_error; |
reg exp_rxd_parity_error; |
reg [7:0] exp_rxd_data_out; |
|
reg mask_rxd_stop_error; |
reg mask_rxd_parity_error; |
reg mask_rxd_stop_error; |
reg mask_rxd_parity_error; |
reg [7:0] mask_rxd_data_out; |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
io_probe_in |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
); |
|
io_probe_in |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
); |
|
|
|
|
io_probe_in |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
|
|
); |
|
|
always@(posedge clk) |
if(reset) |
106,6 → 136,17
end |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
|
|
task clear_rx_host; |
begin |
next(1); |
152,60 → 193,6
end |
endtask |
|
|
io_probe_def |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
|
|
); |
|
|
|
|
|
|
io_probe_def |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
|
|
); |
|
|
|
|
io_probe_def |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
|
|
); |
|
|
|
|
|
|
|
endmodule |
|
/uart_host/rtl/verilog/top.syn
57,10 → 57,10
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
input wire [7:0] rxd_data_out, |
input wire rxd_data_avail, |
inout wire rxd_stop_error, |
inout wire rxd_parity_error |
input wire rxd_stop_error, |
input wire rxd_parity_error |
); |
|
reg exp_rxd_stop_error; |
73,44 → 73,12
|
|
|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
|
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
|
|
end |
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
123,12 → 91,11
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
139,12 → 106,11
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.clk ( clk ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
152,8 → 118,34
|
); |
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
|
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
|
|
end |
|
|
|
|
|
|
|
/uart_host/rtl/verilog/code
0,0 → 1,26
assign drive_8 = 8'bzzzzzzzz; |
assign drive_1 = 1'bz; |
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
end |
|
/micro_bus16_model/rtl/xml/micro_bus16_model_def.xml
48,39 → 48,31
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>micro_bus16_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>micro_bus16_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
89,61 → 81,7
|
|
|
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
152,12 → 90,25
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:name="micro_bus16_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
199,8 → 150,8
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>OUT_DELAY</spirit:name><spirit:value>15</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>OUT_WIDTH</spirit:name><spirit:value>10</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DELAY</spirit:name><spirit:value>15</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
250,13 → 201,100
|
<spirit:port><spirit:name>rdata</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>inout</spirit:direction> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>cs</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/micro_bus16_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/micro_bus16_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
</spirit:component> |
/micro_bus16_model/rtl/xml/micro_bus16_model_def.design.xml
0,0 → 1,133
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>micro_bus16_model</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>exp_rdata</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>mask_rdata</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>mask_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>rdata_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"micro 16 rdata Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/micro_bus16_model/rtl/verilog/copyright.v
File deleted
/micro_bus16_model/rtl/verilog/tasks
0,0 → 1,116
// Tasks |
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask // next |
|
|
|
|
// idle cycle |
task u_idle; |
begin |
addr <= 24'h000000; |
wdata <= 16'h0000; |
rd <= 1'b0; |
cs <= 2'b00; |
wr <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
mask_rdata <= 16'h0000; |
next(1); |
end |
endtask |
|
|
|
|
// write cycle |
task u_write; |
input [23:0] a; |
input [15:0] d; |
|
begin |
|
$display("%t %m cycle %x %x",$realtime,a,d ); |
|
addr <= a; |
wdata <= d; |
rd <= 1'b0; |
cs <= 2'b01; |
wr <= 1'b1; |
ub <= 1'b1; |
lb <= 1'b1; |
next(4); |
rd <= 1'b0; |
cs <= 2'b00; |
wr <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
next(1); |
|
end |
endtask |
|
// read cycle |
task u_read; |
input [23:0] a; |
output [15:0] d; |
|
begin |
|
addr <= a; |
wdata <= 16'h0000; |
rd <= 1'b1; |
cs <= 2'b01; |
wr <= 1'b0; |
ub <= 1'b1; |
lb <= 1'b1; |
|
next(4); |
|
d <= rdata; |
$display("%t %m cycle %x %x",$realtime,a,rdata ); |
rd <= 1'b1; |
next(1); |
rd <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
cs <= 2'b00; |
next(1); |
end |
endtask |
|
// Compare cycle (read data from location and compare with expected data) |
task u_cmp; |
input [23:0] a; |
input [15:0] d_exp; |
|
begin |
addr <= a; |
wdata <= 16'h0000; |
rd <= 1'b1; |
ub <= 1'b1; |
lb <= 1'b1; |
cs <= 2'b01; |
wr <= 1'b0; |
exp_rdata <= d_exp; |
|
next(5); |
mask_rdata <= 16'hffff; |
|
|
next(1); |
$display("%t %m cycle %x %x",$realtime,a,d_exp ); |
mask_rdata <= 16'h0000; |
rd <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
cs <= 2'b00; |
next(1); |
end |
endtask |
|
/micro_bus16_model/rtl/verilog/copyright
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Microprocessor bus functional model (BFM) for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/micro_bus16_model/rtl/verilog/top.sim
1,54 → 1,6
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Microprocessor bus functional model (BFM) for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
|
|
|
module micro_bus16_model_def |
#(parameter OUT_DELAY = 15, |
parameter OUT_WIDTH = 10 |
#(parameter DELAY = 15, |
parameter WIDTH = 16 |
) |
|
|
55,6 → 7,7
( |
input wire clk, |
input wire reset, |
input wire [15:0] rdata, |
|
output reg [23:0] addr, |
output reg [15:0] wdata, |
62,16 → 15,41
output reg rd, |
output reg wr, |
output reg ub, |
output reg lb, |
output reg lb |
|
|
inout wire [15:0] rdata |
); |
|
|
reg [15:0] exp_rdata; |
reg [15:0] mask_rdata; |
|
|
|
io_probe_in |
#(.MESG ("micro rdata Error"), |
.WIDTH (WIDTH), |
.IN_DELAY (DELAY) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
|
|
|
|
|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
88,21 → 66,6
|
|
|
io_probe_def |
#(.MESG ("micro rdata Error"), |
.WIDTH (16), |
.RESET ({16{1'bz}}), |
.OUT_DELAY (OUT_DELAY), |
.OUT_WIDTH (OUT_WIDTH) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.drive_value (16'bzzzzzzzzzzzzzzzz ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
// Tasks |
/micro_bus16_model/rtl/verilog/top.syn
1,54 → 1,6
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Microprocessor bus functional model (BFM) for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
|
|
|
module micro_bus16_model_def |
#(parameter OUT_DELAY = 15, |
parameter OUT_WIDTH = 10 |
#(parameter DELAY = 15, |
parameter WIDTH = 10 |
) |
|
|
55,6 → 7,7
( |
input wire clk, |
input wire reset, |
input wire [15:0] rdata, |
|
output reg [23:0] addr, |
output reg [15:0] wdata, |
62,10 → 15,10
output reg rd, |
output reg wr, |
output reg ub, |
output reg lb, |
output reg lb |
|
|
inout wire [15:0] rdata |
|
); |
|
|
72,10 → 25,26
reg [15:0] exp_rdata; |
reg [15:0] mask_rdata; |
|
|
|
|
io_probe_in |
#(.MESG ("micro rdata Error"), |
.WIDTH (16) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
always@(posedge clk) |
if(reset) |
begin |
addr <= 24'h0000; |
addr <= 24'h000000; |
wdata <= 16'h0000; |
wr <= 1'b0; |
rd <= 1'b0; |
88,27 → 57,9
|
|
|
io_probe_def |
#(.MESG ("micro rdata Error"), |
.WIDTH (16), |
.RESET ({16{1'bz}}), |
.OUT_DELAY (OUT_DELAY), |
.OUT_WIDTH (OUT_WIDTH) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.drive_value (16'bzzzzzzzzzzzzzzzz ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
|
|
|
|
|
endmodule |
|
/micro_bus16_model/rtl/verilog/logic
0,0 → 1,14
always@(posedge clk) |
if(reset) |
begin |
addr <= 24'h0000; |
wdata <= 16'h0000; |
wr <= 1'b0; |
rd <= 1'b0; |
cs <= 2'b00; |
ub <= 1'b0; |
lb <= 1'b0; |
exp_rdata <= 16'h0000; |
mask_rdata <= 16'h0000; |
end |
|
/uart_model/rtl/xml/uart_model_def.xml
46,23 → 46,7
|
|
<spirit:componentGenerators> |
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
72,12 → 56,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>uart_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
91,57 → 71,121
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>uart_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="uart_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
|
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>CLKCNT</spirit:name><spirit:value>4'h5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>txd_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rxd_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
|
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
149,31 → 193,32
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:name>../verilog/top.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
<spirit:name>../verilog/sim/uart_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
216,30 → 261,34
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
<spirit:name>../verilog/syn/uart_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_xmit</spirit:name> |
273,101 → 322,10
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="uart_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
|
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>CLKCNT</spirit:name><spirit:value>4'h5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>txd_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rxd_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/uart_model/rtl/verilog/copyright.v
File deleted
/uart_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/vga_model/rtl/xml/vga_model_def.design.xml
0,0 → 1,190
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>vga_model</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>exp_device_rx_data</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>mask_device_rx_data</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>exp_device_rx_parity</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>drv_device_rx_parity</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
|
|
|
<socgen:node><spirit:name>mask_device_rx_parity</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
|
|
|
|
|
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>exp_device_rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_device_rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_device_rx_parity</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_device_rx_parity" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>mask_device_rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_device_rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>mask_device_rx_parity</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_device_rx_parity" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
|
|
|
<spirit:adHocConnection> |
<spirit:name>prb_device_rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="prb_device_rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>prb_device_rx_parity</spirit:name> |
<spirit:externalPortReference spirit:portRef="prb_device_rx_parity" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>device_rx_data_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2 data receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>device_rx_parity_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2 parity receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/vga_model/rtl/xml/vga_model_def.xml
56,12 → 56,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>vga_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
75,157 → 71,51
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>vga_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="vga_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
325,9 → 215,95
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/vga_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/vga_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
</spirit:component> |
/vga_model/rtl/verilog/copyright.v
File deleted
/vga_model/rtl/verilog/top.rtl
1,8 → 1,23
|
|
assign prb_device_rx_data = 8'h00; |
|
assign prb_device_rx_parity = 1'b0; |
|
always@(posedge clk) |
if(reset) |
mask_device_rx_parity <= 1'b0; |
else |
mask_device_rx_parity <= 1'b0; |
|
always@(posedge clk) |
if(reset) |
mask_device_rx_data <= 8'b0; |
else |
mask_device_rx_data <= 8'b0; |
|
|
|
reg [23:0] red_h_cnt; |
reg [23:0] green_h_cnt; |
reg [23:0] blue_h_cnt; |
84,7 → 99,7
|
|
/* |
io_probe_def |
io_probe_in |
#(.MESG ("vga data receive error"), |
.WIDTH (8) |
) |
91,7 → 106,6
rx_shift_buffer_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz), |
.expected_value( exp_rx_shift_buffer), |
.mask ( mask_rx_shift_buffer), |
.signal ( prb_rx_shift_buffer) |
98,12 → 112,11
); |
|
|
io_probe_def |
io_probe_in |
#(.MESG ("vga parity error")) |
rx_parity_err_prb |
( |
.clk ( clk ), |
.drive_value (1'bz), |
.expected_value( exp_rx_parity_err), |
.mask ( mask_rx_parity_err), |
.signal ( prb_rx_parity_err) |
/vga_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/io_probe/componentCfg.xml
27,5 → 27,38
|
|
|
<socgen:configurations> |
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>MESG</socgen:name><socgen:value>" "</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>RESET</socgen:name><socgen:value>{WIDTH{1'bz}}</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>IN_DELAY</socgen:name><socgen:value>5</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>OUT_DELAY</socgen:name><socgen:value>15</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>OUT_WIDTH</socgen:name><socgen:value>10</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
|
<socgen:configuration> |
<socgen:name>in</socgen:name> |
<socgen:version>in</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>MESG</socgen:name><socgen:value>" "</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>IN_DELAY</socgen:name><socgen:value>5</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
</socgen:configurations> |
|
|
|
|
|
|
</socgen:componentConfiguration> |
/io_probe/rtl/xml/io_probe_in.design.xml
File deleted
/io_probe/rtl/xml/io_probe_def.design.xml
File deleted
/io_probe/rtl/xml/io_probe_in.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
39,35 → 39,9
<spirit:name>io_probe</spirit:name> |
<spirit:version>in</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
76,12 → 50,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.in.sim</spirit:value> |
<spirit:value>io_probe_in</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
94,12 → 64,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.in.syn</spirit:value> |
<spirit:value>io_probe_in</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
145,85 → 111,29
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.in.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body.in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.in.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
307,6 → 217,76
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/io_probe_in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body.in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/io_probe_in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
</spirit:component> |
/io_probe/rtl/xml/io_probe_def.xml
48,24 → 48,6
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
74,12 → 56,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>io_probe_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
93,138 → 71,41
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>io_probe_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
315,9 → 196,78
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/io_probe_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/io_probe_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
</spirit:component> |
/io_probe/rtl/verilog/copyright.v
File deleted
/io_probe/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* io_probe for handling timing delays in dut */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|