URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

This comparison shows the changes necessary to convert path
```
/socgen/trunk/common/opencores.org/Testbench/doc
```
from Rev 134 to Rev 135
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 134 → Rev 135

/Geda/sch/uart_host_def.sch File deleted

/Geda/sch/micro_bus16_model_def.sch File deleted

/Geda/sch/uart_model_def.sch File deleted

/Geda/sch/vga_model_def.sch File deleted

/Geda/sch/io_probe_def.sch File deleted

/Geda/sch/or1200_dbg_model_def.sch File deleted

/Geda/sch/mt45w8mw12_def.sch File deleted

/Geda/sch/ps2_host_def.sch File deleted

/Geda/sch/micro_bus_model_def.sch File deleted

/Geda/sch/ps2_model_def.sch File deleted

/Geda/sch/clock_gen_def.sch File deleted

/Geda/sch/display_model_def.sch File deleted

/Geda/sch/jtag_model_def.sch File deleted

/Geda/sch/io_probe_in.sch File deleted

/Geda/png/ps2_model_def_sym.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/Geda/png/ps2_model_def_sym.png

Geda/png/ps2_model_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/clock_gen_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/clock_gen_def_sym.png =================================================================== --- Geda/png/clock_gen_def_sym.png (revision 134) +++ Geda/png/clock_gen_def_sym.png (nonexistent)

Geda/png/clock_gen_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/mt45w8mw12_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/mt45w8mw12_def_sch.png =================================================================== --- Geda/png/mt45w8mw12_def_sch.png (revision 134) +++ Geda/png/mt45w8mw12_def_sch.png (nonexistent)

Geda/png/mt45w8mw12_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/or1200_dbg_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/or1200_dbg_model_def_sch.png =================================================================== --- Geda/png/or1200_dbg_model_def_sch.png (revision 134) +++ Geda/png/or1200_dbg_model_def_sch.png (nonexistent)

Geda/png/or1200_dbg_model_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/ps2_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/ps2_model_def_sch.png =================================================================== --- Geda/png/ps2_model_def_sch.png (revision 134) +++ Geda/png/ps2_model_def_sch.png (nonexistent)

Geda/png/ps2_model_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/clock_gen_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/clock_gen_def_sch.png =================================================================== --- Geda/png/clock_gen_def_sch.png (revision 134) +++ Geda/png/clock_gen_def_sch.png (nonexistent)

Geda/png/clock_gen_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/uart_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/uart_model_def_sym.png =================================================================== --- Geda/png/uart_model_def_sym.png (revision 134) +++ Geda/png/uart_model_def_sym.png (nonexistent)

Geda/png/uart_model_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/io_probe_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/io_probe_def_sym.png =================================================================== --- Geda/png/io_probe_def_sym.png (revision 134) +++ Geda/png/io_probe_def_sym.png (nonexistent)

Geda/png/io_probe_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/uart_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/uart_model_def_sch.png =================================================================== --- Geda/png/uart_model_def_sch.png (revision 134) +++ Geda/png/uart_model_def_sch.png (nonexistent)

Geda/png/uart_model_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/ps2_host_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/ps2_host_def_sym.png =================================================================== --- Geda/png/ps2_host_def_sym.png (revision 134) +++ Geda/png/ps2_host_def_sym.png (nonexistent)

Geda/png/ps2_host_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/micro_bus_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/micro_bus_model_def_sym.png =================================================================== --- Geda/png/micro_bus_model_def_sym.png (revision 134) +++ Geda/png/micro_bus_model_def_sym.png (nonexistent)

Geda/png/micro_bus_model_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/io_probe_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/io_probe_def_sch.png =================================================================== --- Geda/png/io_probe_def_sch.png (revision 134) +++ Geda/png/io_probe_def_sch.png (nonexistent)

Geda/png/io_probe_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/jtag_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/jtag_model_def_sym.png =================================================================== --- Geda/png/jtag_model_def_sym.png (revision 134) +++ Geda/png/jtag_model_def_sym.png (nonexistent)

Geda/png/jtag_model_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/ps2_host_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/ps2_host_def_sch.png =================================================================== --- Geda/png/ps2_host_def_sch.png (revision 134) +++ Geda/png/ps2_host_def_sch.png (nonexistent)

Geda/png/ps2_host_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/io_probe_in_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/io_probe_in_sym.png =================================================================== --- Geda/png/io_probe_in_sym.png (revision 134) +++ Geda/png/io_probe_in_sym.png (nonexistent)

Geda/png/io_probe_in_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/micro_bus_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/micro_bus_model_def_sch.png =================================================================== --- Geda/png/micro_bus_model_def_sch.png (revision 134) +++ Geda/png/micro_bus_model_def_sch.png (nonexistent)

Geda/png/micro_bus_model_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/uart_host_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/uart_host_def_sym.png =================================================================== --- Geda/png/uart_host_def_sym.png (revision 134) +++ Geda/png/uart_host_def_sym.png (nonexistent)

Geda/png/uart_host_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/micro_bus16_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/micro_bus16_model_def_sym.png =================================================================== --- Geda/png/micro_bus16_model_def_sym.png (revision 134) +++ Geda/png/micro_bus16_model_def_sym.png (nonexistent)

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Geda/png/uart_host_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/micro_bus16_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/micro_bus16_model_def_sch.png =================================================================== --- Geda/png/micro_bus16_model_def_sch.png (revision 134) +++ Geda/png/micro_bus16_model_def_sch.png (nonexistent)

Geda/png/micro_bus16_model_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/mt45w8mw12_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/mt45w8mw12_def_sym.png =================================================================== --- Geda/png/mt45w8mw12_def_sym.png (revision 134) +++ Geda/png/mt45w8mw12_def_sym.png (nonexistent)

Geda/png/mt45w8mw12_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/or1200_dbg_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/or1200_dbg_model_def_sym.png =================================================================== --- Geda/png/or1200_dbg_model_def_sym.png (revision 134) +++ Geda/png/or1200_dbg_model_def_sym.png (nonexistent)

Geda/png/or1200_dbg_model_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/html/micro_bus16_model_def.html =================================================================== --- Geda/html/micro_bus16_model_def.html (revision 134) +++ Geda/html/micro_bus16_model_def.html (nonexistent) @@ -1,222 +0,0 @@ - - - - - start - - - - - - - - - - -

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addr[23:0 ]
output

clk
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cs[1:0 ]
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lb
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rd
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rdata[15:0 ]
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reset
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ub
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wr
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rdata_tpb
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4'h5

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4

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opencores.org
Testbench
io_probe
in
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" "

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1

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{WIDTH{1'bz}}

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5

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15

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10

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clk
input

drive_value[WIDTH-1:0 ]
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inout

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addr[ADDR_BITS-1:0 ]
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adv_n
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or1200_dbg_model_def
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tx_ack_err_tpb
opencores.org
Testbench
io_probe
in
rcv_byte_tpb
opencores.org
Testbench
io_probe
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rdata_tpb
opencores.org
Testbench
io_probe
in
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opencores.org
Testbench
io_probe
def
device_rx_parity_tpb
opencores.org
Testbench
io_probe
def
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mask[WIDTH-1:0 ]
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Description

clk
input

parity_enable
output

reset
input

rxd_data_avail
input

rxd_data_avail_stb
output

rxd_data_out[7:0 ]
input

rxd_force_parity
output

rxd_parity
output

rxd_parity_error
input

rxd_stop_error
input

txd_break
output

txd_buffer_empty
input

txd_data_in[7:0 ]
output

txd_force_parity
output

txd_load
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txd_parity
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rxd_data_out_prb
opencores.org
Testbench
io_probe
in
rxd_stop_error_prb
opencores.org
Testbench
io_probe
in
rxd_parity_error_prb
opencores.org
Testbench
io_probe
in
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- - Index: Geda/src/io_probe_in.v =================================================================== --- Geda/src/io_probe_in.v (revision 134) +++ Geda/src/io_probe_in.v (nonexistent) @@ -1,71 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* io_probe for handling timing delays in dut */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - io_probe_in - #( parameter - IN_DELAY=5, - MESG=" ", - WIDTH=1) - ( - input wire clk, - input wire [ WIDTH-1 : 0] expected_value, - input wire [ WIDTH-1 : 0] mask, - input wire [ WIDTH-1 : 0] signal); -reg [WIDTH-1:0] filtered_value; -reg [WIDTH:1] fail; -always @(posedge clk) filtered_value <= signal; -always @(posedge clk) fail <= mask & (signal^ expected_value); -initial - begin - cg.next(3); - while(1) - begin - if(fail !== {WIDTH{1'b0}}) - begin - $display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail ); - cg.fail(MESG); - end - cg.next(1); - end // while (1) - end // initial begin - endmodule Index: Geda/src/uart_host_def.v =================================================================== --- Geda/src/uart_host_def.v (revision 134) +++ Geda/src/uart_host_def.v (nonexistent) @@ -1,200 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* uart host model for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module uart_host_def ( -input wire clk, -input wire reset, -output reg parity_enable, -output reg txd_parity, -output reg txd_force_parity, -output reg [7:0] txd_data_in, -input wire txd_buffer_empty, -output reg txd_load, -output reg txd_break, -output reg rxd_parity, -output reg rxd_force_parity, -output reg rxd_data_avail_stb, -inout wire [7:0] rxd_data_out, -input wire rxd_data_avail, -inout wire rxd_stop_error, -inout wire rxd_parity_error -); -reg exp_rxd_stop_error; -reg exp_rxd_parity_error; -reg [7:0] exp_rxd_data_out; -reg mask_rxd_stop_error; -reg mask_rxd_parity_error; -reg [7:0] mask_rxd_data_out; -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask -always@(posedge clk) -if(reset) - begin - parity_enable <= 1'b0; - txd_data_in <= 8'h00; - txd_parity <= 1'b0; - txd_force_parity <= 1'b0; - txd_load <= 1'b0; - txd_break <= 1'b0; - rxd_parity <= 1'b0; - rxd_force_parity <= 1'b0; - rxd_data_avail_stb <= 1'b0; - exp_rxd_stop_error <= 1'b0; - exp_rxd_parity_error <= 1'b0; - exp_rxd_data_out <= 8'h00; - mask_rxd_stop_error <= 1'b0; - mask_rxd_parity_error <= 1'b0; - mask_rxd_data_out <= 8'h00; - end -task clear_rx_host; - begin - next(1); - end -endtask -task send_byte; - input [7:0] byte_out; - begin - while(!txd_buffer_empty) next(1); - $display("%t %m %2h",$realtime ,byte_out); - txd_data_in <= byte_out; - next(1); - txd_load <= 1'b1; - next(1); - txd_load <= 1'b0; - next(1); - end -endtask // send_byte -task rcv_byte; - input [7:0] byte_in; - begin - exp_rxd_data_out <= byte_in; - while(!rxd_data_avail) next(1); - $display("%t %m checking %h",$realtime,byte_in); - mask_rxd_stop_error <= 1'b1; - mask_rxd_parity_error <= 1'b1; - mask_rxd_data_out <= 8'hff; - next(1); - mask_rxd_stop_error <= 1'b0; - mask_rxd_parity_error <= 1'b0; - mask_rxd_data_out <= 8'h00; - rxd_data_avail_stb <= 1'b1; - next(1); - rxd_data_avail_stb <= 1'b0; - next(1); -end -endtask -io_probe_def -#(.MESG("uart_host receive error"), - .WIDTH(8)) -rxd_data_out_prb -( - .clk ( clk ), - .drive_value (8'bzzzzzzzz ), - .expected_value ( exp_rxd_data_out ), - .mask ( mask_rxd_data_out ), - .signal ( rxd_data_out ) -); -io_probe_def -#(.MESG("uart_host stop error")) -rxd_stop_error_prb -( - .clk ( clk ), - .drive_value (1'bz ), - .expected_value ( exp_rxd_stop_error ), - .mask ( mask_rxd_stop_error ), - .signal ( rxd_stop_error ) -); -io_probe_def -#(.MESG("uart_host parity error")) -rxd_parity_error_prb -( - .clk ( clk ), - .drive_value (1'bz ), - .expected_value ( exp_rxd_parity_error ), - .mask ( mask_rxd_parity_error ), - .signal ( rxd_parity_error ) -); -endmodule Index: Geda/src/micro_bus16_model_def.v =================================================================== --- Geda/src/micro_bus16_model_def.v (revision 134) +++ Geda/src/micro_bus16_model_def.v (nonexistent) @@ -1,221 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Microprocessor bus functional model (BFM) for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Microprocessor bus functional model (BFM) for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module micro_bus16_model_def -#(parameter OUT_DELAY = 15, - parameter OUT_WIDTH = 10 - ) - ( - input wire clk, - input wire reset, - output reg [23:0] addr, - output reg [15:0] wdata, - output reg [1:0] cs, - output reg rd, - output reg wr, - output reg ub, - output reg lb, - inout wire [15:0] rdata -); - reg [15:0] exp_rdata; - reg [15:0] mask_rdata; -always@(posedge clk) - if(reset) - begin - addr <= 24'h0000; - wdata <= 16'h0000; - wr <= 1'b0; - rd <= 1'b0; - cs <= 2'b00; - ub <= 1'b0; - lb <= 1'b0; - exp_rdata <= 16'h0000; - mask_rdata <= 16'h0000; - end -io_probe_def - #(.MESG ("micro rdata Error"), - .WIDTH (16), - .RESET ({16{1'bz}}), - .OUT_DELAY (OUT_DELAY), - .OUT_WIDTH (OUT_WIDTH) - ) -rdata_tpb - ( - .clk ( clk ), - .drive_value (16'bzzzzzzzzzzzzzzzz ), - .expected_value ( exp_rdata ), - .mask ( mask_rdata ), - .signal ( rdata ) - ); - // Tasks -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask // next - // idle cycle - task u_idle; - begin - addr <= 24'h000000; - wdata <= 16'h0000; - rd <= 1'b0; - cs <= 2'b00; - wr <= 1'b0; - ub <= 1'b0; - lb <= 1'b0; - mask_rdata <= 16'h0000; - next(1); - end - endtask - // write cycle - task u_write; - input [23:0] a; - input [15:0] d; - begin - $display("%t %m cycle %x %x",$realtime,a,d ); - addr <= a; - wdata <= d; - rd <= 1'b0; - cs <= 2'b01; - wr <= 1'b1; - ub <= 1'b1; - lb <= 1'b1; - next(4); - rd <= 1'b0; - cs <= 2'b00; - wr <= 1'b0; - ub <= 1'b0; - lb <= 1'b0; - next(1); - end - endtask - // read cycle - task u_read; - input [23:0] a; - output [15:0] d; - begin - addr <= a; - wdata <= 16'h0000; - rd <= 1'b1; - cs <= 2'b01; - wr <= 1'b0; - ub <= 1'b1; - lb <= 1'b1; - next(4); - d <= rdata; - $display("%t %m cycle %x %x",$realtime,a,rdata ); - rd <= 1'b1; - next(1); - rd <= 1'b0; - ub <= 1'b0; - lb <= 1'b0; - cs <= 2'b00; - next(1); - end - endtask - // Compare cycle (read data from location and compare with expected data) - task u_cmp; - input [23:0] a; - input [15:0] d_exp; - begin - addr <= a; - wdata <= 16'h0000; - rd <= 1'b1; - ub <= 1'b1; - lb <= 1'b1; - cs <= 2'b01; - wr <= 1'b0; - exp_rdata <= d_exp; - next(5); - mask_rdata <= 16'hffff; - next(1); - $display("%t %m cycle %x %x",$realtime,a,d_exp ); - mask_rdata <= 16'h0000; - rd <= 1'b0; - ub <= 1'b0; - lb <= 1'b0; - cs <= 2'b00; - next(1); - end - endtask -endmodule Index: Geda/src/uart_model_def.v =================================================================== --- Geda/src/uart_model_def.v (revision 134) +++ Geda/src/uart_model_def.v (nonexistent) @@ -1,708 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - uart_model_def - #( parameter - CLKCNT=4'h5, - SIZE=4) - ( - input wire clk, - input wire reset, - input wire txd_in, - output wire rxd_out); -reg exp_rx_parity_err; -reg mask_rx_parity_err; -reg [ 7 : 0] exp_rx_shift_buffer; -reg [ 7 : 0] mask_rx_shift_buffer; -wire drv_rx_parity_err; -wire prb_rx_parity_err; -wire [ 7 : 0] drv_rx_shift_buffer; -wire [ 7 : 0] prb_rx_shift_buffer; -io_probe_def -#( .MESG ("uart parity Error"), - .WIDTH (1)) -rx_parity_err_prb - ( - .clk ( clk ), - .drive_value ( drv_rx_parity_err ), - .expected_value ( exp_rx_parity_err ), - .mask ( mask_rx_parity_err ), - .signal ( prb_rx_parity_err )); -io_probe_def -#( .MESG ("uart data receive Error"), - .WIDTH (8)) -rx_shift_buffer_prb - ( - .clk ( clk ), - .drive_value ( drv_rx_shift_buffer[7:0] ), - .expected_value ( exp_rx_shift_buffer[7:0] ), - .mask ( mask_rx_shift_buffer[7:0] ), - .signal ( prb_rx_shift_buffer[7:0] )); -reg rx_parity_enable; // 0 = no parity bit sent; 1= parity bit sent -reg rx_parity ; -reg rx_force_parity ; -reg rx_stop_value; // value out for stop bit -reg rx_start_detect; -reg [7:0] rx_shift_buffer; -reg rx_parity_calc; -reg rx_parity_samp; -reg rx_parity_error; -reg rx_frame_err; -reg exp_rx_frame_err; -reg mask_rx_frame_err; -reg rx_frame_rdy; -reg rx_baud_enable; -wire rx_stop_cnt; -wire rx_last_cnt; -wire [7:0] next_rx_shift_buffer; -wire next_rx_parity_calc; -wire next_rx_parity_samp; -wire next_rx_frame_err; -reg rxd_pad_sig; -reg [1:0] rx_rdy_del; -reg [SIZE-1:0] rx_baudgen; -reg edge_enable; -reg [SIZE-1:0] divide_cnt; - wire xmit_enable; -reg txd_parity_enable; -reg txd_force_parity; -reg txd_parity; -reg txd_load; -reg txd_break; -reg [7:0] txd_data_in; -wire txd_buffer_empty; -// -// watch for start bit -// -always@(posedge clk) - if(reset) - begin - rx_parity_enable <= 1'b0; - rx_parity <= 1'b0; - rx_force_parity <= 1'b0; - rx_stop_value <= 1'b1; - exp_rx_frame_err <= 1'b0; - exp_rx_parity_err <= 1'b0; - exp_rx_shift_buffer <= 8'h00; - mask_rx_frame_err <= 1'b0; - mask_rx_parity_err <= 1'b0; - mask_rx_shift_buffer <= 8'h00; - txd_parity_enable <= 1'b0; - txd_force_parity <= 1'b0; - txd_parity <= 1'b0; - txd_load <= 1'b0; - txd_break <= 1'b0; - txd_data_in <= 8'h00; - end -wire prb_rx_frame_err; -assign prb_rx_shift_buffer = rx_shift_buffer; -assign prb_rx_frame_err = rx_frame_err; -assign prb_rx_parity_err = rx_parity_error; -assign drv_rx_shift_buffer = 8'bzzzzzzzz; -assign drv_rx_parity_err = 1'bz; -/* -io_probe_def -#(.MESG ("uart data receive error"), - .WIDTH (8) - ) -rx_shift_buffer_prb -( - .clk ( clk ), - .drive_value ( drv_rx_shift_buffer ), - .expected_value( exp_rx_shift_buffer ), - .mask ( mask_rx_shift_buffer), - .signal ( prb_rx_shift_buffer ) -); -io_probe_def -#(.MESG ("uart parity error")) -rx_parity_err_prb -( - .clk ( clk ), - .drive_value ( drv_rx_parity_err ), - .expected_value( exp_rx_parity_err ), - .mask ( mask_rx_parity_err), - .signal ( prb_rx_parity_err ) -); -*/ -always@(posedge clk) -if(reset) rx_baudgen <= CLKCNT; -else -if(rx_baudgen == 4'h0) rx_baudgen <= CLKCNT; -else rx_baudgen <= rx_baudgen - 1'h1; -always@(posedge clk) -if(reset) edge_enable <= 1'b0; -else edge_enable <= (rx_baudgen == {SIZE{1'b0}}); -always@(posedge clk) -if(reset) rxd_pad_sig <= 1'b1; -else rxd_pad_sig <= txd_in; -always@(posedge clk) -if(reset) rx_start_detect <= 1'b0; -else -if(rx_start_detect) - begin - if(rx_stop_cnt && edge_enable ) rx_start_detect <= !rxd_pad_sig; - else - if(rx_last_cnt) rx_start_detect <= 1'b0; - else rx_start_detect <= 1'b1; - end -else -if(!rxd_pad_sig ) rx_start_detect <= 1'b1; -else rx_start_detect <= rx_start_detect; -always@(posedge clk) - if(reset) - begin - rx_frame_rdy <= 1'b0; - rx_rdy_del <= 2'b00; - end - else - begin - rx_frame_rdy <= rx_rdy_del[1] ; - rx_rdy_del <= {rx_rdy_del[0],rx_last_cnt}; - end -uart_model_serial_rcvr -#(.WIDTH(8), .SIZE(4) ) -serial_rcvr - ( - .clk ( clk ), - .reset ( reset ), - .edge_enable ( rx_baud_enable ), - .parity_enable ( rx_parity_enable ), - .parity_type ( {rx_force_parity, rx_parity } ), - .stop_cnt ( rx_stop_cnt ), - .last_cnt ( rx_last_cnt ), - .stop_value ( rx_stop_value ), - .ser_in ( txd_in ), - .shift_buffer ( next_rx_shift_buffer ), - .parity_calc ( next_rx_parity_calc ), - .parity_samp ( next_rx_parity_samp ), - .frame_err ( next_rx_frame_err ) -); -always@(posedge clk) - if( reset || (!rx_start_detect)) rx_baud_enable <= 1'b0; - else - if(!edge_enable) rx_baud_enable <= 1'b0; - else rx_baud_enable <= ( divide_cnt == 4'b1000 ); -always@(posedge clk) - if( reset || (!rx_start_detect)) divide_cnt <= 4'b1111; - else - if(!edge_enable) divide_cnt <= divide_cnt; - else - if(!(|divide_cnt)) divide_cnt <= 4'b1111; - else divide_cnt <= divide_cnt - 'b1; -always@(posedge clk) - if(reset) - begin - rx_shift_buffer <= 8'h00; - rx_parity_calc <= 1'b0; - rx_parity_samp <= 1'b0; - rx_parity_error <= 1'b0; - rx_frame_err <= 1'b0; - end - else - if(rx_last_cnt ) - begin - rx_shift_buffer <= next_rx_shift_buffer; - rx_parity_calc <= next_rx_parity_calc; - rx_parity_samp <= next_rx_parity_samp; - rx_parity_error <= (next_rx_parity_samp ^ next_rx_parity_calc) && rx_parity_enable; - rx_frame_err <= next_rx_frame_err; - end - else - begin - rx_shift_buffer <= rx_shift_buffer; - rx_parity_calc <= rx_parity_calc; - rx_parity_samp <= rx_parity_samp; - rx_parity_error <= rx_parity_error; - rx_frame_err <= rx_frame_err; - end -///////////////// Xmit -uart_model_divider -#(.SIZE(4)) -x_divider ( - .clk ( clk ), - .reset ( reset ), - .divider_in ( 4'b1111 ), - .enable ( edge_enable ), - .divider_out ( xmit_enable ) - ); -uart_model_serial_xmit -serial_xmit ( - .clk ( clk ), - .reset ( reset ), - .edge_enable ( xmit_enable ), - .parity_enable ( txd_parity_enable ), - .two_stop_enable ( 1'b0 ), - .parity_type ( {txd_force_parity, txd_parity } ), - .load ( txd_load ), - .start_value ( 1'b0 ), - .stop_value (!txd_break ), - .data ( txd_data_in ), - .buffer_empty ( txd_buffer_empty ), - .ser_out ( rxd_out ) - ); -task next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask -task wait_tx; -begin - while(!txd_buffer_empty) next(1); -end -endtask // wait_tx -task send_byte; - input [7:0] byte_out; -begin - while(!txd_buffer_empty) next(1); - $display("%t %m %2h",$realtime ,byte_out ); - txd_data_in = byte_out; - next(1); - txd_load = 1'b1; - next(1); - txd_load = 1'b0; - next(1); -end -endtask // send_byte -task rcv_byte; - input [7:0] byte_in; - begin - exp_rx_shift_buffer <= byte_in; - while(!rx_frame_rdy) next(1); - $display("%t %m check %h %h ",$realtime,rx_shift_buffer,byte_in); - mask_rx_frame_err <= 1'b1; - mask_rx_parity_err <= 1'b1; - mask_rx_shift_buffer <= 8'hff; - next(1); - mask_rx_frame_err <= 1'b0; - mask_rx_parity_err <= 1'b0; - mask_rx_shift_buffer <= 8'h00; -end -endtask - endmodule -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / LIB \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Generic model for a serial asynchronous receiver */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module -uart_model_serial_rcvr -#(parameter WIDTH=8, // Number of data bits - parameter SIZE=4 // binary size of shift_cnt, must be able to hold WIDTH + 4 states - )( -input wire clk, -input wire reset, -input wire edge_enable, // one pulse per bit time for 16 x data rate timing -input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent -input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1 -input wire stop_value, // value out for stop bit -input wire ser_in, // from pad_ring -output reg [WIDTH-1:0] shift_buffer, -output reg stop_cnt, -output reg last_cnt, -output reg parity_calc, -output reg parity_samp, -output reg frame_err -); -reg [SIZE-1:0] shift_cnt; -// -// shift_cnt controls the serial bit out -// -// 0 Start bit -// 1-> WIDTH Data bit lsb first -// WIDTH+1 Parity bit if enabled -// 2^SIZE-2 Second stop bit if enabled -// 2^SIZE-1 Last stop bit and idle -always@(posedge clk) - if( reset ) - begin - shift_cnt <= {SIZE{1'b1}}; - last_cnt <= 1'b0; - end - else - if(!edge_enable) - begin - shift_cnt <= shift_cnt; - last_cnt <= 1'b0; - end - else - if(( shift_cnt == {SIZE{1'b1}})) - begin - shift_cnt <= {SIZE{1'b0}}; - last_cnt <= 1'b0; - end - else - if ( shift_cnt == WIDTH) - case( parity_enable ) - (1'b0): - begin - shift_cnt <= {SIZE{1'b1}}; - last_cnt <= 1'b1; - end - (1'b1): - begin - shift_cnt <= shift_cnt + 1'b1; - last_cnt <= 1'b0; - end - endcase // case (parity_enable) - else - if ( shift_cnt == (WIDTH+1)) - begin - shift_cnt <= {SIZE{1'b1}}; - last_cnt <= 1'b1; - end - else - begin - shift_cnt <= shift_cnt + 1'b1; - last_cnt <= 1'b0; - end -// -// -// load shift_buffer during start_bit -// shift down every bit -// -// -always@(posedge clk) - if(reset) shift_buffer <= {WIDTH{1'b0}}; - else - if(!edge_enable) shift_buffer <= shift_buffer; - else - if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= {WIDTH{1'b0}}; - else - if(shift_cnt <= WIDTH-1 ) shift_buffer <= {ser_in,shift_buffer[WIDTH-1:1]}; - else shift_buffer <= shift_buffer; -// -// -// calculate parity on the fly -// seed reg with 0 for odd and 1 for even -// force reg to 0 or 1 if needed -// -always@(posedge clk) - if(reset) parity_calc <= 1'b0; - else - if(!edge_enable) parity_calc <= parity_calc; - else - if(parity_type[1] || (shift_cnt == {SIZE{1'b1}})) parity_calc <= parity_type[0]; - else - if(shift_cnt <= WIDTH-1 ) parity_calc <= parity_calc ^ ser_in; - else parity_calc <= parity_calc; -// -// sample parity bit and hold it until next start bit -// -always@(posedge clk) - if(reset) parity_samp <= 1'b0; - else - if(!edge_enable) parity_samp <= parity_samp; - else - if(shift_cnt == {SIZE{1'b1}}) parity_samp <= 1'b0; - else - if(shift_cnt == WIDTH ) parity_samp <= ser_in; - else parity_samp <= parity_samp; -// -// check for stop bit error -// -always@(posedge clk) - if(reset) frame_err <= 1'b0; - else - if(!edge_enable) frame_err <= frame_err; - else - if(shift_cnt == {SIZE{1'b1}}) frame_err <= 1'b0; - else - if(shift_cnt == WIDTH+1 ) frame_err <= ser_in ^ stop_value; - else frame_err <= frame_err; -always@(*) - if( shift_cnt == {SIZE{1'b1}}) stop_cnt = 1'b1; - else stop_cnt = 1'b0; -endmodule -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / LIB \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Generic model for a serial asynchronous transmitter */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module -uart_model_serial_xmit -#(parameter WIDTH=8, // Number of data bits - parameter SIZE=4 // binary size of shift_cnt, must be able to hold WIDTH + 4 states - ) -( -input wire clk, -input wire reset, -input wire edge_enable, // one pulse per bit time for data rate timing -input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent -input wire two_stop_enable, // 0 = 1 stop bit, 1 = 2 stop bits -input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1 -input wire load, // start transmiting data -input wire start_value, // value out at start bit time -input wire stop_value, // value out for stop bit also used for break -input wire [WIDTH-1:0] data, // data byte -output reg buffer_empty, // ready for next byte -output reg ser_out // to pad_ring - ); -reg [SIZE-1:0] shift_cnt; -reg [WIDTH-1:0] shift_buffer; -reg parity_calc; -reg delayed_edge_enable; -// -// shift_cnt controls the serial bit out -// -// 0 Start bit -// 1-> WIDTH Data bit lsb first -// WIDTH+1 Parity bit if enabled -// 2^SIZE-2 Second stop bit if enabled -// 2^SIZE-1 Last stop bit and idle -always@(posedge clk) - if(reset || buffer_empty) shift_cnt <= {SIZE{1'b1}}; - else - if(!edge_enable) shift_cnt <= shift_cnt; - else - if(( shift_cnt == {SIZE{1'b1}} ) && ! buffer_empty ) shift_cnt <= {SIZE{1'b0}}; - else - if ( shift_cnt == WIDTH) - case({two_stop_enable,parity_enable}) - (2'b00): shift_cnt <= {SIZE{1'b1}}; - (2'b01): shift_cnt <= shift_cnt + 1'b1; - (2'b10): shift_cnt <= {SIZE{1'b1}} - 1'b1; - (2'b11): shift_cnt <= shift_cnt + 1'b1; - endcase // case ({two_stop_enable,parity_enable}) - else - if ( shift_cnt == (WIDTH+1)) - case( two_stop_enable) - (1'b0): shift_cnt <= {SIZE{1'b1}}; - (1'b1): shift_cnt <= {SIZE{1'b1}} - 1'b1; - endcase - else shift_cnt <= shift_cnt + 1'b1; -// -// -// Clear buffer_empty upon load pulse -// set it back at the start of the final stop pulse -// if load happens BEFORE the next edge_enable then data transfer will have no pauses -// logic ensures that having load happen on a edge_enable will work -// -always@(posedge clk) - if(reset) delayed_edge_enable <= 1'b0; - else delayed_edge_enable <= edge_enable && ! load; -always@(posedge clk) -if(reset) buffer_empty <= 1'b1; -else -if(load) buffer_empty <= 1'b0; -else -if((shift_cnt == {SIZE{1'b1}}) && delayed_edge_enable) - buffer_empty <= 1'b1; -else buffer_empty <= buffer_empty; -// -// -// load shift_buffer during start_bit -// shift down every bit -// -// -always@(posedge clk) - if(reset) shift_buffer <= {WIDTH{1'b0}}; - else - if(!edge_enable) shift_buffer <= shift_buffer; - else - if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= data; - else shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]}; -// -// -// calculate parity on the fly -// seed reg with 0 for odd and 1 for even -// force reg to 0 or 1 if needed -// -always@(posedge clk) - if(reset) parity_calc <= 1'b0; - else - if(!edge_enable) parity_calc <= parity_calc; - else - if(parity_type[1] || (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type[0]; - else parity_calc <= parity_calc ^ shift_buffer[0]; -// send start_bit,data,parity and stop based on shift_cnt - always@(posedge clk) - if(reset) ser_out <= stop_value; - else - if( shift_cnt == {SIZE{1'b0}} ) ser_out <= start_value; - else - if( shift_cnt == {SIZE{1'b1}} ) ser_out <= stop_value; - else - if( shift_cnt == ({SIZE{1'b1}}+1'b1) ) ser_out <= stop_value; - else - if( shift_cnt == (WIDTH+1) ) ser_out <= parity_calc; - else ser_out <= shift_buffer[0]; -endmodule -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / LIB \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Generic model for a rate divider */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module -uart_model_divider -#(parameter SIZE=4, - parameter SAMPLE=0, - parameter RESET=1 - ) -( -input wire clk, -input wire reset, -input wire enable, -input wire [SIZE-1:0] divider_in, -output reg divider_out - ); -reg [SIZE-1:0] divide_cnt; -always@(posedge clk) - if(reset) divider_out <= RESET; - else - if(!enable) divider_out <= 1'b0; - else divider_out <= ( divide_cnt == SAMPLE ); -always@(posedge clk) - if(reset) divide_cnt <= divider_in; - else - if(!enable) divide_cnt <= divide_cnt; - else - if(!(|divide_cnt)) divide_cnt <= divider_in; - else divide_cnt <= divide_cnt - 'b1; -endmodule Index: Geda/src/vga_model_def.v =================================================================== --- Geda/src/vga_model_def.v (revision 134) +++ Geda/src/vga_model_def.v (nonexistent) @@ -1,142 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - vga_model_def - ( - input wire clk, - input wire hsync_n, - input wire reset, - input wire vsync_n, - input wire [ 1 : 0] blue, - input wire [ 2 : 0] green, - input wire [ 2 : 0] red); -reg exp_device_rx_parity; -reg mask_device_rx_parity; -reg [ 7 : 0] exp_device_rx_data; -reg [ 7 : 0] mask_device_rx_data; -wire drv_device_rx_parity; -wire prb_device_rx_parity; -wire [ 7 : 0] drv_device_rx_data; -wire [ 7 : 0] prb_device_rx_data; -assign prb_device_rx_data = 8'h00; -assign prb_device_rx_parity = 1'b0; -always@(posedge clk) - if(reset) - mask_device_rx_parity <= 1'b0; - else - mask_device_rx_parity <= 1'b0; -always@(posedge clk) - if(reset) - mask_device_rx_data <= 8'b0; - else - mask_device_rx_data <= 8'b0; -reg [23:0] red_h_cnt; -reg [23:0] green_h_cnt; -reg [23:0] blue_h_cnt; -reg [23:0] red_h_lat; -reg [23:0] green_h_lat; -reg [23:0] blue_h_lat; -reg [47:0] v_cnt; -reg [47:0] v_lat; -reg hsync; -reg vsync; -always@(posedge clk) -if(reset) hsync <= 1'b0; -else hsync <= !hsync_n; -always@(posedge clk) -if(reset) vsync <= 1'b0; -else vsync <= !vsync_n; -always@(posedge clk) -if(reset || (hsync)) red_h_cnt <= 24'h0; -else red_h_cnt <= red_h_cnt + red; -always@(posedge clk) -if (reset) red_h_lat <= 24'h0; -else if(!hsync_n &&(!hsync)) red_h_lat <= red_h_cnt; -else red_h_lat <= red_h_lat; -always@(posedge clk) -if(reset || (hsync)) green_h_cnt <= 24'h0; -else green_h_cnt <= green_h_cnt + green; -always@(posedge clk) -if (reset) green_h_lat <= 24'h0; -else if(!hsync_n &&(!hsync)) green_h_lat <= green_h_cnt; -else green_h_lat <= green_h_lat; -always@(posedge clk) -if(reset || (hsync)) blue_h_cnt <= 24'h0; -else blue_h_cnt <= blue_h_cnt + blue; -always@(posedge clk) -if (reset) blue_h_lat <= 24'h0; -else if(!hsync_n &&(!hsync)) blue_h_lat <= blue_h_lat; -else blue_h_lat <= blue_h_cnt; -always@(posedge clk) -if (reset) v_cnt <= 48'h0; -else if(!hsync_n &&(!hsync)) v_cnt <= red_h_cnt + green_h_cnt + blue_h_cnt + v_cnt; -else v_cnt <= v_cnt; -always@(posedge clk) -if (reset) v_lat <= 48'h0; -else if(!vsync_n &&(vsync)) v_lat <= v_cnt; -else v_lat <= v_lat; -/* -io_probe_def -#(.MESG ("vga data receive error"), - .WIDTH (8) - ) -rx_shift_buffer_prb -( - .clk ( clk ), - .drive_value (8'bzzzzzzzz), - .expected_value( exp_rx_shift_buffer), - .mask ( mask_rx_shift_buffer), - .signal ( prb_rx_shift_buffer) -); -io_probe_def -#(.MESG ("vga parity error")) -rx_parity_err_prb -( - .clk ( clk ), - .drive_value (1'bz), - .expected_value( exp_rx_parity_err), - .mask ( mask_rx_parity_err), - .signal ( prb_rx_parity_err) -); -*/ - endmodule Index: Geda/src/io_probe_def.v =================================================================== --- Geda/src/io_probe_def.v (revision 134) +++ Geda/src/io_probe_def.v (nonexistent) @@ -1,76 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* io_probe for handling timing delays in dut */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - io_probe_def - #( parameter - IN_DELAY=5, - MESG=" ", - OUT_DELAY=15, - OUT_WIDTH=10, - RESET={WIDTH{1'bz}}, - WIDTH=1) - ( - inout wire [ WIDTH-1 : 0] signal, - input wire clk, - input wire [ WIDTH-1 : 0] drive_value, - input wire [ WIDTH-1 : 0] expected_value, - input wire [ WIDTH-1 : 0] mask); -reg [WIDTH-1:0] filtered_value; -reg [WIDTH:1] fail; -assign signal = drive_value; -always @(posedge clk) filtered_value <= signal; -always @(posedge clk) fail <= mask & (signal^ expected_value); -initial - begin - cg.next(3); - while(1) - begin - if(fail !== {WIDTH{1'b0}}) - begin - $display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail ); - cg.fail(MESG); - end - cg.next(1); - end // while (1) - end // initial begin - endmodule Index: Geda/src/mt45w8mw12_def.v =================================================================== --- Geda/src/mt45w8mw12_def.v (revision 134) +++ Geda/src/mt45w8mw12_def.v (nonexistent) @@ -1,75 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* psram behavioral model for sims */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module mt45w8mw12_def -#( - parameter ADDR_BITS = 23, - parameter DQ_BITS = 16, - parameter MEM_BITS = 16 - ) -( - input wire clk, - input wire adv_n, - input wire cre, - output wire o_wait, - input wire ce_n, - input wire oe_n, - input wire we_n, - input wire lb_n, - input wire ub_n, - input wire [ADDR_BITS-1 : 0] addr, - inout wire [DQ_BITS-1 : 0] dq -); -reg [7:0] memoryl [1< */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - or1200_dbg_model_def - ( - reg dbg_ewt_i, - reg dbg_stall_i, - reg dbg_stb_i, - reg dbg_we_i, - reg [ 31 : 0] dbg_adr_i, - reg [ 31 : 0] dbg_dat_i, - wire dbg_ack_o, - wire dbg_bp_o, - wire [ 1 : 0] dbg_is_o, - wire [ 10 : 0] dbg_wp_o, - wire [ 3 : 0] dbg_lss_o, - wire [ 31 : 0] dbg_dat_o, - input wire clk, - input wire reset); - reg [31:0] exp_rdata; - reg [31:0] mask_rdata; -always@(posedge clk) - if(reset) - begin - dbg_adr_i <= 32'h00000000; - dbg_dat_i <= 32'h00000000; - dbg_we_i <= 1'b0; - dbg_stb_i <= 1'b0; - dbg_stall_i <= 1'b1; - dbg_ewt_i <= 1'b0; - exp_rdata <= 32'h00000000; - mask_rdata <= 32'h00000000; - end // if (reset) -io_probe_in - #(.MESG ("or1200 rdata Error"), - .WIDTH (32) - ) -rdata_tpb - ( - .clk ( clk ), - .expected_value ( exp_rdata ), - .mask ( mask_rdata ), - .signal ( dbg_dat_o ) - ); - // Tasks -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask // next - // write cycle - task u_write; - input [31:0] a; - input [31:0] d; - begin - $display("%t %m cycle %x %x",$realtime,a,d ); - dbg_adr_i <= a; - dbg_dat_i <= d; - dbg_we_i <= 1'b1; - dbg_stb_i <= 1'b1; - next(1); - dbg_adr_i <= 32'h00000000; - dbg_dat_i <= 32'h00000000; - dbg_we_i <= 1'b0; - dbg_stb_i <= 1'b0; - end - endtask -// read cycle - task u_read; - input [31:0] a; - output [31:0] d; - begin - dbg_adr_i <= a; - dbg_we_i <= 1'b0; - dbg_stb_i <= 1'b1; - next(4); - d <= dbg_dat_o; - $display("%t %m cycle %x %x",$realtime,a,dbg_dat_o ); - next(1); - dbg_adr_i <= 32'h00000000; - dbg_we_i <= 1'b0; - dbg_stb_i <= 1'b0; - next(1); - end - endtask -// compare cycle - task u_cmp; - input [31:0] a; - input [31:0] d_exp; - begin - dbg_adr_i <= a; - dbg_we_i <= 1'b0; - dbg_stb_i <= 1'b1; - exp_rdata <= d_exp; - next(4); - mask_rdata <= 32'hffffffff; - next(1); - $display("%t %m cycle %x %x",$realtime,a,d_exp ); - mask_rdata <= 32'h00000000; - next(1); - dbg_adr_i <= 32'h00000000; - dbg_we_i <= 1'b0; - dbg_stb_i <= 1'b0; - next(1); - end - endtask - endmodule Index: Geda/src/ps2_host_def.v =================================================================== --- Geda/src/ps2_host_def.v (revision 134) +++ Geda/src/ps2_host_def.v (nonexistent) @@ -1,178 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* ps2 host model for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ -module ps2_host_def -( -input wire clk, -input wire reset, -input wire busy, -inout wire [7:0] rx_data, -input wire rx_read, -input wire rx_full, -input wire rx_parity_error, -input wire rx_parity_rcv, -input wire rx_parity_cal, -input wire rx_frame_error, -inout wire tx_ack_error, -output reg rx_clr, -output reg [7:0] tx_data, -output reg tx_write -); -reg exp_tx_ack_err; -reg mask_tx_ack_err; -reg [7:0] exp_rcv_byte; -reg [7:0] mask_rcv_byte; -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask -always@(posedge clk) - if(reset) - begin - tx_data <= 8'h00; - tx_write <= 1'b0; - rx_clr <= 1'b0; - exp_tx_ack_err <= 1'b0; - mask_tx_ack_err <= 1'b0; - exp_rcv_byte <= 8'h00; - mask_rcv_byte <= 8'h00; - end -task clear_rx_host; - begin - rx_clr <= 1'b1; - next(1); - rx_clr <= 1'b0; - end -endtask -task send_byte; - input [7:0] byte_out; - begin - $display("%t %m %2h",$realtime ,byte_out ); - tx_data <= byte_out; - next(1); - tx_write <= 1'b1; - next(1); - tx_write <= 1'b0; - next(1); - while(busy) next(1); - mask_tx_ack_err <= 1'b1; - next(1); - mask_tx_ack_err <= 1'b0; - end -endtask // send_byte -io_probe_def -#( .MESG("ps2_host tx_ack error") - ) -tx_ack_err_tpb -( - .clk ( clk ), - .drive_value ( 1'bz ), - .expected_value ( exp_tx_ack_err ), - .mask ( mask_tx_ack_err ), - .signal ( tx_ack_error ) -); -task rcv_byte; - input [7:0] byte_in; - begin - exp_rcv_byte <= byte_in; - while(!rx_read) next(1); - $display("%t checking %h",$realtime,byte_in); - mask_rcv_byte <= 8'hff; - next(1); - mask_rcv_byte <= 8'h00; -end -endtask -io_probe_def -#( .MESG("ps2_host receive error"), - .WIDTH (8) - ) -rcv_byte_tpb -( - .clk ( clk ), - .drive_value ( {8{1'bz}} ), - .expected_value ( exp_rcv_byte ), - .mask ( mask_rcv_byte ), - .signal ( rx_data ) -); -endmodule Index: Geda/src/micro_bus_model_def.v =================================================================== --- Geda/src/micro_bus_model_def.v (revision 134) +++ Geda/src/micro_bus_model_def.v (nonexistent) @@ -1,135 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Microprocessor bus functional model (BFM) for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - micro_bus_model_def - #( parameter - OUT_DELAY=15, - OUT_WIDTH=10, - addr_width=16) - ( - inout wire [ 7 : 0] rdata, - input wire clk, - input wire reset, - output reg cs, - output reg rd, - output reg wr, - output reg [ 7 : 0] wdata, - output reg [ addr_width-1 : 0] addr); -reg [ 7 : 0] exp_rdata; -reg [ 7 : 0] mask_rdata; -io_probe_in -#( .MESG ("micro rdata Error"), - .WIDTH (8)) -rdata_tpb - ( - .clk ( clk ), - .expected_value ( exp_rdata[7:0] ), - .mask ( mask_rdata[7:0] ), - .signal ( rdata[7:0] )); - always@(posedge clk) - if(reset) - begin - addr <= 16'h0000; - wdata <= 8'h00; - wr <= 1'b0; - rd <= 1'b0; - cs <= 1'b1; - exp_rdata <= 8'h00; - mask_rdata <= 8'h00; - end - // Tasks -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask // next - // write cycle - task u_write; - input [addr_width-1:0] a; - input [7:0] d; - begin - $display("%t %m cycle %x %x",$realtime,a,d ); - addr <= a; - wdata <= d; - rd <= 1'b0; - wr <= 1'b1; - next(1); - wr <= 1'b0; - next(1); - end - endtask - // read cycle - task u_read; - input [addr_width-1:0] a; - output [7:0] d; - begin - addr <= a; - wdata <= 8'h00; - rd <= 1'b1; - wr <= 1'b0; - next(2); - d <= rdata; - $display("%t %m cycle %x %x",$realtime,a,rdata ); - rd <= 1'b1; - next(1); - rd <= 1'b0; - end - endtask - // Compare cycle (read data from location and compare with expected data) - task u_cmp; - input [addr_width-1:0] a; - input [7:0] d_exp; - begin - addr <= a; - wdata <= 8'h00; - rd <= 1'b1; - wr <= 1'b0; - exp_rdata <= d_exp; - next(1); - mask_rdata <= 8'hff; - next(1); - $display("%t %m cycle %x %x",$realtime,a,d_exp ); - mask_rdata <= 8'h00; - rd <= 1'b0; - end - endtask - endmodule Index: Geda/src/ps2_model_def.v =================================================================== --- Geda/src/ps2_model_def.v (revision 134) +++ Geda/src/ps2_model_def.v (nonexistent) @@ -1,315 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - ps2_model_def - #( parameter - CLKCNT=10'h1f0, - SIZE=10) - ( - inout wire ps2_clk, - inout wire ps2_data, - input wire clk, - input wire reset); -reg exp_device_rx_parity; -reg mask_device_rx_parity; -reg [ 7 : 0] exp_device_rx_data; -reg [ 7 : 0] mask_device_rx_data; -wire drv_device_rx_parity; -wire prb_device_rx_parity; -wire [ 7 : 0] drv_device_rx_data; -wire [ 7 : 0] prb_device_rx_data; -io_probe_def -#( .MESG ("ps2 data receive Error"), - .WIDTH (8)) -device_rx_data_tpb - ( - .clk ( clk ), - .drive_value ( drv_device_rx_data[7:0] ), - .expected_value ( exp_device_rx_data[7:0] ), - .mask ( mask_device_rx_data[7:0] ), - .signal ( prb_device_rx_data[7:0] )); -io_probe_def -#( .MESG ("ps2 parity receive Error"), - .WIDTH (1)) -device_rx_parity_tpb - ( - .clk ( clk ), - .drive_value ( drv_device_rx_parity ), - .expected_value ( exp_device_rx_parity ), - .mask ( mask_device_rx_parity ), - .signal ( prb_device_rx_parity )); -//******************************************************************** -//*** TAP Controller State Machine -//******************************************************************** -// TAP state parameters -parameter RESET = 2'b00, - WAIT_63US = 2'b01, - CLOCK = 2'b10, - IDLE = 2'b11; -reg device_rx_parity; -reg [7:0] device_rx_data; -wire device_rx_read; -reg ps2_data_out; -reg dev_host; -reg [1:0] tap_state, next_tap_state; -reg [SIZE-1:0] count; -reg clk_out; -reg [4:0] bit_cnt; -reg ack; -reg [10:0] frame; -reg clk_fall; -reg clk_rise; -reg device_write; -reg [7:0] device_tx_data; -reg device_tx_parity; -reg device_ack; -reg device_stop; -assign drv_device_rx_data = 8'bzzzzzzzz; -assign prb_device_rx_parity = device_rx_parity; -assign prb_device_rx_data = device_rx_data; -assign drv_device_rx_parity = 1'bz; -/* -io_probe_def -#(.MESG ( "ps2 data receive error"), - .WIDTH ( 8)) -device_rx_data_tpb ( - .clk ( clk ), - .drive_value ( drv_device_rx_data ), - .expected_value ( exp_device_rx_data ), - .mask ( mask_device_rx_data ), - .signal ( prb_device_rx_data ) - ); -io_probe_def -#(.MESG ( "ps2 parity receive error")) -device_rx_parity_tpb ( - .clk ( clk ), - .drive_value ( drv_device_rx_parity ), - .expected_value ( exp_device_rx_parity ), - .mask ( mask_device_rx_parity ), - .signal ( prb_device_rx_parity ) - ); -*/ -assign ps2_clk = clk_out ? 1'b0 : 1'bz ; -assign ps2_data = ps2_data_out ? 1'b0 : 1'bz ; -always @(posedge clk or posedge reset ) - begin - if (reset) - begin - tap_state <= RESET; - ps2_data_out <= 1'b0; - end - else - begin - tap_state <= next_tap_state; - ps2_data_out <= ( (tap_state == CLOCK) && (dev_host? frame[0] : ack) ); - end - end -always @(posedge clk or posedge reset ) - begin - if (reset) dev_host <= 1'b0; - else - if( device_write) dev_host <= 1'b1; - else - if( bit_cnt == 5'h16 ) dev_host <= 1'b0; - else dev_host <= dev_host ; - end -always@(*) ack = (((bit_cnt == 5'h14)|| (bit_cnt == 5'h15)) && device_ack ) ; -// next state decode for tap controller -always @(*) - begin - if(device_write) next_tap_state = CLOCK; - else - case (tap_state) // synopsys parallel_case - RESET: - begin - next_tap_state = ps2_clk ? RESET : WAIT_63US ; - end - WAIT_63US: - begin - next_tap_state = ps2_clk ? CLOCK : WAIT_63US ; - end - CLOCK: - begin - next_tap_state = ((bit_cnt == 5'h16)&& (count == 'h0)) ? IDLE : CLOCK; - end - IDLE: - begin - next_tap_state = ps2_data ? IDLE : WAIT_63US; - end - endcase - end -always @(posedge clk or posedge reset ) - begin - if (reset) - begin - count <= CLKCNT; - clk_out <= 1'b0; - bit_cnt <= 5'h00; - clk_fall <= 1'b0; - clk_rise <= 1'b0; - end - else - if((next_tap_state != CLOCK)) - begin - count <= CLKCNT; - clk_out <= 1'b0; - bit_cnt <= 5'h00; - clk_fall <= 1'b0; - clk_rise <= 1'b0; - end - else - if((count == 'h0) ) - begin - count <= CLKCNT; - clk_out <= !clk_out; - bit_cnt <= bit_cnt+5'b0001; - clk_fall <= !clk_out; - clk_rise <= clk_out; - end - else - begin - count <= count - 'h1; - clk_out <= clk_out; - bit_cnt <= bit_cnt; - clk_fall <= 1'b0; - clk_rise <= 1'b0; - end - end -always @(posedge clk or posedge reset ) - begin - if (reset) - begin - frame <= {device_ack,10'h000}; - end - else - if(device_write) - begin - frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1}; - end - else - if((tap_state == WAIT_63US) || (tap_state == IDLE)) - begin - frame <= {device_ack,10'h000}; - end - else - if((tap_state == CLOCK) && clk_fall && !dev_host ) frame <= { ps2_data,frame[10:1]}; - else - if((tap_state == CLOCK) && clk_rise && dev_host ) frame <= { 1'b0,frame[10:1]}; - else frame <= frame; - end -always @(posedge clk or posedge reset ) - begin - if (reset) - begin - device_rx_data <= 8'h00; - device_rx_parity <= 1'b0; - end - else - if(tap_state == WAIT_63US) - begin - device_rx_data <= 8'h00; - device_rx_parity <= 1'b0; - end - else - if((bit_cnt == 5'h12) && clk_rise) - begin - device_rx_data <= frame[10:3]; - device_rx_parity <= ps2_data; - end - else - begin - device_rx_data <= device_rx_data; - device_rx_parity <= device_rx_parity; - end - end -assign device_rx_read = (bit_cnt == 5'h13) && !dev_host && clk_fall; -initial - begin - device_write <= 1'b0; - device_tx_data <= 8'h00; - device_tx_parity <= 1'b0; - device_ack <= 1'b1; - device_stop <= 1'b1; - exp_device_rx_data <= 8'h00; - mask_device_rx_data <= 8'h00; - exp_device_rx_parity <= 1'b0; - mask_device_rx_parity <= 1'b0; - end -task next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask -task send_byte; - input [7:0] byte_out; -begin - while(tap_state != IDLE) next(1); - $display("%t %m %2h parity %b",$realtime ,byte_out,device_tx_parity ); - device_tx_data <= byte_out; - next(1); - device_write <= 1'b1; - next(1); - device_write <= 1'b0; -end -endtask // send_byte -task rcv_byte; - input [7:0] byte_in; - input parity; - begin - exp_device_rx_data <= byte_in; - exp_device_rx_parity <= parity; - while(!device_rx_read) next(1); - $display("%t checking %h %b",$realtime,byte_in,parity); - mask_device_rx_data <= 8'hff; - mask_device_rx_parity <= 1'b1; - next(1); - mask_device_rx_data <= 8'h00; - mask_device_rx_parity <= 1'b0; -end -endtask -always@(posedge clk) - if( device_rx_read) - $display ("%t %m device rec %h parity %b",$realtime,device_rx_data,device_rx_parity); -always@(posedge clk) - if(device_write) - $display ("%t %m device send %h parity %b stop %b ",$realtime,device_tx_data,device_tx_parity,device_stop); - endmodule Index: Geda/src/clock_gen_def.v =================================================================== --- Geda/src/clock_gen_def.v (revision 134) +++ Geda/src/clock_gen_def.v (nonexistent) @@ -1,160 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - - - -module clock_gen_def -#(parameter STOP_WIDTH = 1, - parameter BAD_WIDTH = 1 -) - - (input wire clk, - input wire START, - input wire [STOP_WIDTH-1:0] STOP, - input wire [BAD_WIDTH-1:0] BAD, - output reg FINISH, - output reg FAIL, - output reg reset - ); - -reg task_reset; -reg task_FAIL; -reg task_FINISH; - - - - - - -always@(posedge clk or negedge START) - if(!START) FINISH <= 0; - else FINISH <= (|STOP) || FINISH || task_FINISH; - - - -always@(posedge clk or negedge START) - if(!START) FAIL <= 0; - else FAIL <= task_FAIL || (|BAD); - - -always@(posedge clk or negedge START) - if(!START) reset <= 1'b1; - else reset <= task_reset; - - - - - - -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask // next - - - - - -initial - begin - task_FINISH <= 0; - task_FAIL <= 0; - task_reset <= 0; - end - - - -task reset_on; - task_reset = 1; -endtask // reset_on - -task reset_off; - begin - task_reset = 0; - end -endtask // reset_off - - - - -task automatic fail; - input [799:0] message; - begin - task_FAIL <= 1; - $display("%t Simulation FAILURE: %s ",$realtime,message ); - @(posedge clk); - task_FAIL <= 0; - end -endtask - - - - - - - -task exit; - begin - @(posedge clk); - task_FINISH <= 1; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end -endtask - - - - - - - - - - - -endmodule - - - Index: Geda/src/jtag_model_def.v =================================================================== --- Geda/src/jtag_model_def.v (revision 134) +++ Geda/src/jtag_model_def.v (nonexistent) @@ -1,223 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* JTAG Hoset model for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - jtag_model_def - #( parameter - DIVCNT=4'h1, - SIZE=4) - ( - input wire clk, - input wire reset, - input wire tdi, - output reg tclk, - output reg tdo, - output reg tms, - output reg trst_n); -reg tclk_enable; -reg [SIZE-1:0] tclk_counter; -wire next_tclk_edge; -wire next_tclk_pos_edge; -wire next_tclk_neg_edge; -assign next_tclk_edge = (tclk_counter == 4'h0); -assign next_tclk_pos_edge = next_tclk_edge && (!tclk) ; -assign next_tclk_neg_edge = next_tclk_edge && ( tclk) ; -always@(posedge clk) - if(reset) tclk_counter <= DIVCNT; - else - if(|tclk_counter) tclk_counter <= tclk_counter-4'h1; - else tclk_counter <= DIVCNT; -always@(posedge clk) - if(reset) tclk <= 1'b0; - else - if(!tclk_enable) tclk <= tclk; - else - if( next_tclk_pos_edge ) tclk <= 1'b1; - else - if( next_tclk_neg_edge ) tclk <= 1'b0; - else tclk <= tclk; -reg actual; -initial - begin - tclk_enable <= 1'b0; - tclk <= 1'b0; - tdo <= 1'b1; - tms <= 1'b1; - trst_n <= 1'b0; - end -task automatic next; - input [31:0] num; - repeat (num) @ (posedge clk); -endtask -task enable_tclk; -begin - tclk_enable <= 1'b1; -end -endtask -task enable_trst_n; -begin -Clk_bit(1,1,actual); -Clk_bit(1,1,actual); -Clk_bit(1,1,actual); -Clk_bit(1,1,actual); -Clk_bit(1,1,actual); - trst_n <= 1'b1; -Clk_bit(1,1,actual); -end -endtask -task enable_reset; -begin -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -Clk_bit(1,0,actual); -end -endtask -task init; -begin -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -Clk_bit(0,0,actual); -end -endtask -task Clk_bit; - input TMS; - input TDO; - output ACT; - begin - while (next_tclk_neg_edge != 1) - begin - next(1); - end - if(TMS) tms <= 1'b1; - else tms <= 1'b0; - if ( TDO == 1 ) tdo <= 1'b1; - else if( TDO == 0 ) tdo <= 1'b0; - else tdo <= 1'bx; - while (next_tclk_pos_edge != 1) - begin - next(1); - end - ACT = tdi; - end -endtask -/******************************************************************************/ -/* LoadTapInst (); */ -/******************************************************************************/ -task LoadTapInst; // Load a Tap Instruction that uses the Boundary Register - parameter [15:0] JTAG_INST_LENGTH = 4; - input [JTAG_INST_LENGTH:1] Inst; // This task starts & ends with the Tap in the RT_IDLE state - input [JTAG_INST_LENGTH:1] Inst_Return; // - integer i; - reg [JTAG_INST_LENGTH:1] Ack; - begin - Clk_bit(1'b1,1'b0,actual); // Transition from RT_IDLE to SELECT_DR - Clk_bit(1'b1,1'b0,actual); // Transition from SELECT_DR to SELECT_IR - Clk_bit(1'b0,1'b0,actual); // Transition from SELECT_IR to CAPTURE_IR - Clk_bit(1'b0,1'b0,actual); // Transition from CAPTURE_IR to SHIFT_IR - for (i = 1; i <= JTAG_INST_LENGTH; i = i+1) // Shift in Inst - begin - Clk_bit(( i == JTAG_INST_LENGTH),Inst[i],Ack[i]); - end - $display ("%t %m LoadTapInst %b Expected %b Received %b " ,$realtime,Inst, Inst_Return, Ack ); - if (Ack !== Inst_Return) - begin - cg.fail (" LoadTapInst receive error "); - end - Clk_bit(1'b1,1'b0,actual); // Transition from EXIT1_IR to UPDATE_IR - Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE_IR to RT_IDLE - end -endtask // LoadTapInst -//***************************************************************************/ -//* Shift Register -//***************************************************************************/ -task automatic Shift_Register; // Initialize boundary register with outputs disabled - // This tasks starts at RT_IDLE and ends at SHIFT_DR - parameter [15:0] LENGTH = 100; - input length; - input [LENGTH:1] Dataout; - integer length; - integer i; - reg [LENGTH:1] DataBack; - begin - Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR - Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR - Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR - for (i = 1; i <= length; i = i+1) - Clk_bit((i==length),Dataout[i],DataBack[i]); - $display ("%t %m Shift_data -%d wr-%h rd-%h ",$realtime,length,Dataout[LENGTH:1],DataBack[LENGTH:1]); - Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR - Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE - end -endtask // ShiftRegister -task automatic Shift_Cmp_32; // Initialize boundary register with outputs disabled - // This tasks starts at RT_IDLE and ends at SHIFT_DR - parameter [15:0] LENGTH = 32; - input [LENGTH:1] Dataout; - input [LENGTH:1] DataExp; - integer i; - reg [LENGTH:1] DataBack; - begin - Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR - Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR - Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR - for (i = 1; i <= LENGTH; i = i+1) - Clk_bit((i==LENGTH),Dataout[i],DataBack[i]); - $display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack ); - if (DataBack !== DataExp ) - begin - cg.fail (" Shift_cmp receive error "); - end - Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR - Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE - end -endtask // ShiftRegister - endmodule Index: Geda/src/display_model_def.v =================================================================== --- Geda/src/display_model_def.v (revision 134) +++ Geda/src/display_model_def.v (nonexistent) @@ -1,93 +0,0 @@ -/**********************************************************************/ -/* */ -/* ------- */ -/* / SOC \ */ -/* / GEN \ */ -/* / SIM \ */ -/* ============== */ -/* | | */ -/* |____________| */ -/* */ -/* Clock and Reset generator for simulations */ -/* */ -/* */ -/* Author(s): */ -/* - John Eaton, jt_eaton@opencores.org */ -/* */ -/**********************************************************************/ -/* */ -/* Copyright (C) <2010> */ -/* */ -/* This source file may be used and distributed without */ -/* restriction provided that this copyright statement is not */ -/* removed from the file and that any derivative work contains */ -/* the original copyright notice and the associated disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it */ -/* and/or modify it under the terms of the GNU Lesser General */ -/* Public License as published by the Free Software Foundation; */ -/* either version 2.1 of the License, or (at your option) any */ -/* later version. */ -/* */ -/* This source is distributed in the hope that it will be */ -/* useful, but WITHOUT ANY WARRANTY; without even the implied */ -/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ -/* PURPOSE. See the GNU Lesser General Public License for more */ -/* details. */ -/* */ -/* You should have received a copy of the GNU Lesser General */ -/* Public License along with this source; if not, download it */ -/* from http://www.opencores.org/lgpl.shtml */ -/* */ -/**********************************************************************/ - module - display_model_def - ( - input wire clk, - input wire dp, - input wire reset, - input wire [ 3 : 0] an, - input wire [ 6 : 0] seg); -reg [3:0] decode; -always@(*) -if (seg == 7'b1000000) decode = 4'b0000; -else if (seg == 7'b1111001) decode = 4'b0001; -else if (seg == 7'b0100100) decode = 4'b0010; -else if (seg == 7'b0110000) decode = 4'b0011; -else if (seg == 7'b0011001) decode = 4'b0100; -else if (seg == 7'b0010010) decode = 4'b0101; -else if (seg == 7'b0000010) decode = 4'b0110; -else if (seg == 7'b1111000) decode = 4'b0111; -else if (seg == 7'b0000000) decode = 4'b1000; -else if (seg == 7'b0011000) decode = 4'b1001; -else if (seg == 7'b0001000) decode = 4'b1010; -else if (seg == 7'b0000011) decode = 4'b1011; -else if (seg == 7'b1000110) decode = 4'b1100; -else if (seg == 7'b0100001) decode = 4'b1101; -else if (seg == 7'b0000110) decode = 4'b1110; -else decode = 4'b1111; -reg [3:0] segment0; -reg [3:0] segment1; -reg [3:0] segment2; -reg [3:0] segment3; -always@(posedge clk) -if(reset) segment0 <= 4'h0; -else -if(!an[0]) segment0 <= decode; -else segment0 <= segment0; -always@(posedge clk) -if(reset) segment1 <= 4'h0; -else -if(!an[1]) segment1 <= decode; -else segment1 <= segment1; -always@(posedge clk) -if(reset) segment2 <= 4'h0; -else -if(!an[2]) segment2 <= decode; -else segment2 <= segment2; -always@(posedge clk) -if(reset) segment3 <= 4'h0; -else -if(!an[3]) segment3 <= decode; -else segment3 <= segment3; - endmodule Index: Geda/sym/uart_model_def.sym =================================================================== --- Geda/sym/uart_model_def.sym (revision 134) +++ Geda/sym/uart_model_def.sym (nonexistent) @@ -1,34 +0,0 @@ -v 20100214 1 -B 300 0 1700 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1050 5 10 1 1 0 0 1 1 -device=uart_model_def -T 400 1250 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=txd_in -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 2000 200 2300 200 4 0 1 -{ -T 1900 200 5 10 1 1 0 7 1 1 -pinnumber=rxd_out -T 2000 200 5 10 0 1 0 7 1 1 -pinseq=4 -} Index: Geda/sym/vga_model_def.sym =================================================================== --- Geda/sym/vga_model_def.sym (revision 134) +++ Geda/sym/vga_model_def.sym (nonexistent) @@ -1,55 +0,0 @@ -v 20100214 1 -B 300 0 1400 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1850 5 10 1 1 0 0 1 1 -device=vga_model_def -T 400 2050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=red[2:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=green[2:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 10 1 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=blue[1:0] -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=vsync_n -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=hsync_n -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} Index: Geda/sym/io_probe_def.sym =================================================================== --- Geda/sym/io_probe_def.sym (revision 134) +++ Geda/sym/io_probe_def.sym (nonexistent) @@ -1,41 +0,0 @@ -v 20100214 1 -B 300 0 4600 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1250 5 10 1 1 0 0 1 1 -device=io_probe_def -T 400 1450 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=mask[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=expected_value[WIDTH-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 10 1 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=drive_value[WIDTH-1:0] -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 4900 200 5200 200 10 1 1 -{ -T 4800 200 5 10 1 1 0 7 1 1 -pinnumber=signal[WIDTH-1:0] -T 4800 200 5 10 0 1 0 7 1 1 -pinseq=5 -} Index: Geda/sym/or1200_dbg_model_def.sym =================================================================== --- Geda/sym/or1200_dbg_model_def.sym (revision 134) +++ Geda/sym/or1200_dbg_model_def.sym (nonexistent) @@ -1,20 +0,0 @@ -v 20100214 1 -B 300 0 900 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 850 5 10 1 1 0 0 1 1 -device=or1200_dbg_model_def -T 400 1050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} Index: Geda/sym/mt45w8mw12_def.sym =================================================================== --- Geda/sym/mt45w8mw12_def.sym (revision 134) +++ Geda/sym/mt45w8mw12_def.sym (nonexistent) @@ -1,83 +0,0 @@ -v 20100214 1 -B 300 0 3800 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 2250 5 10 1 1 0 0 1 1 -device=mt45w8mw12_def -T 400 2450 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=addr[ADDR_BITS-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=we_n -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=ub_n -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=oe_n -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=lb_n -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=cre -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} -P 300 1600 0 1600 4 0 1 -{ -T 400 1600 5 10 1 1 0 1 1 1 -pinnumber=ce_n -T 400 1600 5 10 0 1 0 1 1 1 -pinseq=8 -} -P 300 1800 0 1800 4 0 1 -{ -T 400 1800 5 10 1 1 0 1 1 1 -pinnumber=adv_n -T 400 1800 5 10 0 1 0 1 1 1 -pinseq=9 -} -P 4100 200 4400 200 4 0 1 -{ -T 4000 200 5 10 1 1 0 7 1 1 -pinnumber=o_wait -T 4100 200 5 10 0 1 0 7 1 1 -pinseq=10 -} -P 4100 400 4400 400 10 1 1 -{ -T 4000 400 5 10 1 1 0 7 1 1 -pinnumber=dq[DQ_BITS-1:0] -T 4000 400 5 10 0 1 0 7 1 1 -pinseq=11 -} Index: Geda/sym/ps2_host_def.sym =================================================================== --- Geda/sym/ps2_host_def.sym (revision 134) +++ Geda/sym/ps2_host_def.sym (nonexistent) @@ -1,83 +0,0 @@ -v 20100214 1 -B 300 0 2700 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 2250 5 10 1 1 0 0 1 1 -device=ps2_host_def -T 400 2450 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=rx_read -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=rx_parity_rcv -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=rx_parity_error -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=rx_parity_cal -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=rx_full -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=rx_frame_error -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} -P 300 1600 0 1600 4 0 1 -{ -T 400 1600 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1600 5 10 0 1 0 1 1 1 -pinseq=8 -} -P 300 1800 0 1800 4 0 1 -{ -T 400 1800 5 10 1 1 0 1 1 1 -pinnumber=busy -T 400 1800 5 10 0 1 0 1 1 1 -pinseq=9 -} -P 3000 200 3300 200 4 0 1 -{ -T 2900 200 5 10 1 1 0 7 1 1 -pinnumber=tx_write -T 3000 200 5 10 0 1 0 7 1 1 -pinseq=10 -} -P 3000 400 3300 400 4 0 1 -{ -T 2900 400 5 10 1 1 0 7 1 1 -pinnumber=rx_clr -T 3000 400 5 10 0 1 0 7 1 1 -pinseq=11 -} Index: Geda/sym/micro_bus_model_def.sym =================================================================== --- Geda/sym/micro_bus_model_def.sym (revision 134) +++ Geda/sym/micro_bus_model_def.sym (nonexistent) @@ -1,62 +0,0 @@ -v 20100214 1 -B 300 0 2900 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1650 5 10 1 1 0 0 1 1 -device=micro_bus_model_def -T 400 1850 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 3200 200 3500 200 10 1 1 -{ -T 3100 200 5 10 1 1 0 7 1 1 -pinnumber=wdata[7:0] -T 3100 200 5 10 0 1 0 7 1 1 -pinseq=3 -} -P 3200 400 3500 400 10 1 1 -{ -T 3100 400 5 10 1 1 0 7 1 1 -pinnumber=addr[addr_width-1:0] -T 3100 400 5 10 0 1 0 7 1 1 -pinseq=4 -} -P 3200 600 3500 600 4 0 1 -{ -T 3100 600 5 10 1 1 0 7 1 1 -pinnumber=wr -T 3200 600 5 10 0 1 0 7 1 1 -pinseq=5 -} -P 3200 800 3500 800 4 0 1 -{ -T 3100 800 5 10 1 1 0 7 1 1 -pinnumber=rd -T 3200 800 5 10 0 1 0 7 1 1 -pinseq=6 -} -P 3200 1000 3500 1000 4 0 1 -{ -T 3100 1000 5 10 1 1 0 7 1 1 -pinnumber=cs -T 3200 1000 5 10 0 1 0 7 1 1 -pinseq=7 -} -P 3200 1200 3500 1200 10 1 1 -{ -T 3100 1200 5 10 1 1 0 7 1 1 -pinnumber=rdata[7:0] -T 3100 1200 5 10 0 1 0 7 1 1 -pinseq=8 -} Index: Geda/sym/ps2_model_def.sym =================================================================== --- Geda/sym/ps2_model_def.sym (revision 134) +++ Geda/sym/ps2_model_def.sym (nonexistent) @@ -1,34 +0,0 @@ -v 20100214 1 -B 300 0 1700 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 850 5 10 1 1 0 0 1 1 -device=ps2_model_def -T 400 1050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 2000 200 2300 200 4 0 1 -{ -T 1900 200 5 10 1 1 0 7 1 1 -pinnumber=ps2_data -T 2000 200 5 10 0 1 0 7 1 1 -pinseq=3 -} -P 2000 400 2300 400 4 0 1 -{ -T 1900 400 5 10 1 1 0 7 1 1 -pinnumber=ps2_clk -T 2000 400 5 10 0 1 0 7 1 1 -pinseq=4 -} Index: Geda/sym/clock_gen_def.sym =================================================================== --- Geda/sym/clock_gen_def.sym (revision 134) +++ Geda/sym/clock_gen_def.sym (nonexistent) @@ -1,55 +0,0 @@ -v 20100214 1 -B 300 0 3000 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1250 5 10 1 1 0 0 1 1 -device=clock_gen_def -T 400 1450 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=STOP[STOP_WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=BAD[BAD_WIDTH-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=START -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 3300 200 3600 200 4 0 1 -{ -T 3200 200 5 10 1 1 0 7 1 1 -pinnumber=reset -T 3300 200 5 10 0 1 0 7 1 1 -pinseq=5 -} -P 3300 400 3600 400 4 0 1 -{ -T 3200 400 5 10 1 1 0 7 1 1 -pinnumber=FINISH -T 3300 400 5 10 0 1 0 7 1 1 -pinseq=6 -} -P 3300 600 3600 600 4 0 1 -{ -T 3200 600 5 10 1 1 0 7 1 1 -pinnumber=FAIL -T 3300 600 5 10 0 1 0 7 1 1 -pinseq=7 -} Index: Geda/sym/jtag_model_def.sym =================================================================== --- Geda/sym/jtag_model_def.sym (revision 134) +++ Geda/sym/jtag_model_def.sym (nonexistent) @@ -1,55 +0,0 @@ -v 20100214 1 -B 300 0 1500 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1250 5 10 1 1 0 0 1 1 -device=jtag_model_def -T 400 1450 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=tdi -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 1800 200 2100 200 4 0 1 -{ -T 1700 200 5 10 1 1 0 7 1 1 -pinnumber=trst_n -T 1800 200 5 10 0 1 0 7 1 1 -pinseq=4 -} -P 1800 400 2100 400 4 0 1 -{ -T 1700 400 5 10 1 1 0 7 1 1 -pinnumber=tms -T 1800 400 5 10 0 1 0 7 1 1 -pinseq=5 -} -P 1800 600 2100 600 4 0 1 -{ -T 1700 600 5 10 1 1 0 7 1 1 -pinnumber=tdo -T 1800 600 5 10 0 1 0 7 1 1 -pinseq=6 -} -P 1800 800 2100 800 4 0 1 -{ -T 1700 800 5 10 1 1 0 7 1 1 -pinnumber=tclk -T 1800 800 5 10 0 1 0 7 1 1 -pinseq=7 -} Index: Geda/sym/display_model_def.sym =================================================================== --- Geda/sym/display_model_def.sym (revision 134) +++ Geda/sym/display_model_def.sym (nonexistent) @@ -1,41 +0,0 @@ -v 20100214 1 -B 300 0 1200 1300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1450 5 10 1 1 0 0 1 1 -device=display_model_def -T 400 1650 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=seg[6:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=an[3:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=dp -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} Index: Geda/sym/io_probe_in.sym =================================================================== --- Geda/sym/io_probe_in.sym (revision 134) +++ Geda/sym/io_probe_in.sym (nonexistent) @@ -1,34 +0,0 @@ -v 20100214 1 -B 300 0 2900 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1250 5 10 1 1 0 0 1 1 -device=io_probe_in -T 400 1450 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=signal[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=mask[WIDTH-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 10 1 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=expected_value[WIDTH-1:0] -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} Index: Geda/sym/uart_host_def.sym =================================================================== --- Geda/sym/uart_host_def.sym (revision 134) +++ Geda/sym/uart_host_def.sym (nonexistent) @@ -1,69 +0,0 @@ -v 20100214 1 -B 300 0 3600 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1650 5 10 1 1 0 0 1 1 -device=uart_host_def -T 400 1850 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=txd_buffer_empty -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=rxd_stop_error -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=rxd_parity_error -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=rxd_data_avail -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 3900 200 4200 200 4 0 1 -{ -T 3800 200 5 10 1 1 0 7 1 1 -pinnumber=txd_parity -T 3900 200 5 10 0 1 0 7 1 1 -pinseq=7 -} -P 3900 400 4200 400 4 0 1 -{ -T 3800 400 5 10 1 1 0 7 1 1 -pinnumber=txd_force_parity -T 3900 400 5 10 0 1 0 7 1 1 -pinseq=8 -} -P 3900 600 4200 600 4 0 1 -{ -T 3800 600 5 10 1 1 0 7 1 1 -pinnumber=parity_enable -T 3900 600 5 10 0 1 0 7 1 1 -pinseq=9 -} Index: Geda/sym/micro_bus16_model_def.sym =================================================================== --- Geda/sym/micro_bus16_model_def.sym (revision 134) +++ Geda/sym/micro_bus16_model_def.sym (nonexistent) @@ -1,69 +0,0 @@ -v 20100214 1 -B 300 0 2000 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1850 5 10 1 1 0 0 1 1 -device=micro_bus16_model_def -T 400 2050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 4 0 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 2300 200 2600 200 10 1 1 -{ -T 2200 200 5 10 1 1 0 7 1 1 -pinnumber=wdata[15:0] -T 2200 200 5 10 0 1 0 7 1 1 -pinseq=3 -} -P 2300 400 2600 400 10 1 1 -{ -T 2200 400 5 10 1 1 0 7 1 1 -pinnumber=addr[23:0] -T 2200 400 5 10 0 1 0 7 1 1 -pinseq=4 -} -P 2300 600 2600 600 4 0 1 -{ -T 2200 600 5 10 1 1 0 7 1 1 -pinnumber=wr -T 2300 600 5 10 0 1 0 7 1 1 -pinseq=5 -} -P 2300 800 2600 800 4 0 1 -{ -T 2200 800 5 10 1 1 0 7 1 1 -pinnumber=ub -T 2300 800 5 10 0 1 0 7 1 1 -pinseq=6 -} -P 2300 1000 2600 1000 4 0 1 -{ -T 2200 1000 5 10 1 1 0 7 1 1 -pinnumber=rd -T 2300 1000 5 10 0 1 0 7 1 1 -pinseq=7 -} -P 2300 1200 2600 1200 4 0 1 -{ -T 2200 1200 5 10 1 1 0 7 1 1 -pinnumber=lb -T 2300 1200 5 10 0 1 0 7 1 1 -pinseq=8 -} -P 2300 1400 2600 1400 10 1 1 -{ -T 2200 1400 5 10 1 1 0 7 1 1 -pinnumber=rdata[15:0] -T 2200 1400 5 10 0 1 0 7 1 1 -pinseq=9 -} Index: html/or1200_dbg_model_def.html =================================================================== --- html/or1200_dbg_model_def.html (revision 134) +++ html/or1200_dbg_model_def.html (nonexistent) @@ -1,240 +0,0 @@ - - - - - start - - - - - - - - - - -
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axi_rvalid
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axi_wready
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clk
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reset
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axi_bid[11:0]
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axi_bresp[1:0]
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axi_rid[11:0]
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rdata_tpb
opencores.org
Testbench
io_probe
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html/axi_model_master.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/axi_model_slave.html =================================================================== --- html/axi_model_slave.html (nonexistent) +++ html/axi_model_slave.html (revision 135) @@ -0,0 +1,305 @@ + + + + + start + + + + + + + + + + +
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NAME
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Description

axi_arvalid
input

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input

axi_bready
input

axi_rready
input

axi_wlast
input

axi_wvalid
input

clk
input

reset
input

axi_araddr[31:0]
input

axi_arburst[1:0]
input

axi_arid[11:0]
input

axi_arlen[7:0]
input

axi_arsize[2:0]
input

axi_awaddr[31:0]
input

axi_awburst[1:0]
input

axi_awid[11:0]
input

axi_awlen[7:0]
input

axi_awsize[2:0]
input

axi_wdata[31:0]
input

axi_wstrb[3:0]
input

axi_arready
output

axi_awready
output

axi_bvalid
output

axi_rlast
output

axi_rvalid
output

axi_wready
output

axi_bid[11:0]
output

axi_bresp[1:0]
output

axi_rdata[31:0]
output

axi_rid[11:0]
output

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
wdata_tpb
opencores.org
Testbench
io_probe
in
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+ +

html/axi_model_slave.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/clock_gen_def.html =================================================================== --- html/clock_gen_def.html (revision 134) +++ html/clock_gen_def.html (revision 135) @@ -1,240 +1,188 @@ - - - - - start - - - - - - - - - - -
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SOCGEN Datasheet:
+
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clock_gen_def
+
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+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
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+
Interface
+
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Children
+
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Theory of Operation
+
+
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+ + +
+
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+
Parameters
+
+
+ + + + + + + + + + + + + + + + + + + +
Name
default
Description
BAD_WIDTH
1

STOP_WIDTH
1

+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

START
input

clk
input

BAD[BAD_WIDTH-1:0]
input

STOP[STOP_WIDTH-1:0]
input

FAIL
output

FINISH
output

reset
output

+

+
+
Children
+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+

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+ + Index: html/display_model_def.html =================================================================== --- html/display_model_def.html (revision 134) +++ html/display_model_def.html (revision 135) @@ -1,111 +1,168 @@ - - - - - start - - - - - - - - - - -
SOCGEN Datasheet:
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SOCGEN Datasheet:
+
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display_model_def
+
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+
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+
+
SourceCode
+
+
+
+
Parameters
+
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+
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Interface
+
+
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Children
+
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+
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Theory of Operation
+
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+ + +
+
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+
Parameters
+
+
+ + + + + + + + + +
Name
default
Description
+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

dp
input

reset
input

an[3:0]
input

seg[6:0]
input

+

+
+
Children
+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+

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+
+
+ + Index: html/io_host_model_def.html =================================================================== --- html/io_host_model_def.html (nonexistent) +++ html/io_host_model_def.html (revision 135) @@ -0,0 +1,198 @@ + + + + + start + + + + + + + + + + +
SOCGEN Datasheet:
+
+
+
+
+
io_host_model_def
+
+
+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
+
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Interface
+
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Children
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Theory of Operation
+
+
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+ + +
+
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Parameters
+
+
+ + + + + + + + + +
Name
default
Description
+

+
+

+
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+
+

+
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Interface
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

io_host_in_ready
input

io_host_out_valid
input

reset
input

io_host_out_bits[15:0]
input

io_host_clk
output

io_host_clk_edge
output

io_host_debug_stats_pcr
output

io_host_in_valid
output

io_host_out_ready
output

io_host_in_bits[15:0]
output

+

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+ +

html/io_host_model_def.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/io_mem_model_def.html =================================================================== --- html/io_mem_model_def.html (nonexistent) +++ html/io_mem_model_def.html (revision 135) @@ -0,0 +1,238 @@ + + + + + start + + + + + + + + + + +
SOCGEN Datasheet:
+
+
+
+
+
io_mem_model_def
+
+
+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
+
+
Interface
+
+
+
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Children
+
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Theory of Operation
+
+
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+ + +
+
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+
Parameters
+
+
+ + + + + + + + + +
Name
default
Description
+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

io_mem_req_cmd_bits_rw
input

io_mem_req_cmd_valid
input

io_mem_req_data_valid
input

reset
input

io_mem_req_cmd_bits_addr[25:0]
input

io_mem_req_cmd_bits_tag[4:0]
input

io_mem_req_data_bits_data[127:0]
input

io_in_mem_ready
output

io_in_mem_valid
output

io_mem_backup_en
output

io_mem_req_cmd_ready
output

io_mem_req_data_ready
output

io_mem_resp_ready
output

io_mem_resp_valid
output

io_out_mem_ready
output

io_out_mem_valid
output

io_mem_resp_bits_data[127:0]
output

io_mem_resp_bits_tag[4:0]
output

+

+
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+

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+ +

html/io_mem_model_def.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/io_probe_def.html =================================================================== --- html/io_probe_def.html (revision 134) +++ html/io_probe_def.html (revision 135) @@ -1,240 +1,198 @@ - - - - - start - - - - - - - - - - -
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SOCGEN Datasheet:
+
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io_probe_def
+
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+
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SourceCode
+
+
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+
Parameters
+
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Interface
+
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Children
+
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Theory of Operation
+
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Parameters
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
IN_DELAY
5

MESG
" "

OUT_DELAY
15

OUT_WIDTH
10

RESET
{WIDTH{1'bz}}

WIDTH
1

+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

drive_value[WIDTH-1:0]
input

expected_value[WIDTH-1:0]
input

mask[WIDTH-1:0]
input

signal[WIDTH-1:0]
inout

+

+
+
Children
+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+

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+
+ + Index: html/io_probe_in.html =================================================================== --- html/io_probe_in.html (revision 134) +++ html/io_probe_in.html (revision 135) @@ -1,240 +1,178 @@ - - - - - start - - - - - - - - - - -
SOCGEN Datasheet:
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SOCGEN Datasheet:
+
+
+
+
+
io_probe_in
+
+
+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
+
+
Interface
+
+
+
+
Children
+
+
+
+
Theory of Operation
+
+
+
+ + +
+
+
+
Parameters
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
IN_DELAY
5

MESG
" "

WIDTH
1

+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

expected_value[WIDTH-1:0]
input

mask[WIDTH-1:0]
input

signal[WIDTH-1:0]
input

+

+
+
Children
+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: html/jtag_model_def.html =================================================================== --- html/jtag_model_def.html (revision 134) +++ html/jtag_model_def.html (revision 135) @@ -1,240 +1,188 @@ - - - - - start - - - - - - - - - - -
SOCGEN Datasheet:
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Description
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Theory of Operation
-
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Description
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Theory of Operation
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- - + + + + + start + + + + + + + + + + +
SOCGEN Datasheet:
+
+
+
+
+
jtag_model_def
+
+
+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
+
+
Interface
+
+
+
+
Children
+
+
+
+
Theory of Operation
+
+
+
+ + +
+
+
+
Parameters
+
+
+ + + + + + + + + + + + + + + + + + + +
Name
default
Description
DIVCNT
4'h1

SIZE
4

+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

reset
input

tdi
input

tclk
output

tdo
output

tms
output

trst_n
output

+

+
+
Children
+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+

+
+
+
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+ + Index: html/micro_bus16_model_def.html =================================================================== --- html/micro_bus16_model_def.html (revision 134) +++ html/micro_bus16_model_def.html (revision 135) @@ -1,240 +1,210 @@ - - - - - start - - - - - - - - - - -
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SourceCode
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Parameters
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Name
default
Description
DELAY
15

WIDTH
16

+

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+

+
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+
+

+
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+
Interface
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

reset
input

rdata[15:0]
input

lb
output

rd
output

ub
output

wr
output

addr[23:0]
output

cs[1:0]
output

wdata[15:0]
output

+

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+
Children
+
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Instance
Vendor
Library
Component
Version
rdata_tpb
opencores.org
Testbench
io_probe
in
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+ + Index: html/micro_bus_model_def.html =================================================================== --- html/micro_bus_model_def.html (revision 134) +++ html/micro_bus_model_def.html (revision 135) @@ -1,240 +1,205 @@ - - - - - start - - - - - - - - - - -
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micro_bus_model_def
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SourceCode
+
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Parameters
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Interface
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Theory of Operation
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Parameters
+
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+ + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
OUT_DELAY
15

OUT_WIDTH
10

addr_width
16

+

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+
+

+
+

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+
Interface
+
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+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

reset
input

cs
output

rd
output

wr
output

addr[addr_width-1:0]
output

wdata[7:0]
output

rdata[7:0]
inout

+

+
+
Children
+
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Instance
Vendor
Library
Component
Version
rdata_tpb
opencores.org
Testbench
io_probe
in
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+ + Index: html/mt45w8mw12_def.html =================================================================== --- html/mt45w8mw12_def.html (revision 134) +++ html/mt45w8mw12_def.html (revision 135) @@ -1,240 +1,213 @@ - - - - - start - - - - - - - - - - -
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SourceCode
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Parameters
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Name
default
Description
ADDR_BITS
23

DQ_BITS
16

MEM_BITS
16

+

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+
Interface
+
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NAME
Type
Description

adv_n
input

ce_n
input

clk
input

cre
input

lb_n
input

oe_n
input

ub_n
input

we_n
input

addr[ADDR_BITS-1:0]
input

o_wait
output

dq[DQ_BITS-1:0]
inout

+

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Children
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Instance
Vendor
Library
Component
Version
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+ + Index: html/ps2_host_def.html =================================================================== --- html/ps2_host_def.html (revision 134) +++ html/ps2_host_def.html (revision 135) @@ -1,240 +1,227 @@ - - - - - start - - - - - - - - - - -
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SOCGEN Datasheet:
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ps2_host_def
+
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SourceCode
+
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Parameters
+
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Interface
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Theory of Operation
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Name
default
Description
+

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Interface
+
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+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

busy
input

clk
input

reset
input

rx_frame_error
input

rx_full
input

rx_parity_cal
input

rx_parity_error
input

rx_parity_rcv
input

rx_read
input

tx_ack_error
input

rx_data[7:0]
input

rx_clr
output

tx_write
output

tx_data[7:0]
output

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
tx_ack_err_tpb
opencores.org
Testbench
io_probe
in
rcv_byte_tpb
opencores.org
Testbench
io_probe
in
+

+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+ + Index: html/ps2_model_def.html =================================================================== --- html/ps2_model_def.html (revision 134) +++ html/ps2_model_def.html (revision 135) @@ -1,240 +1,177 @@ - - - - - start - - - - - - - - - - -
SOCGEN Datasheet:
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SOCGEN Datasheet:
+
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+
+
+
ps2_model_def
+
+
+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
+
+
Interface
+
+
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Children
+
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Theory of Operation
+
+
+
+ + +
+
+
+
Parameters
+
+
+ + + + + + + + + + + + + + + + + + + +
Name
default
Description
CLKCNT
10'h1f0

SIZE
10

+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

reset
input

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
device_rx_data_tpb
opencores.org
Testbench
io_probe
def
device_rx_parity_tpb
opencores.org
Testbench
io_probe
def
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+ + Index: html/spi_host_def.html =================================================================== --- html/spi_host_def.html (nonexistent) +++ html/spi_host_def.html (revision 135) @@ -0,0 +1,227 @@ + + + + + start + + + + + + + + + + +
SOCGEN Datasheet:
+
+
+
+
+
spi_host_def
+
+
+
+
+
+
SourceCode
+
+
+
+
Parameters
+
+
+
+
Interface
+
+
+
+
Children
+
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+
+
Theory of Operation
+
+
+
+ + +
+
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Parameters
+
+
+ + + + + + + + + +
Name
default
Description
+

+
+

+
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+
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Interface
+
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NAME
Type
Description

busy
input

clk
input

reset
input

rx_frame_error
input

rx_full
input

rx_parity_cal
input

rx_parity_error
input

rx_parity_rcv
input

rx_read
input

tx_ack_error
input

rx_data[7:0]
input

rx_clr
output

tx_write
output

tx_data[7:0]
output

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
tx_ack_err_tpb
opencores.org
Testbench
io_probe
in
rcv_byte_tpb
opencores.org
Testbench
io_probe
in
+

+
+
+
+
+
+
+
+
+
+
+
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html/spi_host_def.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/spi_model_def.html =================================================================== --- html/spi_model_def.html (nonexistent) +++ html/spi_model_def.html (revision 135) @@ -0,0 +1,177 @@ + + + + + start + + + + + + + + + + +
SOCGEN Datasheet:
+
+
+
+
+
spi_model_def
+
+
+
+
+
+
SourceCode
+
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+
+
Parameters
+
+
+
+
Interface
+
+
+
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Children
+
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Theory of Operation
+
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+
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Parameters
+
+
+ + + + + + + + + + + + + + + + + + + +
Name
default
Description
CLKCNT
10'h1f0

SIZE
10

+

+
+

+
+

+
+

+
+
+
Interface
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

reset
input

+

+
+
Children
+
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Vendor
Library
Component
Version
device_rx_data_tpb
opencores.org
Testbench
io_probe
def
device_rx_parity_tpb
opencores.org
Testbench
io_probe
def
+

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html/spi_model_def.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/spi_model_master.html =================================================================== --- html/spi_model_master.html (nonexistent) +++ html/spi_model_master.html (revision 135) @@ -0,0 +1,190 @@ + + + + + start + + + + + + + + + + +
SOCGEN Datasheet:
+
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spi_model_master
+
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SourceCode
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Name
default
Description
CLKCNT
10'h1f0

SIZE
10

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Type
Description

clk
input

reset
input

spi_miso
input

spi_clk
output

spi_mosi
output

spi_sel_n
output

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
device_rx_data_tpb
opencores.org
Testbench
io_probe
in
+

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html/spi_model_master.html Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: html/uart_host_def.html =================================================================== --- html/uart_host_def.html (revision 134) +++ html/uart_host_def.html (revision 135) @@ -1,240 +1,244 @@ - - - - - start - - - - - - - - - - -
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SOCGEN Datasheet:
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uart_host_def
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NAME
Type
Description

clk
input

reset
input

rxd_data_avail
input

rxd_parity_error
input

rxd_stop_error
input

txd_buffer_empty
input

rxd_data_out[7:0]
input

parity_enable
output

rxd_data_avail_stb
output

rxd_force_parity
output

rxd_parity
output

txd_break
output

txd_force_parity
output

txd_load
output

txd_parity
output

txd_data_in[7:0]
output

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
rxd_data_out_prb
opencores.org
Testbench
io_probe
in
rxd_stop_error_prb
opencores.org
Testbench
io_probe
in
rxd_parity_error_prb
opencores.org
Testbench
io_probe
in
+

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+ + Index: html/uart_model_def.html =================================================================== --- html/uart_model_def.html (revision 134) +++ html/uart_model_def.html (revision 135) @@ -1,240 +1,187 @@ - - - - - start - - - - - - - - - - -
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SOCGEN Datasheet:
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uart_model_def
+
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SourceCode
+
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Parameters
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Parameters
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Name
default
Description
CLKCNT
4'h5

SIZE
4

+

+
+

+
+

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+

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+
Interface
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description

clk
input

reset
input

txd_in
input

rxd_out
output

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
rx_shift_buffer_prb
opencores.org
Testbench
io_probe
def
rx_parity_err_prb
opencores.org
Testbench
io_probe
def
+

+
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+ + Index: html/vga_model_def.html =================================================================== --- html/vga_model_def.html (revision 134) +++ html/vga_model_def.html (revision 135) @@ -1,111 +1,192 @@ - - - - - start - - - - - - - - - - -
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SOCGEN Datasheet:
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vga_model_def
+
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SourceCode
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default
Description
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Type
Description

clk
input

hsync_n
input

reset
input

vsync_n
input

blue[1:0]
input

green[2:0]
input

red[2:0]
input

+

+
+
Children
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
device_rx_data_tpb
opencores.org
Testbench
io_probe
in
device_rx_parity_tpb
opencores.org
Testbench
io_probe
in
+

+
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png/axi_model_master_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/axi_model_slave_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/axi_model_slave_sch.png =================================================================== --- png/axi_model_slave_sch.png (nonexistent) +++ png/axi_model_slave_sch.png (revision 135)

png/axi_model_slave_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/axi_model_slave_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/axi_model_slave_sym.png =================================================================== --- png/axi_model_slave_sym.png (nonexistent) +++ png/axi_model_slave_sym.png (revision 135)

png/axi_model_slave_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/clock_gen_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/clock_gen_def_sch.png =================================================================== --- png/clock_gen_def_sch.png (nonexistent) +++ png/clock_gen_def_sch.png (revision 135)

png/clock_gen_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/clock_gen_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/clock_gen_def_sym.png =================================================================== --- png/clock_gen_def_sym.png (nonexistent) +++ png/clock_gen_def_sym.png (revision 135)

png/clock_gen_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/display_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/display_model_def_sch.png =================================================================== --- png/display_model_def_sch.png (nonexistent) +++ png/display_model_def_sch.png (revision 135)

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png/display_model_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/io_probe_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/io_probe_def_sch.png =================================================================== --- png/io_probe_def_sch.png (nonexistent) +++ png/io_probe_def_sch.png (revision 135)

png/io_probe_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/io_probe_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/io_probe_def_sym.png =================================================================== --- png/io_probe_def_sym.png (nonexistent) +++ png/io_probe_def_sym.png (revision 135)

png/io_probe_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/io_probe_in_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/io_probe_in_sch.png =================================================================== --- png/io_probe_in_sch.png (nonexistent) +++ png/io_probe_in_sch.png (revision 135)

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png/jtag_model_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/jtag_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/jtag_model_def_sym.png =================================================================== --- png/jtag_model_def_sym.png (nonexistent) +++ png/jtag_model_def_sym.png (revision 135)

png/jtag_model_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/micro_bus16_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/micro_bus16_model_def_sch.png =================================================================== --- png/micro_bus16_model_def_sch.png (nonexistent) +++ png/micro_bus16_model_def_sch.png (revision 135)

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png/ps2_host_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/ps2_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/ps2_model_def_sch.png =================================================================== --- png/ps2_model_def_sch.png (nonexistent) +++ png/ps2_model_def_sch.png (revision 135)

png/ps2_model_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/ps2_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/ps2_model_def_sym.png =================================================================== --- png/ps2_model_def_sym.png (nonexistent) +++ png/ps2_model_def_sym.png (revision 135)

png/ps2_model_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/spi_host_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/spi_host_def_sch.png =================================================================== --- png/spi_host_def_sch.png (nonexistent) +++ png/spi_host_def_sch.png (revision 135)

png/spi_host_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/spi_host_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/spi_host_def_sym.png =================================================================== --- png/spi_host_def_sym.png (nonexistent) +++ png/spi_host_def_sym.png (revision 135)

png/spi_host_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/spi_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/spi_model_def_sch.png =================================================================== --- png/spi_model_def_sch.png (nonexistent) +++ png/spi_model_def_sch.png (revision 135)

png/spi_model_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/spi_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/spi_model_def_sym.png =================================================================== --- png/spi_model_def_sym.png (nonexistent) +++ png/spi_model_def_sym.png (revision 135)

png/spi_model_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/spi_model_master_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/spi_model_master_sch.png =================================================================== --- png/spi_model_master_sch.png (nonexistent) +++ png/spi_model_master_sch.png (revision 135)

png/spi_model_master_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/spi_model_master_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/spi_model_master_sym.png =================================================================== --- png/spi_model_master_sym.png (nonexistent) +++ png/spi_model_master_sym.png (revision 135)

png/spi_model_master_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/uart_host_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/uart_host_def_sch.png =================================================================== --- png/uart_host_def_sch.png (nonexistent) +++ png/uart_host_def_sch.png (revision 135)

png/uart_host_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/uart_host_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/uart_host_def_sym.png =================================================================== --- png/uart_host_def_sym.png (nonexistent) +++ png/uart_host_def_sym.png (revision 135)

png/uart_host_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/uart_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/uart_model_def_sch.png =================================================================== --- png/uart_model_def_sch.png (nonexistent) +++ png/uart_model_def_sch.png (revision 135)

png/uart_model_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/uart_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/uart_model_def_sym.png =================================================================== --- png/uart_model_def_sym.png (nonexistent) +++ png/uart_model_def_sym.png (revision 135)

png/uart_model_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/vga_model_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/vga_model_def_sch.png =================================================================== --- png/vga_model_def_sch.png (nonexistent) +++ png/vga_model_def_sch.png (revision 135)

png/vga_model_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/vga_model_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/vga_model_def_sym.png =================================================================== --- png/vga_model_def_sym.png (nonexistent) +++ png/vga_model_def_sym.png (revision 135)

png/vga_model_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sch/axi_model_master.sch =================================================================== --- sch/axi_model_master.sch (nonexistent) +++ sch/axi_model_master.sch (revision 135) @@ -0,0 +1,151 @@ +v 20100214 1 +C 1700 300 1 0 0 in_port_vector.sym +{ +T 1700 300 5 10 1 1 0 6 1 1 +refdes=axi_rid[11:0] +} +C 1700 700 1 0 0 in_port_vector.sym +{ +T 1700 700 5 10 1 1 0 6 1 1 +refdes=axi_rdata[31:0] +} +C 1700 1100 1 0 0 in_port_vector.sym +{ +T 1700 1100 5 10 1 1 0 6 1 1 +refdes=axi_bresp[1:0] +} +C 1700 1500 1 0 0 in_port_vector.sym +{ +T 1700 1500 5 10 1 1 0 6 1 1 +refdes=axi_bid[11:0] +} +C 1700 1900 1 0 0 in_port.sym +{ +T 1700 1900 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1700 2300 1 0 0 in_port.sym +{ +T 1700 2300 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1700 2700 1 0 0 in_port.sym +{ +T 1700 2700 5 10 1 1 0 6 1 1 +refdes=axi_wready +} +C 1700 3100 1 0 0 in_port.sym +{ +T 1700 3100 5 10 1 1 0 6 1 1 +refdes=axi_rvalid +} +C 1700 3500 1 0 0 in_port.sym +{ +T 1700 3500 5 10 1 1 0 6 1 1 +refdes=axi_rlast +} +C 1700 3900 1 0 0 in_port.sym +{ +T 1700 3900 5 10 1 1 0 6 1 1 +refdes=axi_bvalid +} +C 1700 4300 1 0 0 in_port.sym +{ +T 1700 4300 5 10 1 1 0 6 1 1 +refdes=axi_awready +} +C 1700 4700 1 0 0 in_port.sym +{ +T 1700 4700 5 10 1 1 0 6 1 1 +refdes=axi_arready +} +C 4600 300 1 0 0 out_port_vector.sym +{ +T 5600 300 5 10 1 1 0 0 1 1 +refdes=axi_wstrb[3:0] +} +C 4600 700 1 0 0 out_port_vector.sym +{ +T 5600 700 5 10 1 1 0 0 1 1 +refdes=axi_wdata[31:0] +} +C 4600 1100 1 0 0 out_port_vector.sym +{ +T 5600 1100 5 10 1 1 0 0 1 1 +refdes=axi_awsize[2:0] +} +C 4600 1500 1 0 0 out_port_vector.sym +{ +T 5600 1500 5 10 1 1 0 0 1 1 +refdes=axi_awlen[7:0] +} +C 4600 1900 1 0 0 out_port_vector.sym +{ +T 5600 1900 5 10 1 1 0 0 1 1 +refdes=axi_awid[11:0] +} +C 4600 2300 1 0 0 out_port_vector.sym +{ +T 5600 2300 5 10 1 1 0 0 1 1 +refdes=axi_awburst[1:0] +} +C 4600 2700 1 0 0 out_port_vector.sym +{ +T 5600 2700 5 10 1 1 0 0 1 1 +refdes=axi_awaddr[31:0] +} +C 4600 3100 1 0 0 out_port_vector.sym +{ +T 5600 3100 5 10 1 1 0 0 1 1 +refdes=axi_arsize[2:0] +} +C 4600 3500 1 0 0 out_port_vector.sym +{ +T 5600 3500 5 10 1 1 0 0 1 1 +refdes=axi_arlen[7:0] +} +C 4600 3900 1 0 0 out_port_vector.sym +{ +T 5600 3900 5 10 1 1 0 0 1 1 +refdes=axi_arid[11:0] +} +C 4600 4300 1 0 0 out_port_vector.sym +{ +T 5600 4300 5 10 1 1 0 0 1 1 +refdes=axi_arburst[1:0] +} +C 4600 4700 1 0 0 out_port_vector.sym +{ +T 5600 4700 5 10 1 1 0 0 1 1 +refdes=axi_araddr[31:0] +} +C 4600 5100 1 0 0 out_port.sym +{ +T 5600 5100 5 10 1 1 0 0 1 1 +refdes=axi_wvalid +} +C 4600 5500 1 0 0 out_port.sym +{ +T 5600 5500 5 10 1 1 0 0 1 1 +refdes=axi_wlast +} +C 4600 5900 1 0 0 out_port.sym +{ +T 5600 5900 5 10 1 1 0 0 1 1 +refdes=axi_rready +} +C 4600 6300 1 0 0 out_port.sym +{ +T 5600 6300 5 10 1 1 0 0 1 1 +refdes=axi_bready +} +C 4600 6700 1 0 0 out_port.sym +{ +T 5600 6700 5 10 1 1 0 0 1 1 +refdes=axi_awvalid +} +C 4600 7100 1 0 0 out_port.sym +{ +T 5600 7100 5 10 1 1 0 0 1 1 +refdes=axi_arvalid +} Index: sch/axi_model_slave.sch =================================================================== --- sch/axi_model_slave.sch (nonexistent) +++ sch/axi_model_slave.sch (revision 135) @@ -0,0 +1,151 @@ +v 20100214 1 +C 1800 300 1 0 0 in_port_vector.sym +{ +T 1800 300 5 10 1 1 0 6 1 1 +refdes=axi_wstrb[3:0] +} +C 1800 700 1 0 0 in_port_vector.sym +{ +T 1800 700 5 10 1 1 0 6 1 1 +refdes=axi_wdata[31:0] +} +C 1800 1100 1 0 0 in_port_vector.sym +{ +T 1800 1100 5 10 1 1 0 6 1 1 +refdes=axi_awsize[2:0] +} +C 1800 1500 1 0 0 in_port_vector.sym +{ +T 1800 1500 5 10 1 1 0 6 1 1 +refdes=axi_awlen[7:0] +} +C 1800 1900 1 0 0 in_port_vector.sym +{ +T 1800 1900 5 10 1 1 0 6 1 1 +refdes=axi_awid[11:0] +} +C 1800 2300 1 0 0 in_port_vector.sym +{ +T 1800 2300 5 10 1 1 0 6 1 1 +refdes=axi_awburst[1:0] +} +C 1800 2700 1 0 0 in_port_vector.sym +{ +T 1800 2700 5 10 1 1 0 6 1 1 +refdes=axi_awaddr[31:0] +} +C 1800 3100 1 0 0 in_port_vector.sym +{ +T 1800 3100 5 10 1 1 0 6 1 1 +refdes=axi_arsize[2:0] +} +C 1800 3500 1 0 0 in_port_vector.sym +{ +T 1800 3500 5 10 1 1 0 6 1 1 +refdes=axi_arlen[7:0] +} +C 1800 3900 1 0 0 in_port_vector.sym +{ +T 1800 3900 5 10 1 1 0 6 1 1 +refdes=axi_arid[11:0] +} +C 1800 4300 1 0 0 in_port_vector.sym +{ +T 1800 4300 5 10 1 1 0 6 1 1 +refdes=axi_arburst[1:0] +} +C 1800 4700 1 0 0 in_port_vector.sym +{ +T 1800 4700 5 10 1 1 0 6 1 1 +refdes=axi_araddr[31:0] +} +C 1800 5100 1 0 0 in_port.sym +{ +T 1800 5100 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1800 5500 1 0 0 in_port.sym +{ +T 1800 5500 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1800 5900 1 0 0 in_port.sym +{ +T 1800 5900 5 10 1 1 0 6 1 1 +refdes=axi_wvalid +} +C 1800 6300 1 0 0 in_port.sym +{ +T 1800 6300 5 10 1 1 0 6 1 1 +refdes=axi_wlast +} +C 1800 6700 1 0 0 in_port.sym +{ +T 1800 6700 5 10 1 1 0 6 1 1 +refdes=axi_rready +} +C 1800 7100 1 0 0 in_port.sym +{ +T 1800 7100 5 10 1 1 0 6 1 1 +refdes=axi_bready +} +C 1800 7500 1 0 0 in_port.sym +{ +T 1800 7500 5 10 1 1 0 6 1 1 +refdes=axi_awvalid +} +C 1800 7900 1 0 0 in_port.sym +{ +T 1800 7900 5 10 1 1 0 6 1 1 +refdes=axi_arvalid +} +C 4600 300 1 0 0 out_port_vector.sym +{ +T 5600 300 5 10 1 1 0 0 1 1 +refdes=axi_rid[11:0] +} +C 4600 700 1 0 0 out_port_vector.sym +{ +T 5600 700 5 10 1 1 0 0 1 1 +refdes=axi_rdata[31:0] +} +C 4600 1100 1 0 0 out_port_vector.sym +{ +T 5600 1100 5 10 1 1 0 0 1 1 +refdes=axi_bresp[1:0] +} +C 4600 1500 1 0 0 out_port_vector.sym +{ +T 5600 1500 5 10 1 1 0 0 1 1 +refdes=axi_bid[11:0] +} +C 4600 1900 1 0 0 out_port.sym +{ +T 5600 1900 5 10 1 1 0 0 1 1 +refdes=axi_wready +} +C 4600 2300 1 0 0 out_port.sym +{ +T 5600 2300 5 10 1 1 0 0 1 1 +refdes=axi_rvalid +} +C 4600 2700 1 0 0 out_port.sym +{ +T 5600 2700 5 10 1 1 0 0 1 1 +refdes=axi_rlast +} +C 4600 3100 1 0 0 out_port.sym +{ +T 5600 3100 5 10 1 1 0 0 1 1 +refdes=axi_bvalid +} +C 4600 3500 1 0 0 out_port.sym +{ +T 5600 3500 5 10 1 1 0 0 1 1 +refdes=axi_awready +} +C 4600 3900 1 0 0 out_port.sym +{ +T 5600 3900 5 10 1 1 0 0 1 1 +refdes=axi_arready +} Index: sch/clock_gen_def.sch =================================================================== --- sch/clock_gen_def.sch (nonexistent) +++ sch/clock_gen_def.sch (revision 135) @@ -0,0 +1,36 @@ +v 20100214 1 +C 2200 300 1 0 0 in_port_vector.sym +{ +T 2200 300 5 10 1 1 0 6 1 1 +refdes=STOP[STOP_WIDTH-1:0] +} +C 2200 700 1 0 0 in_port_vector.sym +{ +T 2200 700 5 10 1 1 0 6 1 1 +refdes=BAD[BAD_WIDTH-1:0] +} +C 2200 1100 1 0 0 in_port.sym +{ +T 2200 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 2200 1500 1 0 0 in_port.sym +{ +T 2200 1500 5 10 1 1 0 6 1 1 +refdes=START +} +C 4100 300 1 0 0 out_port.sym +{ +T 5100 300 5 10 1 1 0 0 1 1 +refdes=reset +} +C 4100 700 1 0 0 out_port.sym +{ +T 5100 700 5 10 1 1 0 0 1 1 +refdes=FINISH +} +C 4100 1100 1 0 0 out_port.sym +{ +T 5100 1100 5 10 1 1 0 0 1 1 +refdes=FAIL +} Index: sch/display_model_def.sch =================================================================== --- sch/display_model_def.sch (nonexistent) +++ sch/display_model_def.sch (revision 135) @@ -0,0 +1,26 @@ +v 20100214 1 +C 1000 300 1 0 0 in_port_vector.sym +{ +T 1000 300 5 10 1 1 0 6 1 1 +refdes=seg[6:0] +} +C 1000 700 1 0 0 in_port_vector.sym +{ +T 1000 700 5 10 1 1 0 6 1 1 +refdes=an[3:0] +} +C 1000 1100 1 0 0 in_port.sym +{ +T 1000 1100 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1000 1500 1 0 0 in_port.sym +{ +T 1000 1500 5 10 1 1 0 6 1 1 +refdes=dp +} +C 1000 1900 1 0 0 in_port.sym +{ +T 1000 1900 5 10 1 1 0 6 1 1 +refdes=clk +} Index: sch/io_host_model_def.sch =================================================================== --- sch/io_host_model_def.sch (nonexistent) +++ sch/io_host_model_def.sch (revision 135) @@ -0,0 +1,56 @@ +v 20100214 1 +C 2400 300 1 0 0 in_port_vector.sym +{ +T 2400 300 5 10 1 1 0 6 1 1 +refdes=io_host_out_bits[15:0] +} +C 2400 700 1 0 0 in_port.sym +{ +T 2400 700 5 10 1 1 0 6 1 1 +refdes=reset +} +C 2400 1100 1 0 0 in_port.sym +{ +T 2400 1100 5 10 1 1 0 6 1 1 +refdes=io_host_out_valid +} +C 2400 1500 1 0 0 in_port.sym +{ +T 2400 1500 5 10 1 1 0 6 1 1 +refdes=io_host_in_ready +} +C 2400 1900 1 0 0 in_port.sym +{ +T 2400 1900 5 10 1 1 0 6 1 1 +refdes=clk +} +C 6000 300 1 0 0 out_port_vector.sym +{ +T 7000 300 5 10 1 1 0 0 1 1 +refdes=io_host_in_bits[15:0] +} +C 6000 700 1 0 0 out_port.sym +{ +T 7000 700 5 10 1 1 0 0 1 1 +refdes=io_host_out_ready +} +C 6000 1100 1 0 0 out_port.sym +{ +T 7000 1100 5 10 1 1 0 0 1 1 +refdes=io_host_in_valid +} +C 6000 1500 1 0 0 out_port.sym +{ +T 7000 1500 5 10 1 1 0 0 1 1 +refdes=io_host_debug_stats_pcr +} +C 6000 1900 1 0 0 out_port.sym +{ +T 7000 1900 5 10 1 1 0 0 1 1 +refdes=io_host_clk_edge +} +C 6000 2300 1 0 0 out_port.sym +{ +T 7000 2300 5 10 1 1 0 0 1 1 +refdes=io_host_clk +} Index: sch/io_mem_model_def.sch =================================================================== --- sch/io_mem_model_def.sch (nonexistent) +++ sch/io_mem_model_def.sch (revision 135) @@ -0,0 +1,96 @@ +v 20100214 1 +C 3400 300 1 0 0 in_port_vector.sym +{ +T 3400 300 5 10 1 1 0 6 1 1 +refdes=io_mem_req_data_bits_data[127:0] +} +C 3400 700 1 0 0 in_port_vector.sym +{ +T 3400 700 5 10 1 1 0 6 1 1 +refdes=io_mem_req_cmd_bits_tag[4:0] +} +C 3400 1100 1 0 0 in_port_vector.sym +{ +T 3400 1100 5 10 1 1 0 6 1 1 +refdes=io_mem_req_cmd_bits_addr[25:0] +} +C 3400 1500 1 0 0 in_port.sym +{ +T 3400 1500 5 10 1 1 0 6 1 1 +refdes=reset +} +C 3400 1900 1 0 0 in_port.sym +{ +T 3400 1900 5 10 1 1 0 6 1 1 +refdes=io_mem_req_data_valid +} +C 3400 2300 1 0 0 in_port.sym +{ +T 3400 2300 5 10 1 1 0 6 1 1 +refdes=io_mem_req_cmd_valid +} +C 3400 2700 1 0 0 in_port.sym +{ +T 3400 2700 5 10 1 1 0 6 1 1 +refdes=io_mem_req_cmd_bits_rw +} +C 3400 3100 1 0 0 in_port.sym +{ +T 3400 3100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 7500 300 1 0 0 out_port_vector.sym +{ +T 8500 300 5 10 1 1 0 0 1 1 +refdes=io_mem_resp_bits_tag[4:0] +} +C 7500 700 1 0 0 out_port_vector.sym +{ +T 8500 700 5 10 1 1 0 0 1 1 +refdes=io_mem_resp_bits_data[127:0] +} +C 7500 1100 1 0 0 out_port.sym +{ +T 8500 1100 5 10 1 1 0 0 1 1 +refdes=io_out_mem_valid +} +C 7500 1500 1 0 0 out_port.sym +{ +T 8500 1500 5 10 1 1 0 0 1 1 +refdes=io_out_mem_ready +} +C 7500 1900 1 0 0 out_port.sym +{ +T 8500 1900 5 10 1 1 0 0 1 1 +refdes=io_mem_resp_valid +} +C 7500 2300 1 0 0 out_port.sym +{ +T 8500 2300 5 10 1 1 0 0 1 1 +refdes=io_mem_resp_ready +} +C 7500 2700 1 0 0 out_port.sym +{ +T 8500 2700 5 10 1 1 0 0 1 1 +refdes=io_mem_req_data_ready +} +C 7500 3100 1 0 0 out_port.sym +{ +T 8500 3100 5 10 1 1 0 0 1 1 +refdes=io_mem_req_cmd_ready +} +C 7500 3500 1 0 0 out_port.sym +{ +T 8500 3500 5 10 1 1 0 0 1 1 +refdes=io_mem_backup_en +} +C 7500 3900 1 0 0 out_port.sym +{ +T 8500 3900 5 10 1 1 0 0 1 1 +refdes=io_in_mem_valid +} +C 7500 4300 1 0 0 out_port.sym +{ +T 8500 4300 5 10 1 1 0 0 1 1 +refdes=io_in_mem_ready +} Index: sch/io_probe_def.sch =================================================================== --- sch/io_probe_def.sch (nonexistent) +++ sch/io_probe_def.sch (revision 135) @@ -0,0 +1,26 @@ +v 20100214 1 +C 2700 300 1 0 0 in_port_vector.sym +{ +T 2700 300 5 10 1 1 0 6 1 1 +refdes=mask[WIDTH-1:0] +} +C 2700 700 1 0 0 in_port_vector.sym +{ +T 2700 700 5 10 1 1 0 6 1 1 +refdes=expected_value[WIDTH-1:0] +} +C 2700 1100 1 0 0 in_port_vector.sym +{ +T 2700 1100 5 10 1 1 0 6 1 1 +refdes=drive_value[WIDTH-1:0] +} +C 2700 1500 1 0 0 in_port.sym +{ +T 2700 1500 5 10 1 1 0 6 1 1 +refdes=clk +} +C 5700 300 1 0 0 io_port_vector.sym +{ +T 6700 300 5 10 1 1 0 0 1 1 +refdes=signal[WIDTH-1:0] +} Index: sch/io_probe_in.sch =================================================================== --- sch/io_probe_in.sch (nonexistent) +++ sch/io_probe_in.sch (revision 135) @@ -0,0 +1,21 @@ +v 20100214 1 +C 2700 300 1 0 0 in_port_vector.sym +{ +T 2700 300 5 10 1 1 0 6 1 1 +refdes=signal[WIDTH-1:0] +} +C 2700 700 1 0 0 in_port_vector.sym +{ +T 2700 700 5 10 1 1 0 6 1 1 +refdes=mask[WIDTH-1:0] +} +C 2700 1100 1 0 0 in_port_vector.sym +{ +T 2700 1100 5 10 1 1 0 6 1 1 +refdes=expected_value[WIDTH-1:0] +} +C 2700 1500 1 0 0 in_port.sym +{ +T 2700 1500 5 10 1 1 0 6 1 1 +refdes=clk +} Index: sch/jtag_model_def.sch =================================================================== --- sch/jtag_model_def.sch (nonexistent) +++ sch/jtag_model_def.sch (revision 135) @@ -0,0 +1,36 @@ +v 20100214 1 +C 700 300 1 0 0 in_port.sym +{ +T 700 300 5 10 1 1 0 6 1 1 +refdes=tdi +} +C 700 700 1 0 0 in_port.sym +{ +T 700 700 5 10 1 1 0 6 1 1 +refdes=reset +} +C 700 1100 1 0 0 in_port.sym +{ +T 700 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 2600 300 1 0 0 out_port.sym +{ +T 3600 300 5 10 1 1 0 0 1 1 +refdes=trst_n +} +C 2600 700 1 0 0 out_port.sym +{ +T 3600 700 5 10 1 1 0 0 1 1 +refdes=tms +} +C 2600 1100 1 0 0 out_port.sym +{ +T 3600 1100 5 10 1 1 0 0 1 1 +refdes=tdo +} +C 2600 1500 1 0 0 out_port.sym +{ +T 3600 1500 5 10 1 1 0 0 1 1 +refdes=tclk +} Index: sch/micro_bus16_model_def.sch =================================================================== --- sch/micro_bus16_model_def.sch (nonexistent) +++ sch/micro_bus16_model_def.sch (revision 135) @@ -0,0 +1,51 @@ +v 20100214 1 +C 1300 300 1 0 0 in_port_vector.sym +{ +T 1300 300 5 10 1 1 0 6 1 1 +refdes=rdata[15:0] +} +C 1300 700 1 0 0 in_port.sym +{ +T 1300 700 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1300 1100 1 0 0 in_port.sym +{ +T 1300 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 3700 300 1 0 0 out_port_vector.sym +{ +T 4700 300 5 10 1 1 0 0 1 1 +refdes=wdata[15:0] +} +C 3700 700 1 0 0 out_port_vector.sym +{ +T 4700 700 5 10 1 1 0 0 1 1 +refdes=cs[1:0] +} +C 3700 1100 1 0 0 out_port_vector.sym +{ +T 4700 1100 5 10 1 1 0 0 1 1 +refdes=addr[23:0] +} +C 3700 1500 1 0 0 out_port.sym +{ +T 4700 1500 5 10 1 1 0 0 1 1 +refdes=wr +} +C 3700 1900 1 0 0 out_port.sym +{ +T 4700 1900 5 10 1 1 0 0 1 1 +refdes=ub +} +C 3700 2300 1 0 0 out_port.sym +{ +T 4700 2300 5 10 1 1 0 0 1 1 +refdes=rd +} +C 3700 2700 1 0 0 out_port.sym +{ +T 4700 2700 5 10 1 1 0 0 1 1 +refdes=lb +} Index: sch/micro_bus_model_def.sch =================================================================== --- sch/micro_bus_model_def.sch (nonexistent) +++ sch/micro_bus_model_def.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 700 300 1 0 0 in_port.sym +{ +T 700 300 5 10 1 1 0 6 1 1 +refdes=reset +} +C 700 700 1 0 0 in_port.sym +{ +T 700 700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 4000 300 1 0 0 out_port_vector.sym +{ +T 5000 300 5 10 1 1 0 0 1 1 +refdes=wdata[7:0] +} +C 4000 700 1 0 0 out_port_vector.sym +{ +T 5000 700 5 10 1 1 0 0 1 1 +refdes=addr[addr_width-1:0] +} +C 4000 1100 1 0 0 out_port.sym +{ +T 5000 1100 5 10 1 1 0 0 1 1 +refdes=wr +} +C 4000 1500 1 0 0 out_port.sym +{ +T 5000 1500 5 10 1 1 0 0 1 1 +refdes=rd +} +C 4000 1900 1 0 0 out_port.sym +{ +T 5000 1900 5 10 1 1 0 0 1 1 +refdes=cs +} +C 4000 2300 1 0 0 io_port_vector.sym +{ +T 5000 2300 5 10 1 1 0 0 1 1 +refdes=rdata[7:0] +} Index: sch/mt45w8mw12_def.sch =================================================================== --- sch/mt45w8mw12_def.sch (nonexistent) +++ sch/mt45w8mw12_def.sch (revision 135) @@ -0,0 +1,56 @@ +v 20100214 1 +C 2100 300 1 0 0 in_port_vector.sym +{ +T 2100 300 5 10 1 1 0 6 1 1 +refdes=addr[ADDR_BITS-1:0] +} +C 2100 700 1 0 0 in_port.sym +{ +T 2100 700 5 10 1 1 0 6 1 1 +refdes=we_n +} +C 2100 1100 1 0 0 in_port.sym +{ +T 2100 1100 5 10 1 1 0 6 1 1 +refdes=ub_n +} +C 2100 1500 1 0 0 in_port.sym +{ +T 2100 1500 5 10 1 1 0 6 1 1 +refdes=oe_n +} +C 2100 1900 1 0 0 in_port.sym +{ +T 2100 1900 5 10 1 1 0 6 1 1 +refdes=lb_n +} +C 2100 2300 1 0 0 in_port.sym +{ +T 2100 2300 5 10 1 1 0 6 1 1 +refdes=cre +} +C 2100 2700 1 0 0 in_port.sym +{ +T 2100 2700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 2100 3100 1 0 0 in_port.sym +{ +T 2100 3100 5 10 1 1 0 6 1 1 +refdes=ce_n +} +C 2100 3500 1 0 0 in_port.sym +{ +T 2100 3500 5 10 1 1 0 6 1 1 +refdes=adv_n +} +C 4900 300 1 0 0 out_port.sym +{ +T 5900 300 5 10 1 1 0 0 1 1 +refdes=o_wait +} +C 4900 700 1 0 0 io_port_vector.sym +{ +T 5900 700 5 10 1 1 0 0 1 1 +refdes=dq[DQ_BITS-1:0] +} Index: sch/ps2_host_def.sch =================================================================== --- sch/ps2_host_def.sch (nonexistent) +++ sch/ps2_host_def.sch (revision 135) @@ -0,0 +1,71 @@ +v 20100214 1 +C 1700 300 1 0 0 in_port_vector.sym +{ +T 1700 300 5 10 1 1 0 6 1 1 +refdes=rx_data[7:0] +} +C 1700 700 1 0 0 in_port.sym +{ +T 1700 700 5 10 1 1 0 6 1 1 +refdes=tx_ack_error +} +C 1700 1100 1 0 0 in_port.sym +{ +T 1700 1100 5 10 1 1 0 6 1 1 +refdes=rx_read +} +C 1700 1500 1 0 0 in_port.sym +{ +T 1700 1500 5 10 1 1 0 6 1 1 +refdes=rx_parity_rcv +} +C 1700 1900 1 0 0 in_port.sym +{ +T 1700 1900 5 10 1 1 0 6 1 1 +refdes=rx_parity_error +} +C 1700 2300 1 0 0 in_port.sym +{ +T 1700 2300 5 10 1 1 0 6 1 1 +refdes=rx_parity_cal +} +C 1700 2700 1 0 0 in_port.sym +{ +T 1700 2700 5 10 1 1 0 6 1 1 +refdes=rx_full +} +C 1700 3100 1 0 0 in_port.sym +{ +T 1700 3100 5 10 1 1 0 6 1 1 +refdes=rx_frame_error +} +C 1700 3500 1 0 0 in_port.sym +{ +T 1700 3500 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1700 3900 1 0 0 in_port.sym +{ +T 1700 3900 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1700 4300 1 0 0 in_port.sym +{ +T 1700 4300 5 10 1 1 0 6 1 1 +refdes=busy +} +C 4200 300 1 0 0 out_port_vector.sym +{ +T 5200 300 5 10 1 1 0 0 1 1 +refdes=tx_data[7:0] +} +C 4200 700 1 0 0 out_port.sym +{ +T 5200 700 5 10 1 1 0 0 1 1 +refdes=tx_write +} +C 4200 1100 1 0 0 out_port.sym +{ +T 5200 1100 5 10 1 1 0 0 1 1 +refdes=rx_clr +} Index: sch/ps2_model_def.sch =================================================================== --- sch/ps2_model_def.sch (nonexistent) +++ sch/ps2_model_def.sch (revision 135) @@ -0,0 +1,21 @@ +v 20100214 1 +C 700 300 1 0 0 in_port.sym +{ +T 700 300 5 10 1 1 0 6 1 1 +refdes=reset +} +C 700 700 1 0 0 in_port.sym +{ +T 700 700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 2800 300 1 0 0 io_port.sym +{ +T 3800 300 5 10 1 1 0 0 1 1 +refdes=ps2_data +} +C 2800 700 1 0 0 io_port.sym +{ +T 3800 700 5 10 1 1 0 0 1 1 +refdes=ps2_clk +} Index: sch/spi_host_def.sch =================================================================== --- sch/spi_host_def.sch (nonexistent) +++ sch/spi_host_def.sch (revision 135) @@ -0,0 +1,71 @@ +v 20100214 1 +C 1700 300 1 0 0 in_port_vector.sym +{ +T 1700 300 5 10 1 1 0 6 1 1 +refdes=rx_data[7:0] +} +C 1700 700 1 0 0 in_port.sym +{ +T 1700 700 5 10 1 1 0 6 1 1 +refdes=tx_ack_error +} +C 1700 1100 1 0 0 in_port.sym +{ +T 1700 1100 5 10 1 1 0 6 1 1 +refdes=rx_read +} +C 1700 1500 1 0 0 in_port.sym +{ +T 1700 1500 5 10 1 1 0 6 1 1 +refdes=rx_parity_rcv +} +C 1700 1900 1 0 0 in_port.sym +{ +T 1700 1900 5 10 1 1 0 6 1 1 +refdes=rx_parity_error +} +C 1700 2300 1 0 0 in_port.sym +{ +T 1700 2300 5 10 1 1 0 6 1 1 +refdes=rx_parity_cal +} +C 1700 2700 1 0 0 in_port.sym +{ +T 1700 2700 5 10 1 1 0 6 1 1 +refdes=rx_full +} +C 1700 3100 1 0 0 in_port.sym +{ +T 1700 3100 5 10 1 1 0 6 1 1 +refdes=rx_frame_error +} +C 1700 3500 1 0 0 in_port.sym +{ +T 1700 3500 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1700 3900 1 0 0 in_port.sym +{ +T 1700 3900 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1700 4300 1 0 0 in_port.sym +{ +T 1700 4300 5 10 1 1 0 6 1 1 +refdes=busy +} +C 4200 300 1 0 0 out_port_vector.sym +{ +T 5200 300 5 10 1 1 0 0 1 1 +refdes=tx_data[7:0] +} +C 4200 700 1 0 0 out_port.sym +{ +T 5200 700 5 10 1 1 0 0 1 1 +refdes=tx_write +} +C 4200 1100 1 0 0 out_port.sym +{ +T 5200 1100 5 10 1 1 0 0 1 1 +refdes=rx_clr +} Index: sch/spi_model_def.sch =================================================================== --- sch/spi_model_def.sch (nonexistent) +++ sch/spi_model_def.sch (revision 135) @@ -0,0 +1,21 @@ +v 20100214 1 +C 700 300 1 0 0 in_port.sym +{ +T 700 300 5 10 1 1 0 6 1 1 +refdes=reset +} +C 700 700 1 0 0 in_port.sym +{ +T 700 700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 2800 300 1 0 0 io_port.sym +{ +T 3800 300 5 10 1 1 0 0 1 1 +refdes=spi_data +} +C 2800 700 1 0 0 io_port.sym +{ +T 3800 700 5 10 1 1 0 0 1 1 +refdes=spi_clk +} Index: sch/spi_model_master.sch =================================================================== --- sch/spi_model_master.sch (nonexistent) +++ sch/spi_model_master.sch (revision 135) @@ -0,0 +1,31 @@ +v 20100214 1 +C 1000 300 1 0 0 in_port.sym +{ +T 1000 300 5 10 1 1 0 6 1 1 +refdes=spi_miso +} +C 1000 700 1 0 0 in_port.sym +{ +T 1000 700 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1000 1100 1 0 0 in_port.sym +{ +T 1000 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 3200 300 1 0 0 out_port.sym +{ +T 4200 300 5 10 1 1 0 0 1 1 +refdes=spi_sel_n +} +C 3200 700 1 0 0 out_port.sym +{ +T 4200 700 5 10 1 1 0 0 1 1 +refdes=spi_mosi +} +C 3200 1100 1 0 0 out_port.sym +{ +T 4200 1100 5 10 1 1 0 0 1 1 +refdes=spi_clk +} Index: sch/uart_host_def.sch =================================================================== --- sch/uart_host_def.sch (nonexistent) +++ sch/uart_host_def.sch (revision 135) @@ -0,0 +1,81 @@ +v 20100214 1 +C 1900 300 1 0 0 in_port_vector.sym +{ +T 1900 300 5 10 1 1 0 6 1 1 +refdes=rxd_data_out[7:0] +} +C 1900 700 1 0 0 in_port.sym +{ +T 1900 700 5 10 1 1 0 6 1 1 +refdes=txd_buffer_empty +} +C 1900 1100 1 0 0 in_port.sym +{ +T 1900 1100 5 10 1 1 0 6 1 1 +refdes=rxd_stop_error +} +C 1900 1500 1 0 0 in_port.sym +{ +T 1900 1500 5 10 1 1 0 6 1 1 +refdes=rxd_parity_error +} +C 1900 1900 1 0 0 in_port.sym +{ +T 1900 1900 5 10 1 1 0 6 1 1 +refdes=rxd_data_avail +} +C 1900 2300 1 0 0 in_port.sym +{ +T 1900 2300 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1900 2700 1 0 0 in_port.sym +{ +T 1900 2700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 5000 300 1 0 0 out_port_vector.sym +{ +T 6000 300 5 10 1 1 0 0 1 1 +refdes=txd_data_in[7:0] +} +C 5000 700 1 0 0 out_port.sym +{ +T 6000 700 5 10 1 1 0 0 1 1 +refdes=txd_parity +} +C 5000 1100 1 0 0 out_port.sym +{ +T 6000 1100 5 10 1 1 0 0 1 1 +refdes=txd_load +} +C 5000 1500 1 0 0 out_port.sym +{ +T 6000 1500 5 10 1 1 0 0 1 1 +refdes=txd_force_parity +} +C 5000 1900 1 0 0 out_port.sym +{ +T 6000 1900 5 10 1 1 0 0 1 1 +refdes=txd_break +} +C 5000 2300 1 0 0 out_port.sym +{ +T 6000 2300 5 10 1 1 0 0 1 1 +refdes=rxd_parity +} +C 5000 2700 1 0 0 out_port.sym +{ +T 6000 2700 5 10 1 1 0 0 1 1 +refdes=rxd_force_parity +} +C 5000 3100 1 0 0 out_port.sym +{ +T 6000 3100 5 10 1 1 0 0 1 1 +refdes=rxd_data_avail_stb +} +C 5000 3500 1 0 0 out_port.sym +{ +T 6000 3500 5 10 1 1 0 0 1 1 +refdes=parity_enable +} Index: sch/uart_model_def.sch =================================================================== --- sch/uart_model_def.sch (nonexistent) +++ sch/uart_model_def.sch (revision 135) @@ -0,0 +1,21 @@ +v 20100214 1 +C 800 300 1 0 0 in_port.sym +{ +T 800 300 5 10 1 1 0 6 1 1 +refdes=txd_in +} +C 800 700 1 0 0 in_port.sym +{ +T 800 700 5 10 1 1 0 6 1 1 +refdes=reset +} +C 800 1100 1 0 0 in_port.sym +{ +T 800 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 2800 300 1 0 0 out_port.sym +{ +T 3800 300 5 10 1 1 0 0 1 1 +refdes=rxd_out +} Index: sch/vga_model_def.sch =================================================================== --- sch/vga_model_def.sch (nonexistent) +++ sch/vga_model_def.sch (revision 135) @@ -0,0 +1,36 @@ +v 20100214 1 +C 1200 300 1 0 0 in_port_vector.sym +{ +T 1200 300 5 10 1 1 0 6 1 1 +refdes=red[2:0] +} +C 1200 700 1 0 0 in_port_vector.sym +{ +T 1200 700 5 10 1 1 0 6 1 1 +refdes=green[2:0] +} +C 1200 1100 1 0 0 in_port_vector.sym +{ +T 1200 1100 5 10 1 1 0 6 1 1 +refdes=blue[1:0] +} +C 1200 1500 1 0 0 in_port.sym +{ +T 1200 1500 5 10 1 1 0 6 1 1 +refdes=vsync_n +} +C 1200 1900 1 0 0 in_port.sym +{ +T 1200 1900 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1200 2300 1 0 0 in_port.sym +{ +T 1200 2300 5 10 1 1 0 6 1 1 +refdes=hsync_n +} +C 1200 2700 1 0 0 in_port.sym +{ +T 1200 2700 5 10 1 1 0 6 1 1 +refdes=clk +} Index: sym/axi_model_master.sym =================================================================== --- sym/axi_model_master.sym (nonexistent) +++ sym/axi_model_master.sym (revision 135) @@ -0,0 +1,224 @@ +v 20100214 1 +B 300 0 3500 3900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 4050 5 10 1 1 0 0 1 1 +device=axi_model_master +T 400 4250 5 10 1 1 0 0 1 1 +refdes=U? +T 400 4400 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 4400 0 10 0 1 0 0 1 1 +library=Testbench +T 400 4400 0 10 0 1 0 0 1 1 +component=axi_model +T 400 4400 0 10 0 1 0 0 1 1 +version=master +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=axi_rid[11:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=axi_rdata[31:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=axi_bresp[1:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 10 1 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=axi_bid[11:0] +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=axi_wready +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 300 1600 0 1600 4 0 1 +{ +T 400 1600 5 10 1 1 0 1 1 1 +pinnumber=axi_rvalid +T 400 1600 5 10 0 1 0 1 1 1 +pinseq=8 +} +P 300 1800 0 1800 4 0 1 +{ +T 400 1800 5 10 1 1 0 1 1 1 +pinnumber=axi_rlast +T 400 1800 5 10 0 1 0 1 1 1 +pinseq=9 +} +P 300 2000 0 2000 4 0 1 +{ +T 400 2000 5 10 1 1 0 1 1 1 +pinnumber=axi_bvalid +T 400 2000 5 10 0 1 0 1 1 1 +pinseq=10 +} +P 300 2200 0 2200 4 0 1 +{ +T 400 2200 5 10 1 1 0 1 1 1 +pinnumber=axi_awready +T 400 2200 5 10 0 1 0 1 1 1 +pinseq=11 +} +P 300 2400 0 2400 4 0 1 +{ +T 400 2400 5 10 1 1 0 1 1 1 +pinnumber=axi_arready +T 400 2400 5 10 0 1 0 1 1 1 +pinseq=12 +} +P 3800 200 4100 200 10 1 1 +{ +T 3700 200 5 10 1 1 0 7 1 1 +pinnumber=axi_wstrb[3:0] +T 3700 200 5 10 0 1 0 7 1 1 +pinseq=13 +} +P 3800 400 4100 400 10 1 1 +{ +T 3700 400 5 10 1 1 0 7 1 1 +pinnumber=axi_wdata[31:0] +T 3700 400 5 10 0 1 0 7 1 1 +pinseq=14 +} +P 3800 600 4100 600 10 1 1 +{ +T 3700 600 5 10 1 1 0 7 1 1 +pinnumber=axi_awsize[2:0] +T 3700 600 5 10 0 1 0 7 1 1 +pinseq=15 +} +P 3800 800 4100 800 10 1 1 +{ +T 3700 800 5 10 1 1 0 7 1 1 +pinnumber=axi_awlen[7:0] +T 3700 800 5 10 0 1 0 7 1 1 +pinseq=16 +} +P 3800 1000 4100 1000 10 1 1 +{ +T 3700 1000 5 10 1 1 0 7 1 1 +pinnumber=axi_awid[11:0] +T 3700 1000 5 10 0 1 0 7 1 1 +pinseq=17 +} +P 3800 1200 4100 1200 10 1 1 +{ +T 3700 1200 5 10 1 1 0 7 1 1 +pinnumber=axi_awburst[1:0] +T 3700 1200 5 10 0 1 0 7 1 1 +pinseq=18 +} +P 3800 1400 4100 1400 10 1 1 +{ +T 3700 1400 5 10 1 1 0 7 1 1 +pinnumber=axi_awaddr[31:0] +T 3700 1400 5 10 0 1 0 7 1 1 +pinseq=19 +} +P 3800 1600 4100 1600 10 1 1 +{ +T 3700 1600 5 10 1 1 0 7 1 1 +pinnumber=axi_arsize[2:0] +T 3700 1600 5 10 0 1 0 7 1 1 +pinseq=20 +} +P 3800 1800 4100 1800 10 1 1 +{ +T 3700 1800 5 10 1 1 0 7 1 1 +pinnumber=axi_arlen[7:0] +T 3700 1800 5 10 0 1 0 7 1 1 +pinseq=21 +} +P 3800 2000 4100 2000 10 1 1 +{ +T 3700 2000 5 10 1 1 0 7 1 1 +pinnumber=axi_arid[11:0] +T 3700 2000 5 10 0 1 0 7 1 1 +pinseq=22 +} +P 3800 2200 4100 2200 10 1 1 +{ +T 3700 2200 5 10 1 1 0 7 1 1 +pinnumber=axi_arburst[1:0] +T 3700 2200 5 10 0 1 0 7 1 1 +pinseq=23 +} +P 3800 2400 4100 2400 10 1 1 +{ +T 3700 2400 5 10 1 1 0 7 1 1 +pinnumber=axi_araddr[31:0] +T 3700 2400 5 10 0 1 0 7 1 1 +pinseq=24 +} +P 3800 2600 4100 2600 4 0 1 +{ +T 3700 2600 5 10 1 1 0 7 1 1 +pinnumber=axi_wvalid +T 3800 2600 5 10 0 1 0 7 1 1 +pinseq=25 +} +P 3800 2800 4100 2800 4 0 1 +{ +T 3700 2800 5 10 1 1 0 7 1 1 +pinnumber=axi_wlast +T 3800 2800 5 10 0 1 0 7 1 1 +pinseq=26 +} +P 3800 3000 4100 3000 4 0 1 +{ +T 3700 3000 5 10 1 1 0 7 1 1 +pinnumber=axi_rready +T 3800 3000 5 10 0 1 0 7 1 1 +pinseq=27 +} +P 3800 3200 4100 3200 4 0 1 +{ +T 3700 3200 5 10 1 1 0 7 1 1 +pinnumber=axi_bready +T 3800 3200 5 10 0 1 0 7 1 1 +pinseq=28 +} +P 3800 3400 4100 3400 4 0 1 +{ +T 3700 3400 5 10 1 1 0 7 1 1 +pinnumber=axi_awvalid +T 3800 3400 5 10 0 1 0 7 1 1 +pinseq=29 +} +P 3800 3600 4100 3600 4 0 1 +{ +T 3700 3600 5 10 1 1 0 7 1 1 +pinnumber=axi_arvalid +T 3800 3600 5 10 0 1 0 7 1 1 +pinseq=30 +} Index: sym/axi_model_slave.sym =================================================================== --- sym/axi_model_slave.sym (nonexistent) +++ sym/axi_model_slave.sym (revision 135) @@ -0,0 +1,224 @@ +v 20100214 1 +B 300 0 3500 4300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 4450 5 10 1 1 0 0 1 1 +device=axi_model_slave +T 400 4650 5 10 1 1 0 0 1 1 +refdes=U? +T 400 4800 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 4800 0 10 0 1 0 0 1 1 +library=Testbench +T 400 4800 0 10 0 1 0 0 1 1 +component=axi_model +T 400 4800 0 10 0 1 0 0 1 1 +version=slave +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=axi_wstrb[3:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=axi_wdata[31:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=axi_awsize[2:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 10 1 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=axi_awlen[7:0] +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 10 1 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=axi_awid[11:0] +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 10 1 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=axi_awburst[1:0] +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 10 1 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=axi_awaddr[31:0] +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 300 1600 0 1600 10 1 1 +{ +T 400 1600 5 10 1 1 0 1 1 1 +pinnumber=axi_arsize[2:0] +T 400 1600 5 10 0 1 0 1 1 1 +pinseq=8 +} +P 300 1800 0 1800 10 1 1 +{ +T 400 1800 5 10 1 1 0 1 1 1 +pinnumber=axi_arlen[7:0] +T 400 1800 5 10 0 1 0 1 1 1 +pinseq=9 +} +P 300 2000 0 2000 10 1 1 +{ +T 400 2000 5 10 1 1 0 1 1 1 +pinnumber=axi_arid[11:0] +T 400 2000 5 10 0 1 0 1 1 1 +pinseq=10 +} +P 300 2200 0 2200 10 1 1 +{ +T 400 2200 5 10 1 1 0 1 1 1 +pinnumber=axi_arburst[1:0] +T 400 2200 5 10 0 1 0 1 1 1 +pinseq=11 +} +P 300 2400 0 2400 10 1 1 +{ +T 400 2400 5 10 1 1 0 1 1 1 +pinnumber=axi_araddr[31:0] +T 400 2400 5 10 0 1 0 1 1 1 +pinseq=12 +} +P 300 2600 0 2600 4 0 1 +{ +T 400 2600 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 2600 5 10 0 1 0 1 1 1 +pinseq=13 +} +P 300 2800 0 2800 4 0 1 +{ +T 400 2800 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 2800 5 10 0 1 0 1 1 1 +pinseq=14 +} +P 300 3000 0 3000 4 0 1 +{ +T 400 3000 5 10 1 1 0 1 1 1 +pinnumber=axi_wvalid +T 400 3000 5 10 0 1 0 1 1 1 +pinseq=15 +} +P 300 3200 0 3200 4 0 1 +{ +T 400 3200 5 10 1 1 0 1 1 1 +pinnumber=axi_wlast +T 400 3200 5 10 0 1 0 1 1 1 +pinseq=16 +} +P 300 3400 0 3400 4 0 1 +{ +T 400 3400 5 10 1 1 0 1 1 1 +pinnumber=axi_rready +T 400 3400 5 10 0 1 0 1 1 1 +pinseq=17 +} +P 300 3600 0 3600 4 0 1 +{ +T 400 3600 5 10 1 1 0 1 1 1 +pinnumber=axi_bready +T 400 3600 5 10 0 1 0 1 1 1 +pinseq=18 +} +P 300 3800 0 3800 4 0 1 +{ +T 400 3800 5 10 1 1 0 1 1 1 +pinnumber=axi_awvalid +T 400 3800 5 10 0 1 0 1 1 1 +pinseq=19 +} +P 300 4000 0 4000 4 0 1 +{ +T 400 4000 5 10 1 1 0 1 1 1 +pinnumber=axi_arvalid +T 400 4000 5 10 0 1 0 1 1 1 +pinseq=20 +} +P 3800 200 4100 200 10 1 1 +{ +T 3700 200 5 10 1 1 0 7 1 1 +pinnumber=axi_rid[11:0] +T 3700 200 5 10 0 1 0 7 1 1 +pinseq=21 +} +P 3800 400 4100 400 10 1 1 +{ +T 3700 400 5 10 1 1 0 7 1 1 +pinnumber=axi_rdata[31:0] +T 3700 400 5 10 0 1 0 7 1 1 +pinseq=22 +} +P 3800 600 4100 600 10 1 1 +{ +T 3700 600 5 10 1 1 0 7 1 1 +pinnumber=axi_bresp[1:0] +T 3700 600 5 10 0 1 0 7 1 1 +pinseq=23 +} +P 3800 800 4100 800 10 1 1 +{ +T 3700 800 5 10 1 1 0 7 1 1 +pinnumber=axi_bid[11:0] +T 3700 800 5 10 0 1 0 7 1 1 +pinseq=24 +} +P 3800 1000 4100 1000 4 0 1 +{ +T 3700 1000 5 10 1 1 0 7 1 1 +pinnumber=axi_wready +T 3800 1000 5 10 0 1 0 7 1 1 +pinseq=25 +} +P 3800 1200 4100 1200 4 0 1 +{ +T 3700 1200 5 10 1 1 0 7 1 1 +pinnumber=axi_rvalid +T 3800 1200 5 10 0 1 0 7 1 1 +pinseq=26 +} +P 3800 1400 4100 1400 4 0 1 +{ +T 3700 1400 5 10 1 1 0 7 1 1 +pinnumber=axi_rlast +T 3800 1400 5 10 0 1 0 7 1 1 +pinseq=27 +} +P 3800 1600 4100 1600 4 0 1 +{ +T 3700 1600 5 10 1 1 0 7 1 1 +pinnumber=axi_bvalid +T 3800 1600 5 10 0 1 0 7 1 1 +pinseq=28 +} +P 3800 1800 4100 1800 4 0 1 +{ +T 3700 1800 5 10 1 1 0 7 1 1 +pinnumber=axi_awready +T 3800 1800 5 10 0 1 0 7 1 1 +pinseq=29 +} +P 3800 2000 4100 2000 4 0 1 +{ +T 3700 2000 5 10 1 1 0 7 1 1 +pinnumber=axi_arready +T 3800 2000 5 10 0 1 0 7 1 1 +pinseq=30 +} Index: sym/clock_gen_def.sym =================================================================== --- sym/clock_gen_def.sym (nonexistent) +++ sym/clock_gen_def.sym (revision 135) @@ -0,0 +1,63 @@ +v 20100214 1 +B 300 0 3000 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1250 5 10 1 1 0 0 1 1 +device=clock_gen_def +T 400 1450 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1600 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1600 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1600 0 10 0 1 0 0 1 1 +component=clock_gen +T 400 1600 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=STOP[STOP_WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=BAD[BAD_WIDTH-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=START +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 3300 200 3600 200 4 0 1 +{ +T 3200 200 5 10 1 1 0 7 1 1 +pinnumber=reset +T 3300 200 5 10 0 1 0 7 1 1 +pinseq=5 +} +P 3300 400 3600 400 4 0 1 +{ +T 3200 400 5 10 1 1 0 7 1 1 +pinnumber=FINISH +T 3300 400 5 10 0 1 0 7 1 1 +pinseq=6 +} +P 3300 600 3600 600 4 0 1 +{ +T 3200 600 5 10 1 1 0 7 1 1 +pinnumber=FAIL +T 3300 600 5 10 0 1 0 7 1 1 +pinseq=7 +} Index: sym/display_model_def.sym =================================================================== --- sym/display_model_def.sym (nonexistent) +++ sym/display_model_def.sym (revision 135) @@ -0,0 +1,49 @@ +v 20100214 1 +B 300 0 1200 1300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1450 5 10 1 1 0 0 1 1 +device=display_model_def +T 400 1650 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1800 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1800 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1800 0 10 0 1 0 0 1 1 +component=display_model +T 400 1800 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=seg[6:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=an[3:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=dp +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} Index: sym/io_host_model_def.sym =================================================================== --- sym/io_host_model_def.sym (nonexistent) +++ sym/io_host_model_def.sym (revision 135) @@ -0,0 +1,91 @@ +v 20100214 1 +B 300 0 4900 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1650 5 10 1 1 0 0 1 1 +device=io_host_model_def +T 400 1850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2000 0 10 0 1 0 0 1 1 +library=Testbench +T 400 2000 0 10 0 1 0 0 1 1 +component=io_host_model +T 400 2000 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=io_host_out_bits[15:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=io_host_out_valid +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=io_host_in_ready +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 5200 200 5500 200 10 1 1 +{ +T 5100 200 5 10 1 1 0 7 1 1 +pinnumber=io_host_in_bits[15:0] +T 5100 200 5 10 0 1 0 7 1 1 +pinseq=6 +} +P 5200 400 5500 400 4 0 1 +{ +T 5100 400 5 10 1 1 0 7 1 1 +pinnumber=io_host_out_ready +T 5200 400 5 10 0 1 0 7 1 1 +pinseq=7 +} +P 5200 600 5500 600 4 0 1 +{ +T 5100 600 5 10 1 1 0 7 1 1 +pinnumber=io_host_in_valid +T 5200 600 5 10 0 1 0 7 1 1 +pinseq=8 +} +P 5200 800 5500 800 4 0 1 +{ +T 5100 800 5 10 1 1 0 7 1 1 +pinnumber=io_host_debug_stats_pcr +T 5200 800 5 10 0 1 0 7 1 1 +pinseq=9 +} +P 5200 1000 5500 1000 4 0 1 +{ +T 5100 1000 5 10 1 1 0 7 1 1 +pinnumber=io_host_clk_edge +T 5200 1000 5 10 0 1 0 7 1 1 +pinseq=10 +} +P 5200 1200 5500 1200 4 0 1 +{ +T 5100 1200 5 10 1 1 0 7 1 1 +pinnumber=io_host_clk +T 5200 1200 5 10 0 1 0 7 1 1 +pinseq=11 +} Index: sym/io_mem_model_def.sym =================================================================== --- sym/io_mem_model_def.sym (nonexistent) +++ sym/io_mem_model_def.sym (revision 135) @@ -0,0 +1,147 @@ +v 20100214 1 +B 300 0 6400 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 2650 5 10 1 1 0 0 1 1 +device=io_mem_model_def +T 400 2850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 3000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 3000 0 10 0 1 0 0 1 1 +library=Testbench +T 400 3000 0 10 0 1 0 0 1 1 +component=io_mem_model +T 400 3000 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=io_mem_req_data_bits_data[127:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=io_mem_req_cmd_bits_tag[4:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=io_mem_req_cmd_bits_addr[25:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=io_mem_req_data_valid +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=io_mem_req_cmd_valid +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=io_mem_req_cmd_bits_rw +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 300 1600 0 1600 4 0 1 +{ +T 400 1600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1600 5 10 0 1 0 1 1 1 +pinseq=8 +} +P 6700 200 7000 200 10 1 1 +{ +T 6600 200 5 10 1 1 0 7 1 1 +pinnumber=io_mem_resp_bits_tag[4:0] +T 6600 200 5 10 0 1 0 7 1 1 +pinseq=9 +} +P 6700 400 7000 400 10 1 1 +{ +T 6600 400 5 10 1 1 0 7 1 1 +pinnumber=io_mem_resp_bits_data[127:0] +T 6600 400 5 10 0 1 0 7 1 1 +pinseq=10 +} +P 6700 600 7000 600 4 0 1 +{ +T 6600 600 5 10 1 1 0 7 1 1 +pinnumber=io_out_mem_valid +T 6700 600 5 10 0 1 0 7 1 1 +pinseq=11 +} +P 6700 800 7000 800 4 0 1 +{ +T 6600 800 5 10 1 1 0 7 1 1 +pinnumber=io_out_mem_ready +T 6700 800 5 10 0 1 0 7 1 1 +pinseq=12 +} +P 6700 1000 7000 1000 4 0 1 +{ +T 6600 1000 5 10 1 1 0 7 1 1 +pinnumber=io_mem_resp_valid +T 6700 1000 5 10 0 1 0 7 1 1 +pinseq=13 +} +P 6700 1200 7000 1200 4 0 1 +{ +T 6600 1200 5 10 1 1 0 7 1 1 +pinnumber=io_mem_resp_ready +T 6700 1200 5 10 0 1 0 7 1 1 +pinseq=14 +} +P 6700 1400 7000 1400 4 0 1 +{ +T 6600 1400 5 10 1 1 0 7 1 1 +pinnumber=io_mem_req_data_ready +T 6700 1400 5 10 0 1 0 7 1 1 +pinseq=15 +} +P 6700 1600 7000 1600 4 0 1 +{ +T 6600 1600 5 10 1 1 0 7 1 1 +pinnumber=io_mem_req_cmd_ready +T 6700 1600 5 10 0 1 0 7 1 1 +pinseq=16 +} +P 6700 1800 7000 1800 4 0 1 +{ +T 6600 1800 5 10 1 1 0 7 1 1 +pinnumber=io_mem_backup_en +T 6700 1800 5 10 0 1 0 7 1 1 +pinseq=17 +} +P 6700 2000 7000 2000 4 0 1 +{ +T 6600 2000 5 10 1 1 0 7 1 1 +pinnumber=io_in_mem_valid +T 6700 2000 5 10 0 1 0 7 1 1 +pinseq=18 +} +P 6700 2200 7000 2200 4 0 1 +{ +T 6600 2200 5 10 1 1 0 7 1 1 +pinnumber=io_in_mem_ready +T 6700 2200 5 10 0 1 0 7 1 1 +pinseq=19 +} Index: sym/io_probe_def.sym =================================================================== --- sym/io_probe_def.sym (nonexistent) +++ sym/io_probe_def.sym (revision 135) @@ -0,0 +1,49 @@ +v 20100214 1 +B 300 0 4600 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1250 5 10 1 1 0 0 1 1 +device=io_probe_def +T 400 1450 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1600 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1600 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1600 0 10 0 1 0 0 1 1 +component=io_probe +T 400 1600 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=mask[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=expected_value[WIDTH-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=drive_value[WIDTH-1:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 4900 200 5200 200 10 1 1 +{ +T 4800 200 5 10 1 1 0 7 1 1 +pinnumber=signal[WIDTH-1:0] +T 4800 200 5 10 0 1 0 7 1 1 +pinseq=5 +} Index: sym/io_probe_in.sym =================================================================== --- sym/io_probe_in.sym (nonexistent) +++ sym/io_probe_in.sym (revision 135) @@ -0,0 +1,42 @@ +v 20100214 1 +B 300 0 2900 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1250 5 10 1 1 0 0 1 1 +device=io_probe_in +T 400 1450 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1600 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1600 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1600 0 10 0 1 0 0 1 1 +component=io_probe +T 400 1600 0 10 0 1 0 0 1 1 +version=in +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=signal[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=mask[WIDTH-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=expected_value[WIDTH-1:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} Index: sym/jtag_model_def.sym =================================================================== --- sym/jtag_model_def.sym (nonexistent) +++ sym/jtag_model_def.sym (revision 135) @@ -0,0 +1,63 @@ +v 20100214 1 +B 300 0 1500 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1250 5 10 1 1 0 0 1 1 +device=jtag_model_def +T 400 1450 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1600 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1600 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1600 0 10 0 1 0 0 1 1 +component=jtag_model +T 400 1600 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=tdi +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 1800 200 2100 200 4 0 1 +{ +T 1700 200 5 10 1 1 0 7 1 1 +pinnumber=trst_n +T 1800 200 5 10 0 1 0 7 1 1 +pinseq=4 +} +P 1800 400 2100 400 4 0 1 +{ +T 1700 400 5 10 1 1 0 7 1 1 +pinnumber=tms +T 1800 400 5 10 0 1 0 7 1 1 +pinseq=5 +} +P 1800 600 2100 600 4 0 1 +{ +T 1700 600 5 10 1 1 0 7 1 1 +pinnumber=tdo +T 1800 600 5 10 0 1 0 7 1 1 +pinseq=6 +} +P 1800 800 2100 800 4 0 1 +{ +T 1700 800 5 10 1 1 0 7 1 1 +pinnumber=tclk +T 1800 800 5 10 0 1 0 7 1 1 +pinseq=7 +} Index: sym/micro_bus16_model_def.sym =================================================================== --- sym/micro_bus16_model_def.sym (nonexistent) +++ sym/micro_bus16_model_def.sym (revision 135) @@ -0,0 +1,84 @@ +v 20100214 1 +B 300 0 2600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=micro_bus16_model_def +T 400 2050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2200 0 10 0 1 0 0 1 1 +library=Testbench +T 400 2200 0 10 0 1 0 0 1 1 +component=micro_bus16_model +T 400 2200 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=rdata[15:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 2900 200 3200 200 10 1 1 +{ +T 2800 200 5 10 1 1 0 7 1 1 +pinnumber=wdata[15:0] +T 2800 200 5 10 0 1 0 7 1 1 +pinseq=4 +} +P 2900 400 3200 400 10 1 1 +{ +T 2800 400 5 10 1 1 0 7 1 1 +pinnumber=cs[1:0] +T 2800 400 5 10 0 1 0 7 1 1 +pinseq=5 +} +P 2900 600 3200 600 10 1 1 +{ +T 2800 600 5 10 1 1 0 7 1 1 +pinnumber=addr[23:0] +T 2800 600 5 10 0 1 0 7 1 1 +pinseq=6 +} +P 2900 800 3200 800 4 0 1 +{ +T 2800 800 5 10 1 1 0 7 1 1 +pinnumber=wr +T 2900 800 5 10 0 1 0 7 1 1 +pinseq=7 +} +P 2900 1000 3200 1000 4 0 1 +{ +T 2800 1000 5 10 1 1 0 7 1 1 +pinnumber=ub +T 2900 1000 5 10 0 1 0 7 1 1 +pinseq=8 +} +P 2900 1200 3200 1200 4 0 1 +{ +T 2800 1200 5 10 1 1 0 7 1 1 +pinnumber=rd +T 2900 1200 5 10 0 1 0 7 1 1 +pinseq=9 +} +P 2900 1400 3200 1400 4 0 1 +{ +T 2800 1400 5 10 1 1 0 7 1 1 +pinnumber=lb +T 2900 1400 5 10 0 1 0 7 1 1 +pinseq=10 +} Index: sym/micro_bus_model_def.sym =================================================================== --- sym/micro_bus_model_def.sym (nonexistent) +++ sym/micro_bus_model_def.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 2900 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1650 5 10 1 1 0 0 1 1 +device=micro_bus_model_def +T 400 1850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2000 0 10 0 1 0 0 1 1 +library=Testbench +T 400 2000 0 10 0 1 0 0 1 1 +component=micro_bus_model +T 400 2000 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 3200 200 3500 200 10 1 1 +{ +T 3100 200 5 10 1 1 0 7 1 1 +pinnumber=wdata[7:0] +T 3100 200 5 10 0 1 0 7 1 1 +pinseq=3 +} +P 3200 400 3500 400 10 1 1 +{ +T 3100 400 5 10 1 1 0 7 1 1 +pinnumber=addr[addr_width-1:0] +T 3100 400 5 10 0 1 0 7 1 1 +pinseq=4 +} +P 3200 600 3500 600 10 1 1 +{ +T 3100 600 5 10 1 1 0 7 1 1 +pinnumber=rdata[7:0] +T 3100 600 5 10 0 1 0 7 1 1 +pinseq=5 +} +P 3200 800 3500 800 4 0 1 +{ +T 3100 800 5 10 1 1 0 7 1 1 +pinnumber=wr +T 3200 800 5 10 0 1 0 7 1 1 +pinseq=6 +} +P 3200 1000 3500 1000 4 0 1 +{ +T 3100 1000 5 10 1 1 0 7 1 1 +pinnumber=rd +T 3200 1000 5 10 0 1 0 7 1 1 +pinseq=7 +} +P 3200 1200 3500 1200 4 0 1 +{ +T 3100 1200 5 10 1 1 0 7 1 1 +pinnumber=cs +T 3200 1200 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: sym/mt45w8mw12_def.sym =================================================================== --- sym/mt45w8mw12_def.sym (nonexistent) +++ sym/mt45w8mw12_def.sym (revision 135) @@ -0,0 +1,91 @@ +v 20100214 1 +B 300 0 3800 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 2250 5 10 1 1 0 0 1 1 +device=mt45w8mw12_def +T 400 2450 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2600 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2600 0 10 0 1 0 0 1 1 +library=Testbench +T 400 2600 0 10 0 1 0 0 1 1 +component=mt45w8mw12 +T 400 2600 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=addr[ADDR_BITS-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=we_n +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=ub_n +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=oe_n +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=lb_n +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=cre +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 300 1600 0 1600 4 0 1 +{ +T 400 1600 5 10 1 1 0 1 1 1 +pinnumber=ce_n +T 400 1600 5 10 0 1 0 1 1 1 +pinseq=8 +} +P 300 1800 0 1800 4 0 1 +{ +T 400 1800 5 10 1 1 0 1 1 1 +pinnumber=adv_n +T 400 1800 5 10 0 1 0 1 1 1 +pinseq=9 +} +P 4100 200 4400 200 10 1 1 +{ +T 4000 200 5 10 1 1 0 7 1 1 +pinnumber=dq[DQ_BITS-1:0] +T 4000 200 5 10 0 1 0 7 1 1 +pinseq=10 +} +P 4100 400 4400 400 4 0 1 +{ +T 4000 400 5 10 1 1 0 7 1 1 +pinnumber=o_wait +T 4100 400 5 10 0 1 0 7 1 1 +pinseq=11 +} Index: sym/ps2_host_def.sym =================================================================== --- sym/ps2_host_def.sym (nonexistent) +++ sym/ps2_host_def.sym (revision 135) @@ -0,0 +1,112 @@ +v 20100214 1 +B 300 0 3100 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 2650 5 10 1 1 0 0 1 1 +device=ps2_host_def +T 400 2850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 3000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 3000 0 10 0 1 0 0 1 1 +library=Testbench +T 400 3000 0 10 0 1 0 0 1 1 +component=ps2_host +T 400 3000 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=rx_data[7:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=tx_ack_error +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=rx_read +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rx_parity_rcv +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=rx_parity_error +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=rx_parity_cal +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=rx_full +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 300 1600 0 1600 4 0 1 +{ +T 400 1600 5 10 1 1 0 1 1 1 +pinnumber=rx_frame_error +T 400 1600 5 10 0 1 0 1 1 1 +pinseq=8 +} +P 300 1800 0 1800 4 0 1 +{ +T 400 1800 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 1800 5 10 0 1 0 1 1 1 +pinseq=9 +} +P 300 2000 0 2000 4 0 1 +{ +T 400 2000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 2000 5 10 0 1 0 1 1 1 +pinseq=10 +} +P 300 2200 0 2200 4 0 1 +{ +T 400 2200 5 10 1 1 0 1 1 1 +pinnumber=busy +T 400 2200 5 10 0 1 0 1 1 1 +pinseq=11 +} +P 3400 200 3700 200 10 1 1 +{ +T 3300 200 5 10 1 1 0 7 1 1 +pinnumber=tx_data[7:0] +T 3300 200 5 10 0 1 0 7 1 1 +pinseq=12 +} +P 3400 400 3700 400 4 0 1 +{ +T 3300 400 5 10 1 1 0 7 1 1 +pinnumber=tx_write +T 3400 400 5 10 0 1 0 7 1 1 +pinseq=13 +} +P 3400 600 3700 600 4 0 1 +{ +T 3300 600 5 10 1 1 0 7 1 1 +pinnumber=rx_clr +T 3400 600 5 10 0 1 0 7 1 1 +pinseq=14 +} Index: sym/ps2_model_def.sym =================================================================== --- sym/ps2_model_def.sym (nonexistent) +++ sym/ps2_model_def.sym (revision 135) @@ -0,0 +1,42 @@ +v 20100214 1 +B 300 0 1700 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 850 5 10 1 1 0 0 1 1 +device=ps2_model_def +T 400 1050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1200 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1200 0 10 0 1 0 0 1 1 +component=ps2_model +T 400 1200 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 2000 200 2300 200 4 0 1 +{ +T 1900 200 5 10 1 1 0 7 1 1 +pinnumber=ps2_data +T 2000 200 5 10 0 1 0 7 1 1 +pinseq=3 +} +P 2000 400 2300 400 4 0 1 +{ +T 1900 400 5 10 1 1 0 7 1 1 +pinnumber=ps2_clk +T 2000 400 5 10 0 1 0 7 1 1 +pinseq=4 +} Index: sym/spi_host_def.sym =================================================================== --- sym/spi_host_def.sym (nonexistent) +++ sym/spi_host_def.sym (revision 135) @@ -0,0 +1,112 @@ +v 20100214 1 +B 300 0 3100 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 2650 5 10 1 1 0 0 1 1 +device=spi_host_def +T 400 2850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 3000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 3000 0 10 0 1 0 0 1 1 +library=Testbench +T 400 3000 0 10 0 1 0 0 1 1 +component=spi_host +T 400 3000 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=rx_data[7:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=tx_ack_error +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=rx_read +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rx_parity_rcv +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=rx_parity_error +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=rx_parity_cal +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=rx_full +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 300 1600 0 1600 4 0 1 +{ +T 400 1600 5 10 1 1 0 1 1 1 +pinnumber=rx_frame_error +T 400 1600 5 10 0 1 0 1 1 1 +pinseq=8 +} +P 300 1800 0 1800 4 0 1 +{ +T 400 1800 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 1800 5 10 0 1 0 1 1 1 +pinseq=9 +} +P 300 2000 0 2000 4 0 1 +{ +T 400 2000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 2000 5 10 0 1 0 1 1 1 +pinseq=10 +} +P 300 2200 0 2200 4 0 1 +{ +T 400 2200 5 10 1 1 0 1 1 1 +pinnumber=busy +T 400 2200 5 10 0 1 0 1 1 1 +pinseq=11 +} +P 3400 200 3700 200 10 1 1 +{ +T 3300 200 5 10 1 1 0 7 1 1 +pinnumber=tx_data[7:0] +T 3300 200 5 10 0 1 0 7 1 1 +pinseq=12 +} +P 3400 400 3700 400 4 0 1 +{ +T 3300 400 5 10 1 1 0 7 1 1 +pinnumber=tx_write +T 3400 400 5 10 0 1 0 7 1 1 +pinseq=13 +} +P 3400 600 3700 600 4 0 1 +{ +T 3300 600 5 10 1 1 0 7 1 1 +pinnumber=rx_clr +T 3400 600 5 10 0 1 0 7 1 1 +pinseq=14 +} Index: sym/spi_model_def.sym =================================================================== --- sym/spi_model_def.sym (nonexistent) +++ sym/spi_model_def.sym (revision 135) @@ -0,0 +1,42 @@ +v 20100214 1 +B 300 0 1700 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 850 5 10 1 1 0 0 1 1 +device=spi_model_def +T 400 1050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1200 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1200 0 10 0 1 0 0 1 1 +component=spi_model +T 400 1200 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 2000 200 2300 200 4 0 1 +{ +T 1900 200 5 10 1 1 0 7 1 1 +pinnumber=spi_data +T 2000 200 5 10 0 1 0 7 1 1 +pinseq=3 +} +P 2000 400 2300 400 4 0 1 +{ +T 1900 400 5 10 1 1 0 7 1 1 +pinnumber=spi_clk +T 2000 400 5 10 0 1 0 7 1 1 +pinseq=4 +} Index: sym/spi_model_master.sym =================================================================== --- sym/spi_model_master.sym (nonexistent) +++ sym/spi_model_master.sym (revision 135) @@ -0,0 +1,56 @@ +v 20100214 1 +B 300 0 2100 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1050 5 10 1 1 0 0 1 1 +device=spi_model_master +T 400 1250 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1400 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1400 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1400 0 10 0 1 0 0 1 1 +component=spi_model +T 400 1400 0 10 0 1 0 0 1 1 +version=master +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=spi_miso +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 2400 200 2700 200 4 0 1 +{ +T 2300 200 5 10 1 1 0 7 1 1 +pinnumber=spi_sel_n +T 2400 200 5 10 0 1 0 7 1 1 +pinseq=4 +} +P 2400 400 2700 400 4 0 1 +{ +T 2300 400 5 10 1 1 0 7 1 1 +pinnumber=spi_mosi +T 2400 400 5 10 0 1 0 7 1 1 +pinseq=5 +} +P 2400 600 2700 600 4 0 1 +{ +T 2300 600 5 10 1 1 0 7 1 1 +pinnumber=spi_clk +T 2400 600 5 10 0 1 0 7 1 1 +pinseq=6 +} Index: sym/uart_host_def.sym =================================================================== --- sym/uart_host_def.sym (nonexistent) +++ sym/uart_host_def.sym (revision 135) @@ -0,0 +1,126 @@ +v 20100214 1 +B 300 0 3900 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 2250 5 10 1 1 0 0 1 1 +device=uart_host_def +T 400 2450 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2600 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2600 0 10 0 1 0 0 1 1 +library=Testbench +T 400 2600 0 10 0 1 0 0 1 1 +component=uart_host +T 400 2600 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=rxd_data_out[7:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=txd_buffer_empty +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=rxd_stop_error +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rxd_parity_error +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=rxd_data_avail +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 4200 200 4500 200 10 1 1 +{ +T 4100 200 5 10 1 1 0 7 1 1 +pinnumber=txd_data_in[7:0] +T 4100 200 5 10 0 1 0 7 1 1 +pinseq=8 +} +P 4200 400 4500 400 4 0 1 +{ +T 4100 400 5 10 1 1 0 7 1 1 +pinnumber=txd_parity +T 4200 400 5 10 0 1 0 7 1 1 +pinseq=9 +} +P 4200 600 4500 600 4 0 1 +{ +T 4100 600 5 10 1 1 0 7 1 1 +pinnumber=txd_load +T 4200 600 5 10 0 1 0 7 1 1 +pinseq=10 +} +P 4200 800 4500 800 4 0 1 +{ +T 4100 800 5 10 1 1 0 7 1 1 +pinnumber=txd_force_parity +T 4200 800 5 10 0 1 0 7 1 1 +pinseq=11 +} +P 4200 1000 4500 1000 4 0 1 +{ +T 4100 1000 5 10 1 1 0 7 1 1 +pinnumber=txd_break +T 4200 1000 5 10 0 1 0 7 1 1 +pinseq=12 +} +P 4200 1200 4500 1200 4 0 1 +{ +T 4100 1200 5 10 1 1 0 7 1 1 +pinnumber=rxd_parity +T 4200 1200 5 10 0 1 0 7 1 1 +pinseq=13 +} +P 4200 1400 4500 1400 4 0 1 +{ +T 4100 1400 5 10 1 1 0 7 1 1 +pinnumber=rxd_force_parity +T 4200 1400 5 10 0 1 0 7 1 1 +pinseq=14 +} +P 4200 1600 4500 1600 4 0 1 +{ +T 4100 1600 5 10 1 1 0 7 1 1 +pinnumber=rxd_data_avail_stb +T 4200 1600 5 10 0 1 0 7 1 1 +pinseq=15 +} +P 4200 1800 4500 1800 4 0 1 +{ +T 4100 1800 5 10 1 1 0 7 1 1 +pinnumber=parity_enable +T 4200 1800 5 10 0 1 0 7 1 1 +pinseq=16 +} Index: sym/uart_model_def.sym =================================================================== --- sym/uart_model_def.sym (nonexistent) +++ sym/uart_model_def.sym (revision 135) @@ -0,0 +1,42 @@ +v 20100214 1 +B 300 0 1700 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1050 5 10 1 1 0 0 1 1 +device=uart_model_def +T 400 1250 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1400 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1400 0 10 0 1 0 0 1 1 +library=Testbench +T 400 1400 0 10 0 1 0 0 1 1 +component=uart_model +T 400 1400 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=txd_in +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 2000 200 2300 200 4 0 1 +{ +T 1900 200 5 10 1 1 0 7 1 1 +pinnumber=rxd_out +T 2000 200 5 10 0 1 0 7 1 1 +pinseq=4 +} Index: sym/vga_model_def.sym =================================================================== --- sym/vga_model_def.sym (nonexistent) +++ sym/vga_model_def.sym (revision 135) @@ -0,0 +1,63 @@ +v 20100214 1 +B 300 0 1400 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=vga_model_def +T 400 2050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2200 0 10 0 1 0 0 1 1 +library=Testbench +T 400 2200 0 10 0 1 0 0 1 1 +component=vga_model +T 400 2200 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=red[2:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=green[2:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=blue[1:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=vsync_n +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=hsync_n +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +}

powered by: WebSVN 2.1.0

NAME	Type	Description
addr[23:0 ]	output
clk	input
cs[1:0 ]	output
lb	output
rd	output
rdata[15:0 ]	input
reset	input
ub	output
wdata[15:0 ]	output
wr	output

Instance	Vendor	Library	Component	Version
rdata_tpb	opencores.org	Testbench	io_probe	in

Name	default	Description
MESG	" "
WIDTH	1
RESET	{WIDTH{1'bz}}
IN_DELAY	5
OUT_DELAY	15
OUT_WIDTH	10

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