OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/Testbench/mt45w8mw12
    from Rev 134 to Rev 135
    ↔ Reverse comparison
  •

Rev 134 → Rev 135

/bin/Makefile File deleted
/componentCfg.xml
3,7 → 3,7
 
-->
<socgen:componentConfiguration
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
/rtl/xml/mt45w8mw12_def.xml
27,17 → 27,17
// from http://www.opencores.org/lgpl.shtml //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>Testbench</spirit:library>
<spirit:name>mt45w8mw12</spirit:name>
<spirit:version>def</spirit:version> <spirit:configuration>default</spirit:configuration>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>Testbench</ipxact:library>
<ipxact:name>mt45w8mw12</ipxact:name>
<ipxact:version>def</ipxact:version>
 
 
 
45,221 → 45,221
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_sim</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>sim</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_syn</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>syn</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/copyright.v</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/top.sim</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/sim/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-syn</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/copyright.v</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.syn</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/top.syn</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<ipxact:view>
<ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-syn</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
<ipxact:view>
<ipxact:name>doc</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="documentation"/>
</ipxact:vendorExtensions>
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>ADDR_BITS</spirit:name><spirit:value>23</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DQ_BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>MEM_BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>ADDR_BITS</ipxact:name><ipxact:value>23</ipxact:value></ipxact:modelParameter>
<ipxact:modelParameter><ipxact:name>DQ_BITS</ipxact:name><ipxact:value>16</ipxact:value></ipxact:modelParameter>
<ipxact:modelParameter><ipxact:name>MEM_BITS</ipxact:name><ipxact:value>16</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
 
<spirit:ports>
<ipxact:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>clk</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>adv_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>adv_n</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>cre</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>cre</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>o_wait</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>o_wait</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>out</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
<spirit:port><spirit:name>ce_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>ce_n</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
<spirit:port><spirit:name>oe_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>oe_n</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>we_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>we_n</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
<spirit:port><spirit:name>lb_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>lb_n</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>ub_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>ub_n</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>addr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>ADDR_BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>addr</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>ADDR_BITS-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
 
<spirit:port><spirit:name>dq</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>inout</spirit:direction>
<spirit:vector><spirit:left>DQ_BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>dq</ipxact:name>
<ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:wire><ipxact:direction>inout</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>DQ_BITS-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
 
</spirit:ports>
</ipxact:ports>
 
</spirit:model>
</ipxact:model>
 
 
 
274,4 → 274,4
 
 
 
</spirit:component>
</ipxact:component>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.