URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/Testbench/toolflows
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/toolflow/xml/ise.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
41,31 → 41,7
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>gen_root</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_root</spirit:generatorExe> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
73,10 → 49,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
83,28 → 55,10
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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117,25 → 71,12
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
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<spirit:views> |
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<spirit:view> |
<spirit:name>syn</spirit:name> |
<spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
143,14 → 84,8
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef> |
</spirit:view> |
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</spirit:views> |
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</spirit:model> |
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</spirit:component> |
/toolflow/xml/icarus.xml
43,6 → 43,27
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<spirit:componentGenerator> |
<spirit:name>gen_elab_filelists</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions> |
<socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier> |
<socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier> |
</spirit:vendorExtensions> |
<spirit:generatorExe>./tools/sys/gen_elab_child_filelist</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>top_file</spirit:name> |
<spirit:value>./TestBench</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_filelists</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
63,6 → 84,8
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_cov_filelist</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
101,10 → 124,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
120,10 → 139,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
139,10 → 154,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>lint</spirit:value> |
</spirit:parameter> |
/toolflow/xml/verilator.xml
102,10 → 102,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
122,10 → 118,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>lint</spirit:value> |
</spirit:parameter> |
/toolflow/xml/verilog.xml
42,31 → 42,7
<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>gen_root</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_root</spirit:generatorExe> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
</spirit:componentGenerator> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
74,10 → 50,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
94,10 → 66,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
/toolflow/xml/rtl_check.xml
71,13 → 71,6
<spirit:vendorExtensions><socgen:envIdentifier>:*Lint:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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92,10 → 85,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>lint</spirit:value> |
</spirit:parameter> |