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  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog
    from Rev 131 to Rev 134
    ↔ Reverse comparison
  •

Rev 131 → Rev 134

/timescale
0,0 → 1,?rev2len?
`timescale 1 ns / 10ps
/sim/dll
0,0 → 1,65
localparam MIN_CLK_DELAY = 0.01;
 
//****************************************************************************
// Measure the clock in period. Use the and the multiplication
// factor to determine the period for the output clock
//****************************************************************************
real last_edge_time;
real this_edge_time; // $realtime when the input clock edges occur
real ref_clk_period; // input clock period
real dll_clk_out_period; // output clock period
real clk_delay;
 
initial last_edge_time = 0;
initial dll_clk_out_period = 1;
 
always @(posedge ref_clk)
begin
this_edge_time = $realtime;
ref_clk_period = this_edge_time - last_edge_time;
dll_clk_out_period = (ref_clk_period) / MULT;
last_edge_time = this_edge_time;
end
 
 
 
 
//*****************************************************************************
// Create a new clock
//*****************************************************************************
 
 
reg [SIZE-1:0] divider;
initial
begin
dll_clk_out = 1'b0;
forever
begin
clk_delay = (dll_clk_out_period/2);
if (clk_delay < MIN_CLK_DELAY)
clk_delay = MIN_CLK_DELAY;
#(clk_delay) dll_clk_out = ~dll_clk_out;
end
end
 
always@(posedge dll_clk_out or posedge reset )
if ( reset) divider <= DIV/2;
else if ( divider == 'b1) divider <= DIV/2;
else divider <= divider - 'b1;
always@(posedge dll_clk_out or posedge reset )
if(reset) div_clk_out <= 1'b0;
else if (divider == 'b1) div_clk_out <= !div_clk_out;
else div_clk_out <= div_clk_out;
 
 
 
 
 
 
/copyright
0,0 → 1,20
/**********************************************************************/
/* */
/* */
/* Copyright (c) 2012 Ouabache Design Works */
/* */
/* All Rights Reserved Worldwide */
/* */
/* Licensed under the Apache License,Version2.0 (the'License'); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in */
/* writing, software distributed under the License is */
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
/* OR CONDITIONS OF ANY KIND, either express or implied. */
/* See the License for the specific language governing */
/* permissions and limitations under the License. */
/**********************************************************************/
/syn/dll
0,0 → 1,12
 
always@(*)
begin
dll_clk_out = ref_clk;
end
 
 
always@(posedge ref_clk or posedge reset)
if(reset) div_clk_out <= 1'b0;
else div_clk_out <= !div_clk_out;
 
 
/clock_sys
0,0 → 1,78
reg [6:0] counter;
reg [3:0] reset_cnt;
 
 
 
always@(posedge ckIn or posedge pwron_reset)
if(pwron_reset) pwron_reset_n <= 1'b0;
else pwron_reset_n <= 1'b1;
 
generate
 
if( CLOCK_SRC)
 
begin
assign ckIn = b_clk_pad_in;
end
else
begin
assign ckIn = a_clk_pad_in;
end
 
endgenerate
 
 
generate
 
if( RESET_SENSE)
 
begin
assign pwron_reset = !pwron_pad_in;
end
else
begin
assign pwron_reset = pwron_pad_in;
end
 
endgenerate
 
 
 
 
 
 
always@(posedge ckIn or posedge pwron_reset)
if( pwron_reset) reset_cnt <= 4'b1111;
else
if(|reset_cnt) reset_cnt <= reset_cnt-4'b0001;
else reset_cnt <= 4'b0000;
 
 
always@(posedge ckIn or posedge pwron_reset)
if( pwron_reset) ref_reset <= 1'b1;
else ref_reset <= |reset_cnt;
 
 
always@(posedge dll_clk)
if(dll_reset)
begin
one_usec <= 1'b0;
counter <= FREQ*PLL_MULT/2;
end
else if(counter == 7'b0000001)
begin
one_usec <= !one_usec;
counter <= FREQ*PLL_MULT/2;
end
else
begin
one_usec <= one_usec;
counter <= counter -7'b0000001;
end
/clock_sys.v
33,27 → 33,27
input wire a_clk_pad_in,
input wire b_clk_pad_in,
input wire pwron_pad_in,
 
 
output wire div_clk_out,
 
output reg one_usec,
output wire reset
output wire reset
 
);
 
wire ckIn;
wire dll_clk;
reg ref_reset;
reg ref_reset;
reg [6:0] counter;
reg [3:0] reset_cnt;
 
wire pwron_reset;
wire pwron_reset_n;
wire dll_reset;
assign pwron_reset_n = !pwron_reset;
 
generate
 
if( CLOCK_SRC)
144,7 → 144,7
)
ref_rsync(
.clk (div_clk_out),
.reset_n (!pwron_reset),
.reset_n (pwron_reset_n),
.data_in (ref_reset),
.data_out (reset)
);
157,7 → 157,7
)
dll_rsync(
.clk (dll_clk),
.reset_n (!pwron_reset),
.reset_n (pwron_reset_n),
.data_in (ref_reset),
.data_out (dll_reset)
);
/clock_gater
0,0 → 1,19
 
wire latch_enable;
reg latch_output;
 
assign latch_enable = enable | atg_clk_mode;
 
always @(latch_enable or clk_in)
begin
if (~clk_in)
latch_output = latch_enable;
else
latch_output = latch_output;
end
 
assign clk_out = latch_output && clk_in;
 
 
 

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