OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/cde/ip/fifo
    from Rev 133 to Rev 134
    ↔ Reverse comparison
  •

Rev 133 → Rev 134

/componentCfg.xml
2,8 → 2,8
<!--
 
-->
<socgen:componentConfiguration
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<socgen:componentConfiguration
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
11,7 → 11,6
<socgen:library>cde</socgen:library>
<socgen:component>fifo</socgen:component>
 
 
<socgen:ip_name_depth>3</socgen:ip_name_depth>
<socgen:ip_name_vendor_sep>_</socgen:ip_name_vendor_sep>
<socgen:ip_name_library_sep>_</socgen:ip_name_library_sep>
26,9 → 25,121
 
</socgen:doc>
 
<socgen:configurations>
 
 
 
<socgen:configuration>
<socgen:name>default</socgen:name>
<socgen:version>def</socgen:version>
<socgen:version>def_tb</socgen:version>
<socgen:version>def_lint</socgen:version>
<socgen:parameters>
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>2</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>WORDS</socgen:name><socgen:value>4</socgen:value></socgen:parameter>
</socgen:parameters>
 
</socgen:configuration>
 
</socgen:configurations>
 
 
<socgen:sim>
 
<socgen:comp_path>fifo/sim</socgen:comp_path>
 
<socgen:testbenches>
 
<socgen:testbench>
<socgen:variant>fifo_def_tb</socgen:variant>
<socgen:version>def_tb</socgen:version>
<socgen:parameters>
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>10000</socgen:value></socgen:parameter>
</socgen:parameters>
<socgen:code_coverage>
<socgen:cover>
<socgen:name>cde_fifo_def</socgen:name><socgen:componentInstance>TB.test.dut</socgen:componentInstance>
</socgen:cover>
</socgen:code_coverage>
<socgen:tools>
<socgen:tool>icarus</socgen:tool>
<socgen:tool>coverage</socgen:tool>
</socgen:tools>
</socgen:testbench>
 
 
 
 
 
<socgen:testbench>
<socgen:variant>fifo_def_lint</socgen:variant>
<socgen:version>def_lint</socgen:version>
<socgen:tools>
<socgen:tool>rtl_check</socgen:tool>
</socgen:tools>
</socgen:testbench>
 
 
 
 
</socgen:testbenches>
 
 
 
 
 
 
 
<socgen:rtl_check>
 
 
 
 
 
<socgen:lint>
<socgen:name>default</socgen:name>
<socgen:variant>fifo_def_lint</socgen:variant>
</socgen:lint>
 
 
 
</socgen:rtl_check>
 
 
 
 
 
<socgen:icarus>
 
 
 
 
 
<socgen:test>
<socgen:name>default</socgen:name>
<socgen:variant>fifo_def_tb</socgen:variant>
<socgen:configuration>default</socgen:configuration>
</socgen:test>
 
 
 
 
 
 
 
</socgen:icarus>
 
 
 
 
 
 
</socgen:sim>
 
 
 
 
</socgen:componentConfiguration>
 
/rtl/xml/cde_fifo_def.design.xml
14,6 → 14,76
<spirit:name>fifo</spirit:name>
<spirit:version>def.design</spirit:version>
 
<spirit:vendorExtensions>
 
<socgen:nodes>
 
 
 
<socgen:node><spirit:name>push_pointer</spirit:name>
<spirit:typeName>reg</spirit:typeName>
<spirit:wire><spirit:vector><spirit:left>SIZE-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>
 
<socgen:node><spirit:name>pop_pointer</spirit:name>
<spirit:typeName>reg</spirit:typeName>
<spirit:wire><spirit:vector><spirit:left>SIZE-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>
 
 
</socgen:nodes>
</spirit:vendorExtensions>
 
 
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk"/>
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="clk"/>
</spirit:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>push</spirit:name>
<spirit:externalPortReference spirit:portRef="push"/>
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="wr"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>push_pointer</spirit:name>
<spirit:externalPortReference spirit:portRef="push_pointer" spirit:left="SIZE-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="waddr"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pop_pointer</spirit:name>
<spirit:externalPortReference spirit:portRef="pop_pointer" spirit:left="SIZE-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="raddr"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>din</spirit:name>
<spirit:externalPortReference spirit:portRef="din" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="wdata"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dout</spirit:name>
<spirit:externalPortReference spirit:portRef="dout" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="rdata"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection spirit:tiedValue="1'b1" >
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="cs"/>
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="rd"/>
</spirit:adHocConnection>
 
</spirit:adHocConnections>
 
 
 
 
<spirit:componentInstances>
 
 
26,7 → 96,6
<spirit:configurableElementValue spirit:referenceId="ADDR">SIZE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WRITETHRU">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="DEFAULT">DEFAULT</spirit:configurableElementValue>
</spirit:configurableElementValues>
 
</spirit:componentInstance>
/rtl/xml/cde_fifo_def.xml
20,64 → 20,32
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>fifo_def</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
</spirit:componentGenerators>
 
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
90,9 → 58,30
spirit:version="def.design"/>
</spirit:view>
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
102,7 → 91,6
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
110,6 → 98,7
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
132,12 → 121,87
</spirit:views>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/fifo_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/fifo_def</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>8'hff</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
 
174,7 → 238,7
 
 
<spirit:port><spirit:name>dout</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
/rtl/verilog/fifo_def.v File deleted
/rtl/verilog/fifo_def
0,0 → 1,182
reg r;
reg w;
reg [SIZE:0] push_1;
reg [SIZE:0] pop_1;
 
always@(*) push_1 = (push_pointer + 1'b1);
always@(*) pop_1 = (pop_pointer + 1'b1);
 
 
always@(*) r = (pop_pointer == push_1[SIZE-1:0]);
always@(*) w = (push_pointer == pop_1[SIZE-1:0]);
 
 
always@(posedge clk)
if(reset)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= {SIZE{1'b0}};
pop_pointer <= {SIZE{1'b0}};
end
else
if(empty && !full)
if( push && ~pop)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer+1;
pop_pointer <= pop_pointer;
end
else
if(~push && pop)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b1;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if( push && pop)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer + 1;
pop_pointer <= pop_pointer + 1;
end
else
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if(!empty && !full)
if( push && pop)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer + 1;
pop_pointer <= pop_pointer + 1;
end
else
if( push && !pop && r)
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer+1;
pop_pointer <= pop_pointer;
end
else
if( push && !pop && !r)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer+1;
pop_pointer <= pop_pointer;
end
else
if(~push && pop && w)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer+1;
end
else
if(~push && pop && !w)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer+1;
end
else
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if(!empty && full)
if( push && ~pop)
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b1;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if(~push && pop)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer+1;
end
else
if( push && pop)
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer + 1;
pop_pointer <= pop_pointer + 1;
end
else
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
// full and empty at the same time should never occur
 
else
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= {SIZE{1'b0}};
pop_pointer <= {SIZE{1'b0}};
end
 
 
 
 
/doc/Geda/html/cde_fifo_def.html
78,12 → 78,6
<td style="vertical-align: top;"><br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">DEFAULT<br> </td>
<td style="vertical-align: top;">8'hff<br> </td>
<td style="vertical-align: top;"><br></td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
/sim/icarus/default/test_define
0,0 → 1,37
 
 
initial
begin
$display(" ");
$display(" ===================================================");
$display(" Test Start");
$display(" ===================================================");
$display(" ");
test.cg.next(20);
test.write.u_write(8'h00, 8'h01);
test.cg.next(4);
test.read.u_cmp(8'h00, 8'h01);
test.cg.next(4);
test.write.u_write(8'h00, 8'h02);
test.cg.next(4);
test.read.u_cmp(8'h00, 8'h02);
test.cg.next(4);
test.write.u_write(8'h00, 8'h03);
test.cg.next(4);
test.read.u_cmp(8'h00, 8'h03);
test.cg.next(4);
test.write.u_write(8'h00, 8'h04);
test.cg.next(1);
test.read.u_cmp(8'h00, 8'h04);
test.cg.next(4);
 
test.cg.exit;
end
 
 
 
 
 
 
 
 
/sim/icarus/default/wave.sav
0,0 → 1,42
[*]
[*] GTKWave Analyzer v3.3.62 (w)1999-2014 BSI
[*] Fri May 29 00:14:27 2015
[*]
[dumpfile] "/home/johne/Desktop/socgen/work/opencores.org__cde/ip/fifo/sim/icarus/default/TestBench.vcd"
[dumpfile_mtime] "Fri May 29 00:12:25 2015"
[dumpfile_size] 5636
[savefile] "/home/johne/Desktop/socgen/common/opencores.org/cde/ip/fifo/sim/icarus/default/wave.sav"
[timestart] 270
[size] 1613 999
[pos] 211 19
*-8.000000 1410 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TB.
[treeopen] TB.test.
[treeopen] TB.test.dut.
[treeopen] TB.test.read.
[treeopen] TB.test.write.
[sst_width] 223
[signals_width] 238
[sst_expanded] 1
[sst_vpaned_height] 300
@28
TB.test.reset
TB.test.clk
TB.test.reset
TB.test.push
@22
TB.test.din[7:0]
@28
TB.test.pop
@22
TB.test.dout[7:0]
@28
TB.test.dut.push_pointer[1:0]
TB.test.dut.pop_pointer[1:0]
TB.test.full
TB.test.over_run
TB.test.under_run
@29
TB.test.empty
[pattern_trace] 1
[pattern_trace] 0
/sim/icarus/default/dmp_define
0,0 → 1,7
$dumpfile ("TestBench.vcd");
$dumpvars (0, TB.test);
 
 
 
 
 
/sim/testbenches/xml/cde_fifo_def_tb.xml
0,0 → 1,172
<?xml version="1.0" encoding="utf-8"?>
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>fifo</spirit:name>
<spirit:version>def_tb</spirit:version>
 
 
 
<spirit:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>fifo_def_tb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
</spirit:componentGenerators>
 
 
 
 
 
 
 
<spirit:model>
<spirit:modelParameters>
</spirit:modelParameters>
 
<spirit:views>
 
<spirit:view>
<spirit:name>Params</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="fifo"
spirit:version="def_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
<spirit:view>
<spirit:name>Bfm</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="fifo"
spirit:version="bfm.design"/>
</spirit:view>
 
 
<spirit:view>
<spirit:name>icarus</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="icarus"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
 
 
</spirit:model>
 
 
 
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/fifo_def_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/fifo_def_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
</spirit:component>
/sim/testbenches/xml/cde_fifo_def_lint.xml
0,0 → 1,102
<?xml version="1.0" encoding="utf-8"?>
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>fifo</spirit:name>
<spirit:version>def_lint</spirit:version>
 
 
 
<spirit:componentGenerators>
 
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
 
 
<spirit:views>
 
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="fifo"
spirit:version="def_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
<spirit:view>
<spirit:name>lint</spirit:name>
<spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>rtl_check</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="rtl_check"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
</spirit:views>
 
 
 
</spirit:model>
 
 
 
 
 
 
 
 
<spirit:fileSets>
 
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/lint/fifo_def_lint</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
</spirit:component>
/sim/testbenches/xml/cde_fifo_bfm.design.xml
0,0 → 1,105
<?xml version="1.0" encoding="utf-8"?>
<!--
 
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>fifo</spirit:name>
<spirit:version>bfm.design</spirit:version>
 
 
 
 
 
 
 
 
 
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk"/>
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="clk"/>
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="clk"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset"/>
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="reset"/>
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="reset"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pop</spirit:name>
<spirit:externalPortReference spirit:portRef="pop"/>
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="rd"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>push</spirit:name>
<spirit:externalPortReference spirit:portRef="push"/>
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="wr"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>din</spirit:name>
<spirit:externalPortReference spirit:portRef="din" spirit:left="7" spirit:right="0"/>
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="wdata" />
</spirit:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>dout</spirit:name>
<spirit:externalPortReference spirit:portRef="dout" spirit:left="7" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="rdata" />
</spirit:adHocConnection>
 
 
 
 
 
</spirit:adHocConnections>
 
<spirit:componentInstances>
 
 
 
<spirit:componentInstance>
<spirit:instanceName>write</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="micro_bus_model" spirit:version="def"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="addr_width">8</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
 
 
<spirit:componentInstance>
<spirit:instanceName>read</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="micro_bus_model" spirit:version="def"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="addr_width">8</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
 
 
 
 
 
 
 
</spirit:componentInstances>
 
 
 
 
</spirit:design>
/sim/testbenches/xml/cde_fifo_def_dut.params.xml
0,0 → 1,34
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// //
// //
// //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>fifo</spirit:name>
<spirit:version>def_dut.params</spirit:version>
<spirit:model>
 
<spirit:views>
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="fifo"
spirit:version="def_duth.design"/>
</spirit:view>
</spirit:views>
 
</spirit:model>
</spirit:component>
/sim/testbenches/xml/fifo_def_duth.design.xml
0,0 → 1,95
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library cde -component fifo -version def //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>fifo</spirit:name>
<spirit:version>def_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>din</spirit:name>
<spirit:externalPortReference spirit:portRef="din" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="din" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>dout</spirit:name>
<spirit:externalPortReference spirit:portRef="dout" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dout" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>empty</spirit:name>
<spirit:externalPortReference spirit:portRef="empty" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="empty" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>full</spirit:name>
<spirit:externalPortReference spirit:portRef="full" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="full" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>over_run</spirit:name>
<spirit:externalPortReference spirit:portRef="over_run" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="over_run" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>pop</spirit:name>
<spirit:externalPortReference spirit:portRef="pop" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pop" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>push</spirit:name>
<spirit:externalPortReference spirit:portRef="push" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="push" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>under_run</spirit:name>
<spirit:externalPortReference spirit:portRef="under_run" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="under_run" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="fifo" spirit:version="def" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="SIZE">SIZE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/bin/Makefile
0,0 → 1,3
include ../../../../bin/Makefile.root
 
 

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