URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/cde/ip/jtag/rtl/xml
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/cde_jtag_def.design.xml
File deleted
/cde_jtag_rpc_reg.xml
22,66 → 22,60
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<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_rpc_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:fileSets> |
</spirit:componentGenerators> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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|
</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
181,7 → 175,7
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<spirit:port><spirit:name>update_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
197,9 → 191,96
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |
/cde_jtag_classic_rpc_reg.xml
77,60 → 77,62
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<spirit:componentGenerators> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_classic_rpc_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
</spirit:componentGenerators> |
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</spirit:fileSet> |
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<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:model> |
<spirit:views> |
|
</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
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|
</spirit:fileSets> |
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<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
170,6 → 172,98
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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|
</spirit:fileSet> |
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<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
188,7 → 282,7
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<spirit:port><spirit:name>update_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
209,4 → 303,9
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</spirit:component> |
/cde_jtag_tap.xml
255,44 → 255,22
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<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_tap</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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313,11 → 291,33
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="jtag" |
spirit:version="def.design"/> |
spirit:version="tap.design"/> |
</spirit:view> |
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<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
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<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
359,87 → 359,51
</spirit:views> |
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|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h12345678</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
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</spirit:modelParameters> |
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<spirit:ports> |
<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
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<spirit:port><spirit:name>tap_highz_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tap</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:port><spirit:name>bsr_output_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_tdo_i</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>jtag_clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>update_dr_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_select_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
</spirit:fileSet> |
|
</spirit:ports> |
|
</spirit:model> |
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|
<spirit:fileSets> |
|
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_tap</spirit:name> |
<spirit:name>../verilog/common/jtag_tap</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/sim/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
455,12 → 419,17
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_tap</spirit:name> |
<spirit:name>../verilog/common/jtag_tap</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
467,7 → 436,7
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
480,7 → 449,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
489,15 → 458,76
|
|
|
</spirit:fileSets> |
|
|
|
</spirit:fileSets> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h00000000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
|
|
</spirit:modelParameters> |
|
|
<spirit:ports> |
|
|
|
|
<spirit:port><spirit:name>tap_highz_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_output_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_tdo_i</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>jtag_clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>update_dr_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_select_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/cde_jtag_rpc_in_reg.xml
14,59 → 14,59
<spirit:name>jtag</spirit:name> |
<spirit:version>rpc_in_reg</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:busInterfaces> |
|
|
</spirit:componentGenerators> |
<spirit:busInterface><spirit:name>jtag</spirit:name> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/> |
<spirit:slave/> |
<spirit:portMaps> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>capture_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>shift_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
</spirit:fileSet> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdi</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdo</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdo</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>select</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>select</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
|
</spirit:fileSet> |
|
|
</spirit:portMaps> |
</spirit:busInterface> |
|
<spirit:fileSet> |
</spirit:busInterfaces> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
73,13 → 73,66
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_rpc_in_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
119,6 → 172,99
|
|
|
|
|
<spirit:fileSets> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
126,11 → 272,16
|
<spirit:ports> |
|
|
|
|
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
137,33 → 288,11
</spirit:port> |
|
|
<spirit:port><spirit:name>tdi</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>select</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>capture_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>shift_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>tdo</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>capture_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
175,6 → 304,7
|
|
|
|
</spirit:ports> |
|
</spirit:model> |
/cde_jtag_classic_rpc_in_reg.xml
14,59 → 14,71
<spirit:name>jtag</spirit:name> |
<spirit:version>classic_rpc_in_reg</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
<spirit:componentGenerators> |
|
|
|
|
|
<spirit:busInterfaces> |
|
</spirit:componentGenerators> |
|
<spirit:busInterface><spirit:name>jtag</spirit:name> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/> |
<spirit:slave/> |
<spirit:portMaps> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>test_logic_reset</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>test_logic_reset</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSets> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>capture_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>shift_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>update_dr_clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>update_dr_clk</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
</spirit:fileSet> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdi</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdo</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdo</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>select</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>select</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>shiftcapture_dr_clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>shiftcapture_dr_clk</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
</spirit:portMaps> |
</spirit:busInterface> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
</spirit:busInterfaces> |
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
74,10 → 86,71
|
|
|
|
|
|
|
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_classic_rpc_in_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
118,51 → 191,110
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
<spirit:fileSets> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>shiftcapture_dr_clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>test_logic_reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/classic_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:port><spirit:name>tdi</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>select</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:port><spirit:name>capture_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>shift_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:fileSet> |
|
<spirit:port><spirit:name>tdo</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
<spirit:port><spirit:name>capture_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
/cde_jtag_sync.xml
122,14 → 122,63
</spirit:busInterfaces> |
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_sync</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
|
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
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|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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|
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|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
196,7 → 245,29
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
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|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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|
|
</spirit:fileSet> |
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|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
/cde_jtag_tap.design.xml
0,0 → 1,287
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
|
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>jtag</spirit:name> |
<spirit:version>tap.design</spirit:version> |
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|
<spirit:vendorExtensions><socgen:nodes> |
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|
<socgen:node><spirit:name>tclk</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>tclk_n</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>tap_state</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>next_tap_state</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>shift_ir</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>update_ir</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>capture_ir</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
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|
<socgen:node><spirit:name>next_tdo</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>bypass_tdo</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>chip_id_tdo</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>chip_id_select</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>bypass_select</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>extest</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>sample</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>clamp</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>bsr_output_mode</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>shiftcapture_dr</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>aux_update_dr_o</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
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|
<socgen:node><spirit:name>aux_jtag_clk</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
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|
</socgen:nodes></spirit:vendorExtensions> |
|
|
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>jtag_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_clk"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>trst_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="trst_pad_in"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="reset"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdi_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="JTAG_INT_JTAG_TDI_PAD_IN"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="tdi"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>chip_id_select</spirit:name> |
<spirit:externalPortReference spirit:portRef="chip_id_select"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="select"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>chip_id_tdo</spirit:name> |
<spirit:externalPortReference spirit:portRef="chip_id_tdo"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="tdo"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>capture_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_capture_dr"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="capture_dr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>shift_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_shift_dr"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="shift_dr"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>tclk</spirit:name> |
<spirit:externalPortReference spirit:portRef="tclk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="clk_in"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="clk_in"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="clk_in"/> |
</spirit:adHocConnection> |
|
|
|
|
|
<spirit:adHocConnection> |
<spirit:name>jtag_shift_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_shift_clk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="clk_out"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>update_dr_clk_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_update_dr_clk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="clk_out"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>jtag_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_clk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="clk_out"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>shiftcapture_dr</spirit:name> |
<spirit:externalPortReference spirit:portRef="shiftcapture_dr"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="enable"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>update_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="update_dr_o"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="enable"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>chip_id_value</spirit:name> |
<spirit:externalPortReference spirit:portRef="chip_id_value" spirit:left="31" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="capture_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection spirit:tiedValue="1'b1" > |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="enable"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection spirit:tiedValue="1'b0" > |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="atg_clk_mode"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="atg_clk_mode"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="atg_clk_mode"/> |
</spirit:adHocConnection> |
|
|
|
|
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>clk_gater_jtag_shift_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" /> |
</spirit:componentInstance> |
|
<spirit:componentInstance> |
<spirit:instanceName>clk_gater_jtag_update_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" /> |
</spirit:componentInstance> |
|
<spirit:componentInstance> |
<spirit:instanceName>clk_gater_jtag_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" /> |
</spirit:componentInstance> |
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>chip_id_reg</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_in_reg" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="BITS">32</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RESET_VALUE">CHIP_ID_VAL</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
</spirit:componentInstances> |
|
|
|
|
|
</spirit:design> |
/cde_jtag_classic_sync.xml
137,12 → 137,62
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_classic_sync</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
193,6 → 243,39
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_shift_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_capture_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_update_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>syn_tdi_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>syn_select</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
207,12 → 290,43
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/classic_sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
223,9 → 337,28
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
240,7 → 373,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |