OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/cde/ip/jtag
    from Rev 133 to Rev 134
    ↔ Reverse comparison
  •

Rev 133 → Rev 134

/componentCfg.xml
34,6 → 34,8
 
<socgen:configuration>
<socgen:name>default</socgen:name>
<socgen:version>tap</socgen:version>
<socgen:version>tap_lint</socgen:version>
<socgen:parameters>
<socgen:parameter><socgen:name>INST_LENGTH</socgen:name><socgen:value>4</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>INST_RETURN</socgen:name><socgen:value>4'b1101</socgen:value></socgen:parameter>
69,11 → 71,33
 
 
 
<socgen:configuration>
<socgen:name>reg</socgen:name>
<socgen:version>classic_rpc_reg</socgen:version>
<socgen:version>classic_rpc_in_reg</socgen:version>
<socgen:parameters>
<socgen:parameter><socgen:name>BITS</socgen:name><socgen:value>16</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>RESET_VALUE</socgen:name><socgen:value>16'h0000</socgen:value></socgen:parameter>
</socgen:parameters>
 
</socgen:configuration>
 
 
 
</socgen:configurations>
 
 
 
 
 
 
 
 
 
 
 
 
 
<socgen:sim>
 
<socgen:comp_path>jtag/sim</socgen:comp_path>
116,14 → 140,8
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>100000</socgen:value></socgen:parameter>
</socgen:parameters>
<socgen:code_coverage>
<socgen:cover>
<socgen:name>cde_jtag_tap</socgen:name><socgen:componentInstance>TB.test.dut</socgen:componentInstance>
</socgen:cover>
</socgen:code_coverage>
<socgen:tools>
<socgen:tool>icarus</socgen:tool>
<socgen:tool>coverage</socgen:tool>
</socgen:tools>
</socgen:testbench>
 
136,22 → 154,13
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter>
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>100000</socgen:value></socgen:parameter>
</socgen:parameters>
<socgen:code_coverage>
<socgen:cover>
<socgen:name>cde_jtag_tap</socgen:name><socgen:componentInstance>TB.test.dut</socgen:componentInstance>
</socgen:cover>
</socgen:code_coverage>
<socgen:tools>
<socgen:tool>icarus</socgen:tool>
<socgen:tool>coverage</socgen:tool>
</socgen:tools>
</socgen:testbench>
 
 
 
 
 
 
<socgen:testbench>
<socgen:variant>jtag_tap_lint</socgen:variant>
<socgen:version>tap_lint</socgen:version>
/rtl/xml/cde_jtag_def.design.xml File deleted
/rtl/xml/cde_jtag_rpc_reg.xml
22,66 → 22,60
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_rpc_reg</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
</spirit:componentGenerators>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:model>
<spirit:views>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
181,7 → 175,7
 
 
<spirit:port><spirit:name>update_value</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
197,9 → 191,96
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/jtag_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
 
 
 
</spirit:component>
/rtl/xml/cde_jtag_classic_rpc_reg.xml
77,60 → 77,62
 
 
 
<spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_classic_rpc_reg</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:componentGenerators>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:model>
<spirit:views>
 
</spirit:fileSet>
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
</spirit:fileSets>
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
<spirit:model>
<spirit:views>
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
170,6 → 172,98
 
 
 
 
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/classic_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter>
188,7 → 282,7
 
 
<spirit:port><spirit:name>update_value</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
209,4 → 303,9
 
 
 
 
 
 
 
 
</spirit:component>
/rtl/xml/cde_jtag_tap.xml
255,44 → 255,22
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_tap</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:parameters>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
</spirit:componentGenerators>
 
 
313,11 → 291,33
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="jtag"
spirit:version="def.design"/>
spirit:version="tap.design"/>
</spirit:view>
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
359,87 → 359,51
</spirit:views>
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h12345678</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
 
 
</spirit:modelParameters>
 
 
<spirit:ports>
<spirit:fileSets>
 
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:port><spirit:name>tap_highz_mode</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tap</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
<spirit:port><spirit:name>bsr_output_mode</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>bsr_tdo_i</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>jtag_clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>update_dr_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>bsr_select_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
</spirit:fileSet>
 
</spirit:ports>
 
</spirit:model>
 
 
 
 
 
<spirit:fileSets>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/jtag_tap</spirit:name>
<spirit:name>../verilog/common/jtag_tap</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/sim/</spirit:name>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
455,12 → 419,17
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/jtag_tap</spirit:name>
<spirit:name>../verilog/common/jtag_tap</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
467,7 → 436,7
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/syn/</spirit:name>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
480,7 → 449,7
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/syn/</spirit:name>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
489,15 → 458,76
 
 
 
</spirit:fileSets>
 
 
 
</spirit:fileSets>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h00000000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
 
 
</spirit:modelParameters>
 
 
<spirit:ports>
 
 
 
 
<spirit:port><spirit:name>tap_highz_mode</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>bsr_output_mode</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>bsr_tdo_i</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>jtag_clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>update_dr_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>bsr_select_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
</spirit:ports>
 
</spirit:model>
 
 
 
 
 
 
 
 
 
 
</spirit:component>
/rtl/xml/cde_jtag_rpc_in_reg.xml
14,59 → 14,59
<spirit:name>jtag</spirit:name>
<spirit:version>rpc_in_reg</spirit:version> <spirit:configuration>default</spirit:configuration>
 
<spirit:componentGenerators>
 
 
 
 
<spirit:busInterfaces>
 
 
</spirit:componentGenerators>
<spirit:busInterface><spirit:name>jtag</spirit:name>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/>
<spirit:slave/>
<spirit:portMaps>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:portMap>
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>capture_dr</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:portMap>
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>shift_dr</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
</spirit:fileSet>
 
<spirit:portMap>
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdi</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:portMap>
<spirit:logicalPort><spirit:name>tdo</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdo</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:portMap>
<spirit:logicalPort><spirit:name>select</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>select</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
 
 
</spirit:fileSet>
 
 
</spirit:portMaps>
</spirit:busInterface>
 
<spirit:fileSet>
</spirit:busInterfaces>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
73,13 → 73,66
 
 
 
<spirit:componentGenerators>
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_rpc_in_reg</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
 
 
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
119,6 → 172,99
 
 
 
 
 
<spirit:fileSets>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/jtag_rpc_in_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_rpc_in_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_rpc_in_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter>
126,11 → 272,16
 
<spirit:ports>
 
 
 
 
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
137,33 → 288,11
</spirit:port>
 
 
<spirit:port><spirit:name>tdi</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>select</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>capture_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>shift_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>tdo</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>capture_value</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
175,6 → 304,7
 
 
 
 
</spirit:ports>
 
</spirit:model>
/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
14,59 → 14,71
<spirit:name>jtag</spirit:name>
<spirit:version>classic_rpc_in_reg</spirit:version> <spirit:configuration>default</spirit:configuration>
 
<spirit:componentGenerators>
 
 
 
 
 
<spirit:busInterfaces>
 
</spirit:componentGenerators>
 
<spirit:busInterface><spirit:name>jtag</spirit:name>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/>
<spirit:slave/>
<spirit:portMaps>
 
<spirit:portMap>
<spirit:logicalPort><spirit:name>test_logic_reset</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>test_logic_reset</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:fileSets>
<spirit:portMap>
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>capture_dr</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:portMap>
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>shift_dr</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:portMap>
<spirit:logicalPort><spirit:name>update_dr_clk</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>update_dr_clk</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
</spirit:fileSet>
 
<spirit:portMap>
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdi</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:portMap>
<spirit:logicalPort><spirit:name>tdo</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdo</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<spirit:portMap>
<spirit:logicalPort><spirit:name>select</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>select</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
 
<spirit:portMap>
<spirit:logicalPort><spirit:name>shiftcapture_dr_clk</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>shiftcapture_dr_clk</spirit:name></spirit:physicalPort>
</spirit:portMap>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
</spirit:portMaps>
</spirit:busInterface>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:busInterfaces>
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
74,10 → 86,71
 
 
 
 
 
 
 
 
 
 
<spirit:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_classic_rpc_in_reg</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
</spirit:componentGenerators>
 
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
118,51 → 191,110
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
<spirit:fileSets>
 
<spirit:ports>
 
<spirit:port><spirit:name>shiftcapture_dr_clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>test_logic_reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/classic_rpc_in_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
<spirit:port><spirit:name>tdi</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>select</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<spirit:port><spirit:name>capture_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>shift_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
</spirit:fileSet>
 
<spirit:port><spirit:name>tdo</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_rpc_in_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_rpc_in_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
 
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
 
 
<spirit:port><spirit:name>capture_value</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
/rtl/xml/cde_jtag_sync.xml
122,14 → 122,63
</spirit:busInterfaces>
 
 
<spirit:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_sync</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
<spirit:views>
 
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
196,7 → 245,29
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sync</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
/rtl/xml/cde_jtag_tap.design.xml
0,0 → 1,287
<?xml version="1.0" encoding="UTF-8"?>
<!--
 
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>jtag</spirit:name>
<spirit:version>tap.design</spirit:version>
 
 
<spirit:vendorExtensions><socgen:nodes>
 
 
<socgen:node><spirit:name>tclk</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
<socgen:node><spirit:name>tclk_n</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>tap_state</spirit:name>
<spirit:typeName>reg</spirit:typeName>
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>
 
 
<socgen:node><spirit:name>next_tap_state</spirit:name>
<spirit:typeName>reg</spirit:typeName>
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>
 
 
<socgen:node><spirit:name>shift_ir</spirit:name>
<spirit:typeName>reg</spirit:typeName>
 
</socgen:node>
 
<socgen:node><spirit:name>update_ir</spirit:name>
<spirit:typeName>reg</spirit:typeName>
 
</socgen:node>
 
<socgen:node><spirit:name>capture_ir</spirit:name>
<spirit:typeName>reg</spirit:typeName>
 
</socgen:node>
 
 
 
<socgen:node><spirit:name>next_tdo</spirit:name>
<spirit:typeName>reg</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>bypass_tdo</spirit:name>
<spirit:typeName>reg</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>chip_id_tdo</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
<socgen:node><spirit:name>chip_id_select</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
<socgen:node><spirit:name>bypass_select</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>extest</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>sample</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>clamp</spirit:name>
<spirit:typeName>wire</spirit:typeName>
 
</socgen:node>
 
 
<socgen:node><spirit:name>bsr_output_mode</spirit:name>
<spirit:typeName>reg</spirit:typeName>
</socgen:node>
 
 
<socgen:node><spirit:name>shiftcapture_dr</spirit:name>
<spirit:typeName>wire</spirit:typeName>
</socgen:node>
 
 
<socgen:node><spirit:name>aux_update_dr_o</spirit:name>
<spirit:typeName>wire</spirit:typeName>
</socgen:node>
 
 
<socgen:node><spirit:name>aux_jtag_clk</spirit:name>
<spirit:typeName>wire</spirit:typeName>
</socgen:node>
 
 
 
 
 
</socgen:nodes></spirit:vendorExtensions>
 
 
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>jtag_clk</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_clk"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="clk"/>
</spirit:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>trst_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="trst_pad_in"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="reset"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tdi_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="JTAG_INT_JTAG_TDI_PAD_IN"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="tdi"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>chip_id_select</spirit:name>
<spirit:externalPortReference spirit:portRef="chip_id_select"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="select"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>chip_id_tdo</spirit:name>
<spirit:externalPortReference spirit:portRef="chip_id_tdo"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="tdo"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>capture_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_capture_dr"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="capture_dr"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>shift_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_shift_dr"/>
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="shift_dr"/>
</spirit:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>tclk</spirit:name>
<spirit:externalPortReference spirit:portRef="tclk"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="clk_in"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="clk_in"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="clk_in"/>
</spirit:adHocConnection>
 
 
 
 
 
<spirit:adHocConnection>
<spirit:name>jtag_shift_clk</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_shift_clk"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="clk_out"/>
</spirit:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>update_dr_clk_o</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_update_dr_clk"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="clk_out"/>
</spirit:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>jtag_clk</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_clk"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="clk_out"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>shiftcapture_dr</spirit:name>
<spirit:externalPortReference spirit:portRef="shiftcapture_dr"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="enable"/>
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>update_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="update_dr_o"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="enable"/>
</spirit:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>chip_id_value</spirit:name>
<spirit:externalPortReference spirit:portRef="chip_id_value" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="capture_value"/>
</spirit:adHocConnection>
 
 
<spirit:adHocConnection spirit:tiedValue="1'b1" >
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="enable"/>
</spirit:adHocConnection>
 
 
 
<spirit:adHocConnection spirit:tiedValue="1'b0" >
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="atg_clk_mode"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="atg_clk_mode"/>
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="atg_clk_mode"/>
</spirit:adHocConnection>
 
 
 
 
 
 
 
</spirit:adHocConnections>
 
 
 
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>clk_gater_jtag_shift_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" />
</spirit:componentInstance>
 
<spirit:componentInstance>
<spirit:instanceName>clk_gater_jtag_update_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" />
</spirit:componentInstance>
 
<spirit:componentInstance>
<spirit:instanceName>clk_gater_jtag_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" />
</spirit:componentInstance>
 
 
 
<spirit:componentInstance>
<spirit:instanceName>chip_id_reg</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_in_reg" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BITS">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RESET_VALUE">CHIP_ID_VAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
 
 
 
 
</spirit:componentInstances>
 
 
 
 
 
</spirit:design>
/rtl/xml/cde_jtag_classic_sync.xml
137,12 → 137,62
 
 
 
<spirit:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>jtag_classic_sync</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
 
</spirit:componentGenerators>
 
 
 
 
<spirit:model>
<spirit:views>
 
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
193,6 → 243,39
</spirit:port>
 
 
<spirit:port><spirit:name>syn_reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>syn_shift_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>syn_capture_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>syn_update_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>syn_tdi_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>syn_select</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
</spirit:ports>
 
</spirit:model>
207,12 → 290,43
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/classic_sync</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_sync</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
223,9 → 337,28
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/jtag_classic_sync</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
 
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
240,7 → 373,7
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
/rtl/verilog/classic_rpc_reg
0,0 → 1,26
 
// shift buffer and shadow
reg [BITS-1:0] buffer;
 
always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)
if (test_logic_reset) buffer <= RESET_VALUE;
else
if (select && capture_dr) buffer <= capture_value;
else
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };
else buffer <= buffer;
 
 
always @(posedge update_dr_clk or posedge test_logic_reset)
if (test_logic_reset) update_value <= RESET_VALUE;
else
if (select) update_value <= buffer;
else update_value <= update_value;
 
 
 
assign tdo = buffer[0];
 
 
/rtl/verilog/tap
0,0 → 1,286
//********************************************************************
//*** assignments for 2nd channel
//********************************************************************
 
 
assign aux_jtag_clk = jtag_clk;
assign aux_update_dr_clk_o = update_dr_clk_o;
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o;
assign aux_test_logic_reset_o = test_logic_reset_o;
assign aux_tdi_o = tdi_o;
assign aux_capture_dr_o = capture_dr_o;
assign aux_shift_dr_o = shift_dr_o;
assign aux_update_dr_o = update_dr_o;
 
assign chip_id_value = CHIP_ID_VAL ;
 
//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
 
// TAP state parameters
localparam TEST_LOGIC_RESET = 4'b1111,
RUN_TEST_IDLE = 4'b1100,
SELECT_DR_SCAN = 4'b0111,
CAPTURE_DR = 4'b0110,
SHIFT_DR = 4'b0010,
EXIT1_DR = 4'b0001,
PAUSE_DR = 4'b0011,
EXIT2_DR = 4'b0000,
UPDATE_DR = 4'b0101,
SELECT_IR_SCAN = 4'b0100,
CAPTURE_IR = 4'b1110,
SHIFT_IR = 4'b1010,
EXIT1_IR = 4'b1001,
PAUSE_IR = 4'b1011,
EXIT2_IR = 4'b1000,
UPDATE_IR = 4'b1101;
 
 
 
// next state decode for tap controller
always @(*)
case (tap_state) // synopsys parallel_case
TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR;
CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR;
PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR;
EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR;
UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR;
CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR;
PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR;
EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR;
UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
endcase
 
 
//********************************************************************
//*** TAP Controller State Machine Register
//********************************************************************
 
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET;
else tap_state <= next_tap_state;
 
 
// Decode tap_state to get Shift, Update, and Capture signals
 
 
 
always @(*)
begin
shift_ir = (tap_state == SHIFT_IR);
shift_dr_o = (tap_state == SHIFT_DR);
update_ir = (tap_state == UPDATE_IR);
update_dr_o = (tap_state == UPDATE_DR);
capture_dr_o = (tap_state == CAPTURE_DR);
capture_ir = (tap_state == CAPTURE_IR);
end
 
 
// Decode tap_state to get test_logic_reset signal
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) test_logic_reset_o <= 1'b1;
else
if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1;
else test_logic_reset_o <= 1'b0;
 
//******************************************************
//*** Instruction Register
//******************************************************
 
reg [INST_LENGTH-1:0] instruction_buffer;
reg [INST_LENGTH-1:0] instruction;
 
// buffer the instruction register while shifting
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) instruction_buffer <= INST_RESET;
else
if (capture_ir) instruction_buffer <= INST_RETURN;
else
if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]};
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) instruction <= INST_RESET;
else
if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET;
else
if (update_ir) instruction <= instruction_buffer;
 
 
 
 
 
 
assign tclk = tclk_pad_in;
assign tclk_n = !tclk_pad_in;
assign shiftcapture_dr = shift_dr_o || capture_dr_o;
assign tdi_o = tdi_pad_in;
assign trst_pad_in = !trst_n_pad_in;
 
// Instruction Decoder
assign extest = ( instruction == EXTEST );
assign sample = ( instruction == SAMPLE );
assign clamp = ( instruction == CLAMP );
assign chip_id_select = ( instruction == CHIP_ID_ACCESS );
 
// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode
 
assign bypass_select = ( instruction == CLAMP ) || ( instruction == BYPASS );
 
assign shiftcapture_dr_clk_o = jtag_shift_clk;
assign select_o = ( instruction == RPC_ADD );
assign aux_select_o = ( instruction == RPC_DATA );
assign bsr_select_o = ( instruction == EXTEST ) || ( instruction == SAMPLE ) ;
 
 
 
 
//**********************************************************
//** Boundary scan control signals
//**********************************************************
 
 
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) bsr_output_mode <= 1'b0;
else
if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0;
else
if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST)
|| (instruction_buffer == CLAMP);
 
// Control chip pads when we are in highz_mode
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) tap_highz_mode <= 1'b0;
else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0;
else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE);
 
 
 
 
 
//**********************************************************
//*** Bypass register
//**********************************************************
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) bypass_tdo <= 1'b0;
else
if (capture_dr_o) bypass_tdo <= 1'b0;
else
if (shift_dr_o) bypass_tdo <= tdi_pad_in;
else bypass_tdo <= bypass_tdo;
 
 
//****************************************************************
//*** Choose what goes out on the TDO pin
//****************************************************************
 
// output the instruction register when tap_state[3] is 1, else
// put out the appropriate data register.
 
 
always@(*)
begin
if( tap_state[3] ) next_tdo = instruction_buffer[0];
else
if(bypass_select) next_tdo = bypass_tdo;
else
if(chip_id_select) next_tdo = chip_id_tdo;
else
if(select_o) next_tdo = tdo_i;
else
if(aux_select_o) next_tdo = aux_tdo_i;
else next_tdo = 1'b0;
end
 
reg tdo_pad_out_reg;
reg tdo_pad_oe_reg;
 
always @(posedge tclk_n or negedge trst_n_pad_in)
if (!trst_n_pad_in) tdo_pad_out_reg <= 1'b0;
else tdo_pad_out_reg <= next_tdo;
 
 
// output enable for TDO pad
 
always @(posedge tclk_n or negedge trst_n_pad_in)
if ( !trst_n_pad_in ) tdo_pad_oe_reg <= 1'b0;
else tdo_pad_oe_reg <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) );
 
 
 
assign tdo_pad_out = tdo_pad_out_reg;
assign tdo_pad_oe = tdo_pad_oe_reg;
 
`ifndef SYNTHESYS
 
reg [8*16-1:0] tap_string;
 
always @(tap_state) begin
case (tap_state)
TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET";
RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE";
SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN";
CAPTURE_DR: tap_string = "CAPTURE_DR";
SHIFT_DR: tap_string = "SHIFT_DR";
EXIT1_DR: tap_string = "EXIT1_DR";
PAUSE_DR: tap_string = "PAUSE_DR";
EXIT2_DR: tap_string = "EXIT2_DR";
UPDATE_DR: tap_string = "UPDATE_DR";
SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN";
CAPTURE_IR: tap_string = "CAPTURE_IR";
SHIFT_IR: tap_string = "SHIFT_IR";
EXIT1_IR: tap_string = "EXIT1_IR";
PAUSE_IR: tap_string = "PAUSE_IR";
EXIT2_IR: tap_string = "EXIT2_IR";
UPDATE_IR: tap_string = "UPDATE_IR";
default: tap_string = "-XXXXXX-";
endcase
 
$display("%t %m Tap State = %s",$realtime, tap_string);
end
 
 
 
reg [8*16-1:0] inst_string;
 
always @(instruction) begin
case (instruction)
EXTEST: inst_string = "EXTEST";
SAMPLE: inst_string = "SAMPLE";
HIGHZ_MODE: inst_string = "HIGHZ_MODE";
CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS";
CLAMP: inst_string = "CLAMP";
RPC_DATA: inst_string = "RPC_DATA";
RPC_ADD: inst_string = "RPC_ADD";
BYPASS: inst_string = "BYPASS";
default: inst_string = "-XXXXXX-";
endcase
 
$display("%t %m Instruction = %s",$realtime, inst_string);
end
`endif
 
/rtl/verilog/jtag_rpc_reg
0,0 → 1,25
 
// shift buffer and shadow
reg [BITS-1:0] buffer;
 
always @(posedge clk or posedge reset)
if (reset) buffer <= RESET_VALUE;
else
if (select && capture_dr) buffer <= capture_value;
else
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };
else buffer <= buffer;
 
 
always @(posedge update_dr or posedge reset)
if (reset) update_value <= RESET_VALUE;
else
if (select) update_value <= buffer;
else update_value <= update_value;
 
 
 
assign tdo = buffer[0];
 
/rtl/verilog/jtag_tap
24,76 → 24,56
 
cde_jtag_tap
#( parameter
BYPASS=4'b1111,
CHIP_ID_ACCESS=4'b0011,
CHIP_ID_VAL=32'h12345678,
CLAMP=4'b1000,
EXTEST=4'b0000,
HIGHZ_MODE=4'b0010,
INST_LENGTH=4,
INST_RESET=4'b1111,
INST_RETURN=4'b1101,
INST_RESET=4'b1111,
NUM_USER=2,
USER=8'b1010_1001,
EXTEST=4'b0000,
RPC_ADD=4'b1001,
RPC_DATA=4'b1010,
SAMPLE=4'b0001,
HIGHZ_MODE=4'b0010,
CHIP_ID_ACCESS=4'b0011,
CLAMP=4'b1000,
RPC_DATA=4'b1010,
RPC_ADD=4'b1001,
BYPASS=4'b1111,
CHIP_ID_VAL=32'h12345678)
USER=8'b1010_1001)
 
(
input wire aux_tdo_i,
input wire bsr_tdo_i,
input wire tclk_pad_in,
input wire tdi_pad_in,
input wire tdo_i,
input wire tms_pad_in,
input wire trst_n_pad_in,
output wire tdo_pad_oe,
output wire tdo_pad_out,
 
output wire jtag_clk,
output wire update_dr_clk_o,
output wire shiftcapture_dr_clk_o,
 
 
output wire aux_jtag_clk,
output wire aux_update_dr_clk_o,
output wire aux_shiftcapture_dr_clk_o,
 
 
 
 
output reg test_logic_reset_o,
 
output wire aux_test_logic_reset_o,
 
 
output wire tdi_o,
 
output wire aux_tdi_o,
 
 
 
input wire tdo_i,
input wire aux_tdo_i,
input wire bsr_tdo_i,
 
 
 
output reg bsr_output_mode,
output reg capture_dr_o,
output reg shift_dr_o,
output reg tap_highz_mode,
output reg test_logic_reset_o,
output reg update_dr_o,
 
 
output wire aux_capture_dr_o,
output wire aux_select_o,
output wire aux_shift_dr_o,
output wire aux_update_dr_o,
 
 
output reg tap_highz_mode,
output reg bsr_output_mode,
 
output wire aux_shiftcapture_dr_clk_o,
output wire aux_tdi_o,
output wire aux_test_logic_reset_o,
output wire aux_update_dr_clk_o,
output wire tdi_o,
output wire select_o,
output wire aux_select_o,
 
output wire bsr_select_o
output wire tdo_pad_oe,
output wire tdo_pad_out,
output wire jtag_clk,
output wire update_dr_clk_o,
output wire shiftcapture_dr_clk_o,
output wire bsr_select_o
);
 
 
113,21 → 93,14
wire clamp;
wire extest;
wire sample;
wire shift_capture_dr;
wire tclk;
wire tclk_n;
wire trst_pad_in;
wire jtag_shift_clk;
wire aux_update_dr_o;
wire aux_jtag_clk;
 
 
assign aux_jtag_clk = jtag_clk;
assign aux_update_dr_clk_o = update_dr_clk_o;
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o;
assign aux_test_logic_reset_o = test_logic_reset_o;
assign aux_tdi_o = tdi_o;
assign aux_capture_dr_o = capture_dr_o;
assign aux_shift_dr_o = shift_dr_o;
assign aux_update_dr_o = update_dr_o;
 
////////////////////////////////////////////////////////////////
cde_clock_gater
136,7 → 109,7
.atg_clk_mode (1'b0),
.clk_in (tclk),
.clk_out (jtag_shift_clk),
.enable (shift_capture_dr));
.enable (shiftcapture_dr));
 
cde_clock_gater
clk_gater_jtag_update_clk
173,7 → 146,30
.tdi (tdi_pad_in),
.tdo (chip_id_tdo));
 
 
 
 
 
 
 
 
//********************************************************************
//*** assignments for 2nd channel
//********************************************************************
 
 
assign aux_jtag_clk = jtag_clk;
assign aux_update_dr_clk_o = update_dr_clk_o;
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o;
assign aux_test_logic_reset_o = test_logic_reset_o;
assign aux_tdi_o = tdi_o;
assign aux_capture_dr_o = capture_dr_o;
assign aux_shift_dr_o = shift_dr_o;
assign aux_update_dr_o = update_dr_o;
 
 
 
//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
284,7 → 280,7
 
assign tclk = tclk_pad_in;
assign tclk_n = !tclk_pad_in;
assign shift_capture_dr = shift_dr_o || capture_dr_o;
assign shiftcapture_dr = shift_dr_o || capture_dr_o;
assign tdi_o = tdi_pad_in;
assign trst_pad_in = !trst_n_pad_in;
 
/rtl/verilog/top
0,0 → 1,286
//********************************************************************
//*** assignments for 2nd channel
//********************************************************************
 
 
assign aux_jtag_clk = jtag_clk;
assign aux_update_dr_clk_o = update_dr_clk_o;
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o;
assign aux_test_logic_reset_o = test_logic_reset_o;
assign aux_tdi_o = tdi_o;
assign aux_capture_dr_o = capture_dr_o;
assign aux_shift_dr_o = shift_dr_o;
assign aux_update_dr_o = update_dr_o;
 
 
 
//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
 
// TAP state parameters
localparam TEST_LOGIC_RESET = 4'b1111,
RUN_TEST_IDLE = 4'b1100,
SELECT_DR_SCAN = 4'b0111,
CAPTURE_DR = 4'b0110,
SHIFT_DR = 4'b0010,
EXIT1_DR = 4'b0001,
PAUSE_DR = 4'b0011,
EXIT2_DR = 4'b0000,
UPDATE_DR = 4'b0101,
SELECT_IR_SCAN = 4'b0100,
CAPTURE_IR = 4'b1110,
SHIFT_IR = 4'b1010,
EXIT1_IR = 4'b1001,
PAUSE_IR = 4'b1011,
EXIT2_IR = 4'b1000,
UPDATE_IR = 4'b1101;
 
 
 
// next state decode for tap controller
always @(*)
case (tap_state) // synopsys parallel_case
TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR;
CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR;
PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR;
EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR;
UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR;
CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR;
PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR;
EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR;
UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
endcase
 
 
//********************************************************************
//*** TAP Controller State Machine Register
//********************************************************************
 
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET;
else tap_state <= next_tap_state;
 
 
// Decode tap_state to get Shift, Update, and Capture signals
 
 
 
always @(*)
begin
shift_ir = (tap_state == SHIFT_IR);
shift_dr_o = (tap_state == SHIFT_DR);
update_ir = (tap_state == UPDATE_IR);
update_dr_o = (tap_state == UPDATE_DR);
capture_dr_o = (tap_state == CAPTURE_DR);
capture_ir = (tap_state == CAPTURE_IR);
end
 
 
// Decode tap_state to get test_logic_reset signal
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) test_logic_reset_o <= 1'b1;
else
if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1;
else test_logic_reset_o <= 1'b0;
 
//******************************************************
//*** Instruction Register
//******************************************************
 
reg [INST_LENGTH-1:0] instruction_buffer;
reg [INST_LENGTH-1:0] instruction;
 
// buffer the instruction register while shifting
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) instruction_buffer <= INST_RESET;
else
if (capture_ir) instruction_buffer <= INST_RETURN;
else
if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]};
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) instruction <= INST_RESET;
else
if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET;
else
if (update_ir) instruction <= instruction_buffer;
 
 
 
 
 
 
assign tclk = tclk_pad_in;
assign tclk_n = !tclk_pad_in;
assign shift_capture_dr = shift_dr_o || capture_dr_o;
assign tdi_o = tdi_pad_in;
assign trst_pad_in = !trst_n_pad_in;
 
// Instruction Decoder
assign extest = ( instruction == EXTEST );
assign sample = ( instruction == SAMPLE );
assign clamp = ( instruction == CLAMP );
assign chip_id_select = ( instruction == CHIP_ID_ACCESS );
 
// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode
 
assign bypass_select = ( instruction == CLAMP ) || ( instruction == BYPASS );
 
assign shiftcapture_dr_clk_o = jtag_shift_clk;
assign select_o = ( instruction == RPC_ADD );
assign aux_select_o = ( instruction == RPC_DATA );
assign bsr_select_o = ( instruction == EXTEST ) || ( instruction == SAMPLE ) ;
 
 
 
 
//**********************************************************
//** Boundary scan control signals
//**********************************************************
 
 
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) bsr_output_mode <= 1'b0;
else
if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0;
else
if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST)
|| (instruction_buffer == CLAMP);
 
// Control chip pads when we are in highz_mode
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) tap_highz_mode <= 1'b0;
else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0;
else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE);
 
 
 
 
 
//**********************************************************
//*** Bypass register
//**********************************************************
 
always @(posedge jtag_clk or negedge trst_n_pad_in)
if (!trst_n_pad_in) bypass_tdo <= 1'b0;
else
if (capture_dr_o) bypass_tdo <= 1'b0;
else
if (shift_dr_o) bypass_tdo <= tdi_pad_in;
else bypass_tdo <= bypass_tdo;
 
 
//****************************************************************
//*** Choose what goes out on the TDO pin
//****************************************************************
 
// output the instruction register when tap_state[3] is 1, else
// put out the appropriate data register.
 
 
always@(*)
begin
if( tap_state[3] ) next_tdo = instruction_buffer[0];
else
if(bypass_select) next_tdo = bypass_tdo;
else
if(chip_id_select) next_tdo = chip_id_tdo;
else
if(select_o) next_tdo = tdo_i;
else
if(aux_select_o) next_tdo = aux_tdo_i;
else next_tdo = 1'b0;
end
 
reg tdo_pad_out_reg;
reg tdo_pad_oe_reg;
 
always @(posedge tclk_n or negedge trst_n_pad_in)
if (!trst_n_pad_in) tdo_pad_out_reg <= 1'b0;
else tdo_pad_out_reg <= next_tdo;
 
 
// output enable for TDO pad
 
always @(posedge tclk_n or negedge trst_n_pad_in)
if ( !trst_n_pad_in ) tdo_pad_oe_reg <= 1'b0;
else tdo_pad_oe_reg <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) );
 
 
 
assign tdo_pad_out = tdo_pad_out_reg;
assign tdo_pad_oe = tdo_pad_oe_reg;
 
`ifndef SYNTHESYS
 
reg [8*16-1:0] tap_string;
 
always @(tap_state) begin
case (tap_state)
TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET";
RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE";
SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN";
CAPTURE_DR: tap_string = "CAPTURE_DR";
SHIFT_DR: tap_string = "SHIFT_DR";
EXIT1_DR: tap_string = "EXIT1_DR";
PAUSE_DR: tap_string = "PAUSE_DR";
EXIT2_DR: tap_string = "EXIT2_DR";
UPDATE_DR: tap_string = "UPDATE_DR";
SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN";
CAPTURE_IR: tap_string = "CAPTURE_IR";
SHIFT_IR: tap_string = "SHIFT_IR";
EXIT1_IR: tap_string = "EXIT1_IR";
PAUSE_IR: tap_string = "PAUSE_IR";
EXIT2_IR: tap_string = "EXIT2_IR";
UPDATE_IR: tap_string = "UPDATE_IR";
default: tap_string = "-XXXXXX-";
endcase
 
$display("%t %m Tap State = %s",$realtime, tap_string);
end
 
 
 
reg [8*16-1:0] inst_string;
 
always @(instruction) begin
case (instruction)
EXTEST: inst_string = "EXTEST";
SAMPLE: inst_string = "SAMPLE";
HIGHZ_MODE: inst_string = "HIGHZ_MODE";
CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS";
CLAMP: inst_string = "CLAMP";
RPC_DATA: inst_string = "RPC_DATA";
RPC_ADD: inst_string = "RPC_ADD";
BYPASS: inst_string = "BYPASS";
default: inst_string = "-XXXXXX-";
endcase
 
$display("%t %m Instruction = %s",$realtime, inst_string);
end
`endif
 
/rtl/verilog/copyright
0,0 → 1,21
/**********************************************************************/
/* */
/* */
/* Copyright (c) 2012-2015 Ouabache Design Works */
/* */
/* All Rights Reserved Worldwide */
/* */
/* Licensed under the Apache License,Version2.0 (the'License'); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in */
/* writing, software distributed under the License is */
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
/* OR CONDITIONS OF ANY KIND, either express or implied. */
/* See the License for the specific language governing */
/* permissions and limitations under the License. */
/**********************************************************************/
 
/rtl/verilog/classic_rpc_in_reg
0,0 → 1,17
// shift buffer and shadow
reg [BITS-1:0] buffer;
 
always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)
if (test_logic_reset) buffer <= RESET_VALUE;
else
if (select && capture_dr) buffer <= capture_value;
else
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };
else buffer <= buffer;
 
 
 
assign tdo = buffer[0];
 
 
/rtl/verilog/sync
0,0 → 1,7
assign syn_clk = clk;
assign syn_select = select;
assign syn_tdo = tdi;
assign tdo = syn_tdi;
assign syn_capture_dr = capture_dr;
assign syn_shift_dr = shift_dr ;
assign syn_update_dr = update_dr;
/rtl/verilog/jtag_rpc_in_reg
0,0 → 1,19
 
// shift buffer and shadow
reg [BITS-1:0] buffer;
 
always @(posedge clk or posedge reset)
if (reset) buffer <= RESET_VALUE;
else
if (select && capture_dr) buffer <= capture_value;
else
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };
else buffer <= buffer;
 
 
 
assign tdo = buffer[0];
 
 
/rtl/verilog/classic_sync
0,0 → 1,122
reg synced_reset;
 
always@(posedge clk or posedge test_logic_reset )
if(test_logic_reset)
begin
synced_reset <= 1'b1;
syn_reset <= 1'b1;
end
else
begin
synced_reset <= test_logic_reset;
syn_reset <= synced_reset;
end
 
reg synced_shift_dr;
reg synced_capture_dr;
 
 
always@(posedge clk)
if(!shiftcapture_dr_clk)
begin
synced_shift_dr <= shift_dr ;
synced_capture_dr <= capture_dr ;
end
else
begin
synced_shift_dr <= synced_shift_dr ;
synced_capture_dr <= synced_capture_dr ;
end
 
 
reg [1:0] synced_shiftcapture_dr_clk;
 
always@(posedge clk)
synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};
 
 
reg [1:0] synced_update_dr_clk;
 
always@(posedge clk)
synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};
 
 
always@(posedge clk)
if(synced_shiftcapture_dr_clk == 2'b01)
begin
syn_shift_dr <= synced_shift_dr ;
syn_capture_dr <= synced_capture_dr ;
end
else
begin
syn_shift_dr <= 1'b0 ;
syn_capture_dr <= 1'b0 ;
end
 
 
always@(posedge clk)
if(synced_update_dr_clk == 2'b01)
begin
syn_update_dr <= 1'b1 ;
end
else
begin
syn_update_dr <= 1'b0 ;
end
 
 
 
always@(posedge clk)
if(!shiftcapture_dr_clk && (shift_dr || capture_dr ))
begin
syn_tdi_o <= tdi ;
end
else
begin
syn_tdi_o <= syn_tdi_o ;
end
 
 
 
 
 
 
 
 
always@(posedge clk)
if(synced_update_dr_clk == 2'b01)
begin
syn_select <= select;
end
else if(synced_shiftcapture_dr_clk == 2'b01)
begin
syn_select <= select;
end
else
begin
syn_select <= syn_select;
end
 
 
 
 
 
 
assign syn_clk = clk;
assign tdo = syn_tdo_i;
 
/doc/Geda/html/cde_jtag_tap.html
80,7 → 80,7
 
<tr>
<td style="vertical-align: top;">CHIP_ID_VAL<br> </td>
<td style="vertical-align: top;">32'h12345678<br> </td>
<td style="vertical-align: top;">32'h00000000<br> </td>
<td style="vertical-align: top;"><br></td>
</tr>
 
/doc/Geda/html/cde_jtag_classic_rpc_in_reg.html
47,7 → 47,7
</li>
</ul>
</div>
<img style="width: 613px; height: 278px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sym.png"><br>
<img style="width: 613px; height: 302px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
145,6 → 145,12
<td style="vertical-align: top;"><br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">update_dr_clk<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;"><br> </td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
173,7 → 179,7
<br>
<br>
<br>
<img style="width: 613px; height: 278px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sch.png"><br>
<img style="width: 613px; height: 302px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sch.png"><br>
<b><br>
<br>
<br>
/sim/testbenches/xml/cde_jtag_classic_sync_tb.xml
30,15 → 30,8
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.tb.classic_sync</spirit:value>
<spirit:value>jtag_classic_sync_tb</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>top</spirit:name>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
167,7 → 160,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb.classic_sync</spirit:name>
<spirit:name>../verilog/common/jtag_classic_sync_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
179,7 → 172,7
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb.classic_sync</spirit:name>
<spirit:name>../verilog/common/jtag_classic_sync_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/sim/testbenches/xml/jtag_tap_duth.design.xml
0,0 → 1,214
<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library cde -component jtag -version tap //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>jtag</spirit:name>
<spirit:version>tap_duth.design</spirit:version>
<spirit:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>aux_capture_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_capture_dr_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_capture_dr_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_select_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_select_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_select_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_shift_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_shift_dr_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_shift_dr_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_shiftcapture_dr_clk_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_shiftcapture_dr_clk_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_shiftcapture_dr_clk_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_tdi_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_tdi_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_tdi_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_tdo_i</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_tdo_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_tdo_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_test_logic_reset_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_test_logic_reset_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_test_logic_reset_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>aux_update_dr_clk_o</spirit:name>
<spirit:externalPortReference spirit:portRef="aux_update_dr_clk_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_update_dr_clk_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>bsr_output_mode</spirit:name>
<spirit:externalPortReference spirit:portRef="bsr_output_mode" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bsr_output_mode" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>bsr_select_o</spirit:name>
<spirit:externalPortReference spirit:portRef="bsr_select_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bsr_select_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>bsr_tdo_i</spirit:name>
<spirit:externalPortReference spirit:portRef="bsr_tdo_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bsr_tdo_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>capture_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="capture_dr_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="capture_dr_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>jtag_clk</spirit:name>
<spirit:externalPortReference spirit:portRef="jtag_clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="jtag_clk" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>select_o</spirit:name>
<spirit:externalPortReference spirit:portRef="select_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="select_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>shift_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="shift_dr_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="shift_dr_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>shiftcapture_dr_clk_o</spirit:name>
<spirit:externalPortReference spirit:portRef="shiftcapture_dr_clk_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="shiftcapture_dr_clk_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tap_highz_mode</spirit:name>
<spirit:externalPortReference spirit:portRef="tap_highz_mode" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tap_highz_mode" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tclk_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="tclk_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tclk_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tdi_o</spirit:name>
<spirit:externalPortReference spirit:portRef="tdi_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdi_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tdi_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="tdi_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdi_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tdo_i</spirit:name>
<spirit:externalPortReference spirit:portRef="tdo_i" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdo_i" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tdo_pad_oe</spirit:name>
<spirit:externalPortReference spirit:portRef="tdo_pad_oe" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdo_pad_oe" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tdo_pad_out</spirit:name>
<spirit:externalPortReference spirit:portRef="tdo_pad_out" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdo_pad_out" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>test_logic_reset_o</spirit:name>
<spirit:externalPortReference spirit:portRef="test_logic_reset_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="test_logic_reset_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>tms_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="tms_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tms_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>trst_n_pad_in</spirit:name>
<spirit:externalPortReference spirit:portRef="trst_n_pad_in" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="trst_n_pad_in" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>update_dr_clk_o</spirit:name>
<spirit:externalPortReference spirit:portRef="update_dr_clk_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="update_dr_clk_o" />
</spirit:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>update_dr_o</spirit:name>
<spirit:externalPortReference spirit:portRef="update_dr_o" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="update_dr_o" />
</spirit:adHocConnection>
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="tap" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BYPASS">BYPASS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="CHIP_ID_ACCESS">CHIP_ID_ACCESS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="CHIP_ID_VAL">CHIP_ID_VAL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="CLAMP">CLAMP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="EXTEST">EXTEST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="HIGHZ_MODE">HIGHZ_MODE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="INST_LENGTH">INST_LENGTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="INST_RESET">INST_RESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="INST_RETURN">INST_RETURN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="NUM_USER">NUM_USER</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RPC_ADD">RPC_ADD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RPC_DATA">RPC_DATA</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="SAMPLE">SAMPLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="USER">USER</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/sim/testbenches/xml/cde_jtag_classic_tb.xml
30,15 → 30,8
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.tb.classic</spirit:value>
<spirit:value>jtag_classic_tb</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>top</spirit:name>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
144,9 → 137,6
<spirit:name>fs-common</spirit:name>
 
 
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.rpc_2</spirit:name>
167,7 → 157,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb.classic</spirit:name>
<spirit:name>../verilog/common/jtag_classic_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
179,7 → 169,7
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb.classic</spirit:name>
<spirit:name>../verilog/common/jtag_classic_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/sim/testbenches/xml/cde_jtag_tap_tb.xml
30,15 → 30,8
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top.tb</spirit:value>
<spirit:value>jtag_tap_tb</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>top</spirit:name>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
167,7 → 160,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb</spirit:name>
<spirit:name>../verilog/common/jtag_tap_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
179,7 → 172,7
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/top.tb</spirit:name>
<spirit:name>../verilog/common/jtag_tap_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
/sim/testbenches/xml/cde_jtag_tap_lint.xml
18,40 → 18,7
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>configuration</spirit:name>
<spirit:value>default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
<spirit:componentGenerator>
<spirit:name>gen_design</spirit:name>
<spirit:phase>103.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 

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