OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/cde/ip/mult
    from Rev 134 to Rev 135
    ↔ Reverse comparison
  •

Rev 134 → Rev 135

/componentCfg.xml
3,7 → 3,7
 
-->
<socgen:componentConfiguration
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
/doc/Geda/src/cde_mult_ord_r4.v File deleted
/doc/Geda/src/cde_mult_generic.v File deleted
/doc/Geda/src/cde_mult_serial.v File deleted
/doc/Geda/sym/cde_mult_ord_r4.sym File deleted
/doc/Geda/sym/cde_mult_generic.sym File deleted
/doc/Geda/sym/cde_mult_serial.sym File deleted
/doc/Geda/sch/cde_mult_ord_r4.sch File deleted
/doc/Geda/sch/cde_mult_generic.sch File deleted
/doc/Geda/sch/cde_mult_serial.sch File deleted
/doc/Geda/png/cde_mult_ord_r4_sym.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/Geda/png/cde_mult_ord_r4_sym.png
doc/Geda/png/cde_mult_ord_r4_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_mult_generic_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_mult_generic_sym.png =================================================================== --- doc/Geda/png/cde_mult_generic_sym.png (revision 134) +++ doc/Geda/png/cde_mult_generic_sym.png (nonexistent)
doc/Geda/png/cde_mult_generic_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_mult_ord_r4_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_mult_ord_r4_sch.png =================================================================== --- doc/Geda/png/cde_mult_ord_r4_sch.png (revision 134) +++ doc/Geda/png/cde_mult_ord_r4_sch.png (nonexistent)
doc/Geda/png/cde_mult_ord_r4_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_mult_serial_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_mult_serial_sym.png =================================================================== --- doc/Geda/png/cde_mult_serial_sym.png (revision 134) +++ doc/Geda/png/cde_mult_serial_sym.png (nonexistent)
doc/Geda/png/cde_mult_serial_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_mult_generic_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_mult_generic_sch.png =================================================================== --- doc/Geda/png/cde_mult_generic_sch.png (revision 134) +++ doc/Geda/png/cde_mult_generic_sch.png (nonexistent)
doc/Geda/png/cde_mult_generic_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_mult_serial_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_mult_serial_sch.png =================================================================== --- doc/Geda/png/cde_mult_serial_sch.png (revision 134) +++ doc/Geda/png/cde_mult_serial_sch.png (nonexistent)
doc/Geda/png/cde_mult_serial_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/html/cde_mult_ord_r4.html =================================================================== --- doc/Geda/html/cde_mult_ord_r4.html (revision 134) +++ doc/Geda/html/cde_mult_ord_r4.html (nonexistent) @@ -1,191 +0,0 @@ - - - - - start - - - - - - - - - - -

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NAME
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a_in[WIDTH-1:0 ]
input

alu_op_mul
input

b_in[WIDTH-1:0 ]
input

clk
input

ex_freeze
input

mul_prod_r[2*WIDTH-1:0 ]
output

mul_stall
output

reset
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NAME
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Description
a_in[WIDTH-1:0 ]
input

alu_op_mul
input

b_in[WIDTH-1:0 ]
input

clk
input

ex_freeze
input

mul_prod_r[2*WIDTH-1:0 ]
output

mul_stall
output

reset
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NAME
Type
Description
a_in[WIDTH-1:0 ]
input

alu_op_mul
input

b_in[WIDTH-1:0 ]
input

clk
input

ex_freeze
input

mul_prod_r[2*WIDTH-1:0 ]
output

mul_stall
output

reset
input

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NAME
Type
Description
alu_op_mul
input

clk
input

ex_freeze
input

reset
input

a_in[WIDTH-1:0]
input

b_in[WIDTH-1:0]
input

mul_stall
output

mul_prod_r[2*WIDTH-1:0]
output

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NAME
Type
Description
alu_op_mul
input

clk
input

ex_freeze
input

reset
input

a_in[WIDTH-1:0]
input

b_in[WIDTH-1:0]
input

mul_stall
output

mul_prod_r[2*WIDTH-1:0]
output

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NAME
Type
Description
alu_op_mul
input

clk
input

ex_freeze
input

reset
input

a_in[WIDTH-1:0]
input

b_in[WIDTH-1:0]
input

mul_stall
output

mul_prod_r[2*WIDTH-1:0]
output

+


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Children

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Instance
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Version
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+ + Index: doc/png/cde_mult_generic_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_mult_generic_sch.png =================================================================== --- doc/png/cde_mult_generic_sch.png (nonexistent) +++ doc/png/cde_mult_generic_sch.png (revision 135)
doc/png/cde_mult_generic_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_mult_generic_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_mult_generic_sym.png =================================================================== --- doc/png/cde_mult_generic_sym.png (nonexistent) +++ doc/png/cde_mult_generic_sym.png (revision 135)
doc/png/cde_mult_generic_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_mult_ord_r4_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_mult_ord_r4_sch.png =================================================================== --- doc/png/cde_mult_ord_r4_sch.png (nonexistent) +++ doc/png/cde_mult_ord_r4_sch.png (revision 135)
doc/png/cde_mult_ord_r4_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_mult_ord_r4_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_mult_ord_r4_sym.png =================================================================== --- doc/png/cde_mult_ord_r4_sym.png (nonexistent) +++ doc/png/cde_mult_ord_r4_sym.png (revision 135)
doc/png/cde_mult_ord_r4_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_mult_serial_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_mult_serial_sch.png =================================================================== --- doc/png/cde_mult_serial_sch.png (nonexistent) +++ doc/png/cde_mult_serial_sch.png (revision 135)
doc/png/cde_mult_serial_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_mult_serial_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_mult_serial_sym.png =================================================================== --- doc/png/cde_mult_serial_sym.png (nonexistent) +++ doc/png/cde_mult_serial_sym.png (revision 135)
doc/png/cde_mult_serial_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/sch/cde_mult_generic.sch =================================================================== --- doc/sch/cde_mult_generic.sch (nonexistent) +++ doc/sch/cde_mult_generic.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1700 300 1 0 0 in_port_vector.sym +{ +T 1700 300 5 10 1 1 0 6 1 1 +refdes=b_in[WIDTH-1:0] +} +C 1700 700 1 0 0 in_port_vector.sym +{ +T 1700 700 5 10 1 1 0 6 1 1 +refdes=a_in[WIDTH-1:0] +} +C 1700 1100 1 0 0 in_port.sym +{ +T 1700 1100 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1700 1500 1 0 0 in_port.sym +{ +T 1700 1500 5 10 1 1 0 6 1 1 +refdes=ex_freeze +} +C 1700 1900 1 0 0 in_port.sym +{ +T 1700 1900 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1700 2300 1 0 0 in_port.sym +{ +T 1700 2300 5 10 1 1 0 6 1 1 +refdes=alu_op_mul +} +C 5300 300 1 0 0 out_port_vector.sym +{ +T 6300 300 5 10 1 1 0 0 1 1 +refdes=mul_prod_r[2*WIDTH-1:0] +} +C 5300 700 1 0 0 out_port.sym +{ +T 6300 700 5 10 1 1 0 0 1 1 +refdes=mul_stall +} Index: doc/sch/cde_mult_ord_r4.sch =================================================================== --- doc/sch/cde_mult_ord_r4.sch (nonexistent) +++ doc/sch/cde_mult_ord_r4.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1700 300 1 0 0 in_port_vector.sym +{ +T 1700 300 5 10 1 1 0 6 1 1 +refdes=b_in[WIDTH-1:0] +} +C 1700 700 1 0 0 in_port_vector.sym +{ +T 1700 700 5 10 1 1 0 6 1 1 +refdes=a_in[WIDTH-1:0] +} +C 1700 1100 1 0 0 in_port.sym +{ +T 1700 1100 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1700 1500 1 0 0 in_port.sym +{ +T 1700 1500 5 10 1 1 0 6 1 1 +refdes=ex_freeze +} +C 1700 1900 1 0 0 in_port.sym +{ +T 1700 1900 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1700 2300 1 0 0 in_port.sym +{ +T 1700 2300 5 10 1 1 0 6 1 1 +refdes=alu_op_mul +} +C 5300 300 1 0 0 out_port_vector.sym +{ +T 6300 300 5 10 1 1 0 0 1 1 +refdes=mul_prod_r[2*WIDTH-1:0] +} +C 5300 700 1 0 0 out_port.sym +{ +T 6300 700 5 10 1 1 0 0 1 1 +refdes=mul_stall +} Index: doc/sch/cde_mult_serial.sch =================================================================== --- doc/sch/cde_mult_serial.sch (nonexistent) +++ doc/sch/cde_mult_serial.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1700 300 1 0 0 in_port_vector.sym +{ +T 1700 300 5 10 1 1 0 6 1 1 +refdes=b_in[WIDTH-1:0] +} +C 1700 700 1 0 0 in_port_vector.sym +{ +T 1700 700 5 10 1 1 0 6 1 1 +refdes=a_in[WIDTH-1:0] +} +C 1700 1100 1 0 0 in_port.sym +{ +T 1700 1100 5 10 1 1 0 6 1 1 +refdes=reset +} +C 1700 1500 1 0 0 in_port.sym +{ +T 1700 1500 5 10 1 1 0 6 1 1 +refdes=ex_freeze +} +C 1700 1900 1 0 0 in_port.sym +{ +T 1700 1900 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1700 2300 1 0 0 in_port.sym +{ +T 1700 2300 5 10 1 1 0 6 1 1 +refdes=alu_op_mul +} +C 5300 300 1 0 0 out_port_vector.sym +{ +T 6300 300 5 10 1 1 0 0 1 1 +refdes=mul_prod_r[2*WIDTH-1:0] +} +C 5300 700 1 0 0 out_port.sym +{ +T 6300 700 5 10 1 1 0 0 1 1 +refdes=mul_stall +} Index: doc/sym/cde_mult_generic.sym =================================================================== --- doc/sym/cde_mult_generic.sym (nonexistent) +++ doc/sym/cde_mult_generic.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 4200 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1650 5 10 1 1 0 0 1 1 +device=cde_mult_generic +T 400 1850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2000 0 10 0 1 0 0 1 1 +library=cde +T 400 2000 0 10 0 1 0 0 1 1 +component=mult +T 400 2000 0 10 0 1 0 0 1 1 +version=generic +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=b_in[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=a_in[WIDTH-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=ex_freeze +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=alu_op_mul +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 4500 200 4800 200 10 1 1 +{ +T 4400 200 5 10 1 1 0 7 1 1 +pinnumber=mul_prod_r[2*WIDTH-1:0] +T 4400 200 5 10 0 1 0 7 1 1 +pinseq=7 +} +P 4500 400 4800 400 4 0 1 +{ +T 4400 400 5 10 1 1 0 7 1 1 +pinnumber=mul_stall +T 4500 400 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: doc/sym/cde_mult_ord_r4.sym =================================================================== --- doc/sym/cde_mult_ord_r4.sym (nonexistent) +++ doc/sym/cde_mult_ord_r4.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 4200 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1650 5 10 1 1 0 0 1 1 +device=cde_mult_ord_r4 +T 400 1850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2000 0 10 0 1 0 0 1 1 +library=cde +T 400 2000 0 10 0 1 0 0 1 1 +component=mult +T 400 2000 0 10 0 1 0 0 1 1 +version=ord_r4 +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=b_in[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=a_in[WIDTH-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=ex_freeze +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=alu_op_mul +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 4500 200 4800 200 10 1 1 +{ +T 4400 200 5 10 1 1 0 7 1 1 +pinnumber=mul_prod_r[2*WIDTH-1:0] +T 4400 200 5 10 0 1 0 7 1 1 +pinseq=7 +} +P 4500 400 4800 400 4 0 1 +{ +T 4400 400 5 10 1 1 0 7 1 1 +pinnumber=mul_stall +T 4500 400 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: doc/sym/cde_mult_serial.sym =================================================================== --- doc/sym/cde_mult_serial.sym (nonexistent) +++ doc/sym/cde_mult_serial.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 4200 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1650 5 10 1 1 0 0 1 1 +device=cde_mult_serial +T 400 1850 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2000 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2000 0 10 0 1 0 0 1 1 +library=cde +T 400 2000 0 10 0 1 0 0 1 1 +component=mult +T 400 2000 0 10 0 1 0 0 1 1 +version=serial +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=b_in[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=a_in[WIDTH-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=ex_freeze +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=alu_op_mul +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 4500 200 4800 200 10 1 1 +{ +T 4400 200 5 10 1 1 0 7 1 1 +pinnumber=mul_prod_r[2*WIDTH-1:0] +T 4400 200 5 10 0 1 0 7 1 1 +pinseq=7 +} +P 4500 400 4800 400 4 0 1 +{ +T 4400 400 5 10 1 1 0 7 1 1 +pinnumber=mul_stall +T 4500 400 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: rtl/verilog/top.generic =================================================================== --- rtl/verilog/top.generic (revision 134) +++ rtl/verilog/top.generic (revision 135) @@ -20,7 +20,7 @@ reg [1:0] mul_stall_count; -`ifndef SYNTHESYS +`ifndef SYNTHESIS always@(posedge clk)
/rtl/verilog/top.ord_r4
31,7 → 31,7
assign y = b_in;
 
 
`ifndef SYNTHESYS
`ifndef SYNTHESIS
 
 
always@(posedge clk)
/rtl/verilog/top.serial
29,7 → 29,7
assign y = b_in;
 
 
`ifndef SYNTHESYS
`ifndef SYNTHESIS
 
 
always@(posedge clk)
/rtl/xml/cde_mult_generic.xml
2,294 → 2,333
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>generic</spirit:version> <spirit:configuration>default</spirit:configuration>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>generic</ipxact:version>
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>mult_generic</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>mult_generic</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_sim</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>sim</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_syn</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>syn</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
 
<spirit:file>
<spirit:name>../verilog/top.generic</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
 
</spirit:fileSet>
<ipxact:model>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<ipxact:instantiations>
 
<spirit:file>
<spirit:name>../verilog/common/mult_generic</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:componentInstantiation>
<ipxact:name>verilog</ipxact:name>
<ipxact:language>verilog</ipxact:language>
<ipxact:moduleName>cde_mult_generic</ipxact:moduleName>
<ipxact:moduleParameters>
<ipxact:moduleParameter parameterId="WIDTH" usageCount="1" usageType="nontyped">
<ipxact:name>WIDTH</ipxact:name>
<ipxact:value>16</ipxact:value>
</ipxact:moduleParameter>
</ipxact:moduleParameters>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:componentInstantiation>
</ipxact:instantiations>
 
 
<spirit:file>
<spirit:name>../verilog/or1200_gmultp2_32x32.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<ipxact:views>
 
<spirit:file>
<spirit:name>../verilog/common/mult_generic</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:view>
<ipxact:name>rtl</ipxact:name>
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef>
</ipxact:view>
 
<spirit:file>
<spirit:name>../verilog/or1200_gmultp2_32x32.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
</spirit:fileSet>
 
<ipxact:view>
<ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-syn</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:view>
<ipxact:name>doc</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="documentation"/>
</ipxact:vendorExtensions>
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
</ipxact:view>
 
</spirit:fileSet>
 
 
</ipxact:views>
 
 
</spirit:fileSets>
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>16</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
 
 
 
 
<ipxact:ports>
 
<ipxact:port><ipxact:name>clk</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<ipxact:port><ipxact:name>reset</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:port><ipxact:name>a_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
 
<ipxact:port><ipxact:name>b_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
<ipxact:port><ipxact:name>alu_op_mul</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
</spirit:views>
<ipxact:port><ipxact:name>ex_freeze</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
 
 
<ipxact:port><ipxact:name>mul_prod_r</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>2*WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>mul_stall</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
 
</ipxact:ports>
 
</ipxact:model>
 
 
<spirit:port><spirit:name>a_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>b_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:fileSets>
 
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<spirit:port><spirit:name>alu_op_mul</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<ipxact:file>
<ipxact:name>../verilog/top.generic</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
<spirit:port><spirit:name>ex_freeze</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
</ipxact:fileSet>
 
 
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:port><spirit:name>mul_prod_r</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>2*WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<ipxact:file>
<ipxact:name>../verilog/common/mult_generic</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<spirit:port><spirit:name>mul_stall</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<ipxact:file>
<ipxact:name>../verilog/or1200_gmultp2_32x32.v</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/sim/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
</spirit:ports>
 
</spirit:model>
<ipxact:fileSet>
<ipxact:name>fs-syn</ipxact:name>
 
<ipxact:file>
<ipxact:name>../verilog/common/mult_generic</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<ipxact:file>
<ipxact:name>../verilog/or1200_gmultp2_32x32.v</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
 
 
</ipxact:fileSet>
 
 
</spirit:component>
 
<ipxact:fileSet>
 
<ipxact:name>fs-lint</ipxact:name>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
 
 
 
</ipxact:fileSets>
 
 
 
 
 
 
</ipxact:component>
/rtl/xml/cde_mult_ord_r4.xml
2,294 → 2,331
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>ord_r4</spirit:version> <spirit:configuration>default</spirit:configuration>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>ord_r4</ipxact:version>
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>mult_ord_r4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>mult_ord_r4</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_sim</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>sim</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_syn</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>syn</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
 
<spirit:file>
<spirit:name>../verilog/top.ord_r4</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<ipxact:model>
 
<spirit:file>
<spirit:name>../verilog/common/mult_ord_r4</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:instantiations>
 
<ipxact:componentInstantiation>
<ipxact:name>verilog</ipxact:name>
<ipxact:language>verilog</ipxact:language>
<ipxact:moduleName>cde_mult_ord_r4</ipxact:moduleName>
<ipxact:moduleParameters>
<ipxact:moduleParameter parameterId="WIDTH" usageCount="1" usageType="nontyped">
<ipxact:name>WIDTH</ipxact:name>
<ipxact:value>16</ipxact:value>
</ipxact:moduleParameter>
</ipxact:moduleParameters>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:componentInstantiation>
</ipxact:instantiations>
 
<spirit:file>
<spirit:name>../verilog/ord_r4.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:views>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<ipxact:view>
<ipxact:name>rtl</ipxact:name>
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef>
</ipxact:view>
 
<spirit:file>
<spirit:name>../verilog/common/mult_ord_r4</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:name>../verilog/ord_r4.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
 
</spirit:fileSet>
<ipxact:view>
<ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-syn</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<ipxact:view>
<ipxact:name>doc</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="documentation"/>
</ipxact:vendorExtensions>
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
</ipxact:view>
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</ipxact:views>
 
 
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>16</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
 
</spirit:fileSets>
 
 
 
 
<ipxact:ports>
 
<ipxact:port><ipxact:name>clk</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<ipxact:port><ipxact:name>reset</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<ipxact:port><ipxact:name>a_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<ipxact:port><ipxact:name>b_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
<ipxact:port><ipxact:name>alu_op_mul</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
<ipxact:port><ipxact:name>ex_freeze</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
</spirit:views>
 
 
<ipxact:port><ipxact:name>mul_prod_r</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>2*WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
 
<ipxact:port><ipxact:name>mul_stall</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
</ipxact:ports>
 
</ipxact:model>
 
 
 
 
<spirit:port><spirit:name>a_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:fileSets>
 
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<spirit:port><spirit:name>b_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<ipxact:file>
<ipxact:name>../verilog/top.ord_r4</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
<spirit:port><spirit:name>alu_op_mul</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
</ipxact:fileSet>
 
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:port><spirit:name>ex_freeze</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:file>
<ipxact:name>../verilog/common/mult_ord_r4</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
<ipxact:file>
<ipxact:name>../verilog/ord_r4.v</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:port><spirit:name>mul_prod_r</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>2*WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/sim/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
<spirit:port><spirit:name>mul_stall</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
 
<ipxact:fileSet>
<ipxact:name>fs-syn</ipxact:name>
 
<ipxact:file>
<ipxact:name>../verilog/common/mult_ord_r4</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<ipxact:file>
<ipxact:name>../verilog/ord_r4.v</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
</spirit:ports>
 
</spirit:model>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
 
 
</ipxact:fileSet>
 
 
 
<ipxact:fileSet>
 
<ipxact:name>fs-lint</ipxact:name>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</spirit:component>
</ipxact:fileSet>
 
 
 
 
 
</ipxact:fileSets>
 
 
 
 
 
 
</ipxact:component>
/rtl/xml/cde_mult_serial.xml
2,280 → 2,322
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>serial</spirit:version> <spirit:configuration>default</spirit:configuration>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>serial</ipxact:version>
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>mult_serial</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>mult_serial</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_sim</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>sim</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../views</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilogLib_syn</ipxact:name>
<ipxact:phase>105.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilogLib</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>dest_dir</ipxact:name>
<ipxact:value>../views</ipxact:value>
</ipxact:parameter>
<ipxact:parameter>
<ipxact:name>view</ipxact:name>
<ipxact:value>syn</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
 
<spirit:file>
<spirit:name>../verilog/top.serial</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<ipxact:model>
 
<spirit:file>
<spirit:name>../verilog/common/mult_serial</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
<ipxact:instantiations>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<ipxact:componentInstantiation>
<ipxact:name>verilog</ipxact:name>
<ipxact:language>verilog</ipxact:language>
<ipxact:moduleName>cde_mult_serial</ipxact:moduleName>
<ipxact:moduleParameters>
<ipxact:moduleParameter parameterId="WIDTH" usageCount="1" usageType="nontyped">
<ipxact:name>WIDTH</ipxact:name>
<ipxact:value>16</ipxact:value>
</ipxact:moduleParameter>
</ipxact:moduleParameters>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:componentInstantiation>
</ipxact:instantiations>
 
<spirit:file>
<spirit:name>../verilog/common/mult_serial</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<ipxact:views>
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:view>
<ipxact:name>rtl</ipxact:name>
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef>
</ipxact:view>
 
</spirit:fileSet>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
</spirit:fileSets>
 
<ipxact:view>
<ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-syn</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<ipxact:view>
<ipxact:name>doc</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="documentation"/>
</ipxact:vendorExtensions>
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
</ipxact:view>
 
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</ipxact:views>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>16</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
 
<ipxact:ports>
 
<ipxact:port><ipxact:name>clk</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<ipxact:port><ipxact:name>reset</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
</spirit:views>
 
 
 
 
<ipxact:port><ipxact:name>a_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>b_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<ipxact:port><ipxact:name>alu_op_mul</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
<ipxact:port><ipxact:name>ex_freeze</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
 
<spirit:port><spirit:name>a_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<ipxact:port><ipxact:name>mul_prod_r</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>2*WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>b_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<ipxact:port><ipxact:name>mul_stall</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>alu_op_mul</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>ex_freeze</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
</ipxact:ports>
 
</ipxact:model>
 
 
<spirit:port><spirit:name>mul_prod_r</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>2*WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>mul_stall</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:fileSets>
 
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<ipxact:file>
<ipxact:name>../verilog/top.serial</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
</spirit:ports>
 
</spirit:model>
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<ipxact:file>
<ipxact:name>../verilog/common/mult_serial</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/sim/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
 
<ipxact:fileSet>
<ipxact:name>fs-syn</ipxact:name>
 
<ipxact:file>
<ipxact:name>../verilog/common/mult_serial</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
 
</spirit:component>
 
</ipxact:fileSet>
 
 
<ipxact:fileSet>
 
<ipxact:name>fs-lint</ipxact:name>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName><ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
 
 
 
</ipxact:fileSets>
 
 
 
 
 
 
</ipxact:component>
/sim/bin/Makefile File deleted
/sim/testbenches/verilog/synthesys
1,2 → 1,2
`define SYNTHESYS
`define SYNTHESIS
 
/sim/testbenches/verilog/top
22,7 → 22,7
assign mask = {32{mask_R}};
 
 
`ifndef SYNTHESYS
`ifndef SYNTHESIS
 
task u_cmp;
input [31:0] a_in;
/sim/testbenches/verilog/top.64
11,7 → 11,7
.signal ( mul_prod_r[31:0] )
);
 
`ifndef SYNTHESYS
`ifndef SYNTHESIS
 
task u_cmp;
input [31:0] a_in;
/sim/testbenches/xml/cde_mult_bfm.design.xml
2,17 → 2,17
<!--
 
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>bfm.design</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>bfm.design</ipxact:version>
 
 
 
19,41 → 19,41
 
 
 
<spirit:adHocConnections>
<ipxact:adHocConnections>
 
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/>
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="clk"/>
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>clk</ipxact:name>
<ipxact:externalPortReference portRef="slave_clk_clk"/>
<ipxact:internalPortReference componentRef="rdata_tpb" portRef="clk"/>
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>mul_prod_exp_P</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_prod_exp_P" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="expected_value"/>
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_prod_exp_P</ipxact:name>
<ipxact:externalPortReference portRef="mul_prod_exp_P" left="31" right="0" />
<ipxact:internalPortReference componentRef="rdata_tpb" portRef="expected_value"/>
</ipxact:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>mask</spirit:name>
<spirit:externalPortReference spirit:portRef="mask" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="mask"/>
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mask</ipxact:name>
<ipxact:externalPortReference portRef="mask" left="31" right="0" />
<ipxact:internalPortReference componentRef="rdata_tpb" portRef="mask"/>
</ipxact:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>mul_prod_r</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_prod_r" spirit:left="31" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="signal"/>
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_prod_r</ipxact:name>
<ipxact:externalPortReference portRef="mul_prod_r" left="31" right="0" />
<ipxact:internalPortReference componentRef="rdata_tpb" portRef="signal"/>
</ipxact:adHocConnection>
 
 
 
 
</spirit:adHocConnections>
</ipxact:adHocConnections>
 
 
 
63,16 → 63,16
 
 
 
<spirit:componentInstances>
<ipxact:componentInstances>
 
 
<spirit:componentInstance>
<spirit:instanceName>rdata_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MESG">"multiply Error"</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<ipxact:componentInstance>
<ipxact:instanceName>rdata_tpb</ipxact:instanceName> <ipxact:componentRef vendor="opencores.org" library="Testbench" name="io_probe" version="in" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="WIDTH">32</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="MESG">"multiply Error"</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>
 
 
 
84,9 → 84,9
 
 
 
</spirit:componentInstances>
</ipxact:componentInstances>
 
 
 
 
</spirit:design>
</ipxact:design>
/sim/testbenches/xml/cde_mult_generic_lint.xml
2,25 → 2,25
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>generic_lint</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>generic_lint</ipxact:version>
 
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
28,45 → 28,45
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
 
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="generic_dut.params"/>
<ipxact:view>
<ipxact:name>Dut</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="generic_dut.params"/>
 
</spirit:vendorExtensions>
</spirit:view>
</ipxact:vendorExtensions>
</ipxact:view>
 
<spirit:view>
<spirit:name>lint</spirit:name>
<spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>lint</ipxact:name>
<ipxact:envIdentifier>:*Lint:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:fileSetRef><ipxact:localName>fs-lint</ipxact:localName></ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>rtl_check</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="rtl_check"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>rtl_check</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="rtl_check"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
 
</spirit:model>
</ipxact:model>
 
 
 
77,14 → 77,14
 
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
91,29 → 91,29
 
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/lint/mult_generic_lint</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/lint/mult_generic_lint</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
 
</spirit:component>
</ipxact:component>
/sim/testbenches/xml/cde_mult_generic_tb.xml
2,41 → 2,41
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>generic_tb</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>generic_tb</ipxact:version>
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>mult_generic_tb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>mult_generic_tb</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
45,139 → 45,139
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
<spirit:view>
<spirit:name>Params</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="generic_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>Params</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="generic_dut.params"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>Bfm</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="bfm.design"/>
</spirit:view>
<ipxact:view>
<ipxact:name>Bfm</ipxact:name>
<ipxact:hierarchyRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="bfm.design"/>
</ipxact:view>
 
 
 
 
<spirit:view>
<spirit:name>icarus</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="icarus"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>icarus</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="icarus"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:view>
<spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>lint</ipxact:name><ipxact:envIdentifier>:*Lint:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-lint</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
 
</spirit:model>
</ipxact:model>
 
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/top</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/mult_generic_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/mult_generic_tb</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/synthesys</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/synthesys</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/mult_generic_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/mult_generic_tb</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
 
</spirit:component>
</ipxact:component>
/sim/testbenches/xml/cde_mult_ord_r4_lint.xml
2,110 → 2,110
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>ord_r4_lint</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>ord_r4_lint</ipxact:version>
 
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
 
 
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="ord_r4_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>Dut</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="ord_r4_dut.params"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
 
<spirit:view>
<spirit:name>lint</spirit:name>
<spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>lint</ipxact:name>
<ipxact:envIdentifier>:*Lint:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:fileSetRef><ipxact:localName>fs-lint</ipxact:localName></ipxact:fileSetRef>
</ipxact:view>
 
 
 
<spirit:view>
<spirit:name>rtl_check</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="rtl_check"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>rtl_check</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="rtl_check"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
</spirit:model>
</ipxact:model>
 
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/synthesys</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/synthesys</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/lint/mult_ord_r4_lint</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/lint/mult_ord_r4_lint</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
</spirit:component>
</ipxact:component>
/sim/testbenches/xml/cde_mult_ord_r4_tb.xml
2,43 → 2,43
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>ord_r4_tb</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>ord_r4_tb</ipxact:version>
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>mult_ord_r4_tb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>mult_ord_r4_tb</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
47,140 → 47,140
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
 
 
<spirit:view>
<spirit:name>Params</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="ord_r4_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>Params</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="ord_r4_dut.params"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
 
 
<spirit:view>
<spirit:name>Bfm</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="bfm.design"/>
</spirit:view>
<ipxact:view>
<ipxact:name>Bfm</ipxact:name>
<ipxact:hierarchyRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="bfm.design"/>
</ipxact:view>
 
 
 
<spirit:view>
<spirit:name>icarus</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="icarus"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>icarus</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="icarus"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
 
<spirit:view>
<spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>lint</ipxact:name><ipxact:envIdentifier>:*Lint:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-lint</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
 
 
</spirit:model>
</ipxact:model>
 
 
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/top</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
</spirit:fileSet>
</ipxact:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/mult_ord_r4_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/mult_ord_r4_tb</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/synthesys</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/synthesys</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/mult_ord_r4_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/mult_ord_r4_tb</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
 
</spirit:component>
</ipxact:component>
/sim/testbenches/xml/cde_mult_serial_lint.xml
2,25 → 2,25
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>serial_lint</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>serial_lint</ipxact:version>
 
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
27,46 → 27,46
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
 
 
 
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="serial_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>Dut</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="serial_dut.params"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
<spirit:view>
<spirit:name>lint</spirit:name>
<spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>lint</ipxact:name>
<ipxact:envIdentifier>:*Lint:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:fileSetRef><ipxact:localName>fs-lint</ipxact:localName></ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>rtl_check</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="rtl_check"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>rtl_check</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="rtl_check"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
 
</spirit:model>
</ipxact:model>
 
 
 
73,30 → 73,30
 
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/lint/mult_serial_lint</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/lint/mult_serial_lint</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
 
</spirit:component>
</ipxact:component>
/sim/testbenches/xml/cde_mult_serial_tb.xml
2,42 → 2,42
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>serial_tb</spirit:version>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>serial_tb</ipxact:version>
 
 
 
<spirit:componentGenerators>
<ipxact:componentGenerators>
 
 
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>mult_serial_tb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>mult_serial_tb</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
 
 
</spirit:componentGenerators>
</ipxact:componentGenerators>
 
 
 
46,137 → 46,137
 
 
 
<spirit:model>
<spirit:views>
<ipxact:model>
<ipxact:views>
 
<spirit:view>
<spirit:name>Params</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="serial_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>Params</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="serial_dut.params"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>Bfm</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="bfm.design"/>
</spirit:view>
<ipxact:view>
<ipxact:name>Bfm</ipxact:name>
<ipxact:hierarchyRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="bfm.design"/>
</ipxact:view>
 
 
 
<spirit:view>
<spirit:name>icarus</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="icarus"/>
</spirit:vendorExtensions>
</spirit:view>
<ipxact:view>
<ipxact:name>icarus</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="icarus"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
 
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
 
<spirit:view>
<spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<ipxact:view>
<ipxact:name>lint</ipxact:name><ipxact:envIdentifier>:*Lint:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-lint</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
</spirit:views>
</ipxact:views>
 
 
 
 
</spirit:model>
</ipxact:model>
 
 
 
 
<spirit:fileSets>
<ipxact:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/top</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
</spirit:fileSet>
</ipxact:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/mult_serial_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/mult_serial_tb</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/synthesys</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/synthesys</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/mult_serial_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/mult_serial_tb</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
183,4 → 183,4
 
 
 
</spirit:component>
</ipxact:component>
/sim/testbenches/xml/mult_generic_dut.params.xml
6,31 → 6,31
// //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>generic_dut.params</spirit:version>
<spirit:model>
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>generic_dut.params</ipxact:version>
<ipxact:model>
 
<spirit:views>
<ipxact:views>
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="generic_dutg.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
</spirit:component>
<ipxact:view>
<ipxact:name>Dut</ipxact:name>
<ipxact:envIdentifier></ipxact:envIdentifier>
<ipxact:hierarchyRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="generic_dutg.design"/>
</ipxact:view>
</ipxact:views>
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
</ipxact:model>
</ipxact:component>
/sim/testbenches/xml/mult_generic_dutg.design.xml
6,85 → 6,85
// regen by adding -tb to gen_verilog script //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>generic_dutg.design</spirit:version>
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>generic_dutg.design</ipxact:version>
 
 
 
<spirit:adHocConnections>
<ipxact:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>clk</ipxact:name>
<ipxact:externalPortReference portRef="clk" />
<ipxact:internalPortReference componentRef="dut" portRef="clk" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>reset</ipxact:name>
<ipxact:externalPortReference portRef="reset" />
<ipxact:internalPortReference componentRef="dut" portRef="reset" />
</ipxact:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>a_in</spirit:name>
<spirit:externalPortReference spirit:portRef="a_in" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="a_in" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>a_in</ipxact:name>
<ipxact:externalPortReference portRef="a_in" left="WIDTH-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="a_in" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>b_in</spirit:name>
<spirit:externalPortReference spirit:portRef="b_in" spirit:left="WIDTH-1" spirit:right="0"/>
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="b_in" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>b_in</ipxact:name>
<ipxact:externalPortReference portRef="b_in" left="WIDTH-1" right="0"/>
<ipxact:internalPortReference componentRef="dut" portRef="b_in" />
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>alu_op_mul</spirit:name>
<spirit:externalPortReference spirit:portRef="alu_op_mul" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="alu_op_mul" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>alu_op_mul</ipxact:name>
<ipxact:externalPortReference portRef="alu_op_mul" />
<ipxact:internalPortReference componentRef="dut" portRef="alu_op_mul" />
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>ex_freeze</spirit:name>
<spirit:externalPortReference spirit:portRef="ex_freeze" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ex_freeze" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>ex_freeze</ipxact:name>
<ipxact:externalPortReference portRef="ex_freeze" />
<ipxact:internalPortReference componentRef="dut" portRef="ex_freeze" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mul_prod_r</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_prod_r" spirit:left="2*WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mul_prod_r" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_prod_r</ipxact:name>
<ipxact:externalPortReference portRef="mul_prod_r" left="2*WIDTH-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="mul_prod_r" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mul_stall</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_stall" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mul_stall" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_stall</ipxact:name>
<ipxact:externalPortReference portRef="mul_stall" />
<ipxact:internalPortReference componentRef="dut" portRef="mul_stall" />
</ipxact:adHocConnection>
 
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
</ipxact:adHocConnections>
<ipxact:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="mult" spirit:version="generic" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
<ipxact:componentInstance>
<ipxact:instanceName>dut</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="cde" name="mult" version="generic" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="WIDTH">WIDTH</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>
</ipxact:componentInstances>
</ipxact:design>
/sim/testbenches/xml/mult_ord_r4_dut.params.xml
6,31 → 6,31
// //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>ord_r4_dut.params</spirit:version>
<spirit:model>
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>ord_r4_dut.params</ipxact:version>
<ipxact:model>
 
<spirit:views>
<ipxact:views>
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="ord_r4_dutg.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
</spirit:component>
<ipxact:view>
<ipxact:name>Dut</ipxact:name>
<ipxact:envIdentifier></ipxact:envIdentifier>
<ipxact:hierarchyRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="ord_r4_dutg.design"/>
</ipxact:view>
</ipxact:views>
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
</ipxact:model>
</ipxact:component>
/sim/testbenches/xml/mult_ord_r4_dutg.design.xml
6,85 → 6,85
// regen by adding -tb to gen_verilog script //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>ord_r4_dutg.design</spirit:version>
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>ord_r4_dutg.design</ipxact:version>
 
 
 
<spirit:adHocConnections>
<ipxact:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>clk</ipxact:name>
<ipxact:externalPortReference portRef="clk" />
<ipxact:internalPortReference componentRef="dut" portRef="clk" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>reset</ipxact:name>
<ipxact:externalPortReference portRef="reset" />
<ipxact:internalPortReference componentRef="dut" portRef="reset" />
</ipxact:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>a_in</spirit:name>
<spirit:externalPortReference spirit:portRef="a_in" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="a_in" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>a_in</ipxact:name>
<ipxact:externalPortReference portRef="a_in" left="WIDTH-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="a_in" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>b_in</spirit:name>
<spirit:externalPortReference spirit:portRef="b_in" spirit:left="WIDTH-1" spirit:right="0"/>
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="b_in" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>b_in</ipxact:name>
<ipxact:externalPortReference portRef="b_in" left="WIDTH-1" right="0"/>
<ipxact:internalPortReference componentRef="dut" portRef="b_in" />
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>alu_op_mul</spirit:name>
<spirit:externalPortReference spirit:portRef="alu_op_mul" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="alu_op_mul" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>alu_op_mul</ipxact:name>
<ipxact:externalPortReference portRef="alu_op_mul" />
<ipxact:internalPortReference componentRef="dut" portRef="alu_op_mul" />
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>ex_freeze</spirit:name>
<spirit:externalPortReference spirit:portRef="ex_freeze" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ex_freeze" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>ex_freeze</ipxact:name>
<ipxact:externalPortReference portRef="ex_freeze" />
<ipxact:internalPortReference componentRef="dut" portRef="ex_freeze" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mul_prod_r</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_prod_r" spirit:left="2*WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mul_prod_r" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_prod_r</ipxact:name>
<ipxact:externalPortReference portRef="mul_prod_r" left="2*WIDTH-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="mul_prod_r" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mul_stall</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_stall" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mul_stall" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_stall</ipxact:name>
<ipxact:externalPortReference portRef="mul_stall" />
<ipxact:internalPortReference componentRef="dut" portRef="mul_stall" />
</ipxact:adHocConnection>
 
 
 
</spirit:adHocConnections>
<spirit:componentInstances>
</ipxact:adHocConnections>
<ipxact:componentInstances>
 
<spirit:componentInstance>
<spirit:instanceName>dut</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="mult" spirit:version="ord_r4" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
<ipxact:componentInstance>
<ipxact:instanceName>dut</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="cde" name="mult" version="ord_r4" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="WIDTH">WIDTH</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>
</ipxact:componentInstances>
</ipxact:design>
/sim/testbenches/xml/mult_serial_dut.params.xml
6,31 → 6,31
// //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>serial_dut.params</spirit:version>
<spirit:model>
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>serial_dut.params</ipxact:version>
<ipxact:model>
 
<spirit:views>
<ipxact:views>
<spirit:view>
<spirit:name>Dut</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="mult"
spirit:version="serial_dutg.design"/>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
</spirit:component>
<ipxact:view>
<ipxact:name>Dut</ipxact:name>
<ipxact:envIdentifier></ipxact:envIdentifier>
<ipxact:hierarchyRef ipxact:vendor="opencores.org"
ipxact:library="cde"
ipxact:name="mult"
ipxact:version="serial_dutg.design"/>
</ipxact:view>
</ipxact:views>
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>32</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
</ipxact:model>
</ipxact:component>
/sim/testbenches/xml/mult_serial_dutg.design.xml
6,85 → 6,85
// regen by adding -tb to gen_verilog script //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>serial_dutg.design</spirit:version>
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>mult</ipxact:name>
<ipxact:version>serial_dutg.design</ipxact:version>
 
 
 
<spirit:adHocConnections>
<ipxact:adHocConnections>
 
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>clk</ipxact:name>
<ipxact:externalPortReference portRef="clk" />
<ipxact:internalPortReference componentRef="dut" portRef="clk" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>reset</ipxact:name>
<ipxact:externalPortReference portRef="reset" />
<ipxact:internalPortReference componentRef="dut" portRef="reset" />
</ipxact:adHocConnection>
 
 
<spirit:adHocConnection>
<spirit:name>a_in</spirit:name>
<spirit:externalPortReference spirit:portRef="a_in" spirit:left="WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="a_in" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>a_in</ipxact:name>
<ipxact:externalPortReference portRef="a_in" left="WIDTH-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="a_in" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>b_in</spirit:name>
<spirit:externalPortReference spirit:portRef="b_in" spirit:left="WIDTH-1" spirit:right="0"/>
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="b_in" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>b_in</ipxact:name>
<ipxact:externalPortReference portRef="b_in" left="WIDTH-1" right="0"/>
<ipxact:internalPortReference componentRef="dut" portRef="b_in" />
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>alu_op_mul</spirit:name>
<spirit:externalPortReference spirit:portRef="alu_op_mul" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="alu_op_mul" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>alu_op_mul</ipxact:name>
<ipxact:externalPortReference portRef="alu_op_mul" />
<ipxact:internalPortReference componentRef="dut" portRef="alu_op_mul" />
</ipxact:adHocConnection>
 
 
 
<spirit:adHocConnection>
<spirit:name>ex_freeze</spirit:name>
<spirit:externalPortReference spirit:portRef="ex_freeze" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="ex_freeze" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>ex_freeze</ipxact:name>
<ipxact:externalPortReference portRef="ex_freeze" />
<ipxact:internalPortReference componentRef="dut" portRef="ex_freeze" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mul_prod_r</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_prod_r" spirit:left="2*WIDTH-1" spirit:right="0" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mul_prod_r" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_prod_r</ipxact:name>
<ipxact:externalPortReference portRef="mul_prod_r" left="2*WIDTH-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="mul_prod_r" />
</ipxact:adHocConnection>
 
<spirit:adHocConnection>
<spirit:name>mul_stall</spirit:name>
<spirit:externalPortReference spirit:portRef="mul_stall" />
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="mul_stall" />
</spirit:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>mul_stall</ipxact:name>
<ipxact:externalPortReference portRef="mul_stall" />
<ipxact:internalPortReference componentRef="dut" portRef="mul_stall" />
</ipxact:adHocConnection>
 
 
 
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