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  • This comparison shows the changes necessary to convert path
    /socgen/trunk/common/opencores.org/cde/ip/pad/rtl/xml
    from Rev 131 to Rev 133
    Reverse comparison

Rev 131 → Rev 133

/cde_pad_se0_dig.xml
0,0 → 1,205
<?xml version="1.0" encoding="UTF-8"?>
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>pad</spirit:name>
<spirit:version>se0_dig</spirit:version> <spirit:configuration>default</spirit:configuration>
 
 
 
<spirit:busInterfaces>
 
<spirit:busInterface><spirit:name>pad_ring</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="ring"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="ring"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>PAD_io</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>PAD</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
 
</spirit:portMaps>
</spirit:busInterface>
 
 
 
<spirit:busInterface><spirit:name>pad</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="rtl"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_out</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>pad_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_oe</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>pad_oe</spirit:name></spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_in</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>pad_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
 
</spirit:portMaps>
</spirit:busInterface>
 
</spirit:busInterfaces>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
 
 
</spirit:views>
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
 
<spirit:ports>
 
<spirit:port><spirit:name>PAD</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>inout</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>pad_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>pad_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>pad_oe</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
 
 
 
 
</spirit:ports>
 
</spirit:model>
 
 
 
 
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
 
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
 
 
 
</spirit:component>

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