OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/cde/ip/sram/doc
    from Rev 134 to Rev 135
    ↔ Reverse comparison
  •

Rev 134 → Rev 135

/Geda/sch/cde_sram_def.sch File deleted
/Geda/sch/cde_sram_byte.sch File deleted
/Geda/sch/cde_sram_dp.sch File deleted
/Geda/sch/cde_sram_be.sch File deleted
/Geda/sch/cde_sram_word.sch File deleted
/Geda/png/cde_sram_dp_sch.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Geda/png/cde_sram_dp_sch.png
Geda/png/cde_sram_dp_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/cde_sram_be_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/cde_sram_be_sch.png =================================================================== --- Geda/png/cde_sram_be_sch.png (revision 134) +++ Geda/png/cde_sram_be_sch.png (nonexistent)
Geda/png/cde_sram_be_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/cde_sram_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/cde_sram_def_sym.png =================================================================== --- Geda/png/cde_sram_def_sym.png (revision 134) +++ Geda/png/cde_sram_def_sym.png (nonexistent)
Geda/png/cde_sram_def_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/cde_sram_dp_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/cde_sram_dp_sym.png =================================================================== --- Geda/png/cde_sram_dp_sym.png (revision 134) +++ Geda/png/cde_sram_dp_sym.png (nonexistent)
Geda/png/cde_sram_dp_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/cde_sram_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/cde_sram_def_sch.png =================================================================== --- Geda/png/cde_sram_def_sch.png (revision 134) +++ Geda/png/cde_sram_def_sch.png (nonexistent)
Geda/png/cde_sram_def_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/png/cde_sram_be_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Geda/png/cde_sram_be_sym.png =================================================================== --- Geda/png/cde_sram_be_sym.png (revision 134) +++ Geda/png/cde_sram_be_sym.png (nonexistent)
Geda/png/cde_sram_be_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: Geda/html/cde_sram_byte.html =================================================================== --- Geda/html/cde_sram_byte.html (revision 134) +++ Geda/html/cde_sram_byte.html (nonexistent) @@ -1,191 +0,0 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- - - -
-
-
-

Parameters

-
-
- - - - - - - - - -
Name
default
Description
-


-

-


-

-


-

-


-
-

-

Interface 
-

-

-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NAME
Type
Description
addr[ADDR-1:0 ]
input
Memory address bits
be
input
Active high byte enable
clk
input
Active high clock
cs
input
Active high chip select
rd
input
Active high read enable
rdata[7:0 ]
output
read data out
wdata[7:0 ]
input
write data in
wr
input
Active high write enable
-


-

-

Children

-
- - - - - - - - - - - -
Instance
Vendor
Library
Component
Version
-


-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Index: Geda/html/cde_sram_dp.html =================================================================== --- Geda/html/cde_sram_dp.html (revision 134) +++ Geda/html/cde_sram_dp.html (nonexistent) @@ -1,191 +0,0 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- - - -
-
-
-

Parameters

-
-
- - - - - - - - - -
Name
default
Description
-


-

-


-

-


-

-


-
-

-

Interface 
-

-

-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NAME
Type
Description
clk
input
Active high clock
cs
input
Active high chip select
raddr[ADDR-1:0 ]
input
Memory read address bits
rd
input
Active high read enable
rdata[WIDTH-1:0 ]
output
read data out
waddr[ADDR-1:0 ]
input
Memory write address bits
wdata[WIDTH-1:0 ]
input
write data in
wr
input
Active high write enable
-


-

-

Children

-
- - - - - - - - - - - -
Instance
Vendor
Library
Component
Version
-


-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Index: Geda/html/cde_sram_be.html =================================================================== --- Geda/html/cde_sram_be.html (revision 134) +++ Geda/html/cde_sram_be.html (nonexistent) @@ -1,216 +0,0 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- - - -
-
-
-

Parameters

-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Name
default
Description
ADDR
0
Number of address bits
WIDTH
8
Number of data bits
WORDS
0
Number of memory words. Must be fully addressable by ADDR address bits
WRITETHRU
0
If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new
-


-

-


-

-


-

-


-
-

-

Interface 
-

-

-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NAME
Type
Description
addr[ADDR-1:0 ]
input
Memory address bits
be
input
Active high byte enable
clk
input
Active high clock
cs
input
Active high chip select
rd
input
Active high read enable
rdata[WIDTH-1:0 ]
output
read data out
wdata[WIDTH-1:0 ]
input
write data in
wr
input
Active high write enable
-


-

-

Children

-
- - - - - - - - - - - -
Instance
Vendor
Library
Component
Version
-


-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Index: Geda/html/cde_sram_word.html =================================================================== --- Geda/html/cde_sram_word.html (revision 134) +++ Geda/html/cde_sram_word.html (nonexistent) @@ -1,191 +0,0 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- - - -
-
-
-

Parameters

-
-
- - - - - - - - - -
Name
default
Description
-


-

-


-

-


-

-


-
-

-

Interface 
-

-

-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NAME
Type
Description
addr[ADDR:1 ]
input
Memory address bits
be[1:0 ]
input
Active high byte enable
clk
input
Active high clock
cs
input
Active high chip select
rd
input
Active high read enable
rdata[15:0 ]
output
read data out
wdata[15:0 ]
input
write data in
wr
input
Active high write enable
-


-

-

Children

-
- - - - - - - - - - - -
Instance
Vendor
Library
Component
Version
-


-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Index: Geda/html/cde_sram_def.html =================================================================== --- Geda/html/cde_sram_def.html (revision 134) +++ Geda/html/cde_sram_def.html (nonexistent) @@ -1,185 +0,0 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- - - -
-
-
-

Parameters

-
-
- - - - - - - - - -
Name
default
Description
-


-

-


-

-


-

-


-
-

-

Interface 
-

-

-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NAME
Type
Description
addr[ADDR-1:0 ]
input
Memory address bits
clk
input
Active high clock
cs
input
Active high chip select
rd
input
Active high read enable
rdata[WIDTH-1:0 ]
output
read data out
wdata[WIDTH-1:0 ]
input
write data in
wr
input
Active high write enable
-


-

-

Children

-
- - - - - - - - - - - -
Instance
Vendor
Library
Component
Version
-


-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Index: Geda/src/cde_sram_def.v =================================================================== --- Geda/src/cde_sram_def.v (revision 134) +++ Geda/src/cde_sram_def.v (nonexistent) @@ -1,77 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - module - cde_sram_def - #( parameter - ADDR=10, - WIDTH=8, - WORDS=1024, - WRITETHRU=0 - ) - ( - input wire clk, - input wire cs, - input wire rd, - input wire wr, - input wire [ ADDR-1 : 0] addr, - input wire [ WIDTH-1 : 0] wdata, - output reg [ WIDTH-1 : 0] rdata); -// Memory Array -reg [WIDTH-1:0] mem[0:WORDS-1]; -// If used as Rom then load a memory image at startup -initial - begin - $display("SRAM def %m.mem"); - $display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); - end - -// Write function -always@(posedge clk) - if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; -generate -if( WRITETHRU) - begin - // Read function gets new data if also a write cycle - // latch the read addr for next cycle - reg [ADDR-1:0] l_raddr; - reg l_cycle; - - always@(posedge clk) - begin - l_raddr <= addr; - l_cycle <= rd && cs ; - end - - // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block - wire [WIDTH-1:0] tmp_rdata; - assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; - - always@(*) rdata = tmp_rdata; - end -else - begin - // Read function gets old data if also a write cycle - always@(posedge clk) - if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; - else rdata <= {WIDTH{1'b1}}; - end -endgenerate - endmodule Index: Geda/src/cde_sram_dp.v =================================================================== --- Geda/src/cde_sram_dp.v (revision 134) +++ Geda/src/cde_sram_dp.v (nonexistent) @@ -1,77 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - module - cde_sram_dp - #( parameter - ADDR=10, - WIDTH=8, - WORDS=1024, - WRITETHRU=0 - ) - ( - input wire clk, - input wire cs, - input wire rd, - input wire wr, - input wire [ ADDR-1 : 0] raddr, - input wire [ ADDR-1 : 0] waddr, - input wire [ WIDTH-1 : 0] wdata, - output reg [ WIDTH-1 : 0] rdata); -// Memory Array -reg [WIDTH-1:0] mem[0:WORDS-1]; -// If used as Rom then load a memory image at startup -initial - begin - $display("SRAM dp %m.mem"); - $display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); - end - -// Write function -always@(posedge clk) - if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; -generate -if( WRITETHRU) - begin - // Read function gets new data if also a write cycle - // latch the read addr for next cycle - reg [ADDR-1:0] l_raddr; - reg l_cycle; - - always@(posedge clk) - begin - l_raddr <= raddr; - l_cycle <= rd && cs ; - end - - // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block - wire [WIDTH-1:0] tmp_rdata; - assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; - always@(*) rdata = tmp_rdata; - end -else - begin - // Read function gets old data if also a write cycle - always@(posedge clk) - if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; - else rdata <= {WIDTH{1'b1}}; - end -endgenerate - endmodule Index: Geda/src/cde_sram_byte.v =================================================================== --- Geda/src/cde_sram_byte.v (revision 134) +++ Geda/src/cde_sram_byte.v (nonexistent) @@ -1,80 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012-2015 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - module - cde_sram_byte - #( parameter - ADDR=10, - WORDS=1024, - WRITETHRU=0 - ) - ( - - input wire clk, - input wire cs, - input wire rd, - input wire wr, - input wire be, - - input wire [ ADDR-1 : 0] addr, - input wire [ 7 : 0] wdata, - output reg [ 7 : 0] rdata); -// Memory Array -reg [7:0] mem[0:WORDS-1]; - -initial - begin - $display("SRAM byte %m.mem"); - $display(" AddrBits=%d DataBits = 8 Words = %d ",ADDR,WORDS); - end - -// Write function -always@(posedge clk) - if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[7:0]; -generate -if( WRITETHRU) - begin - // Read function gets new data if also a write cycle - // latch the read addr for next cycle - reg [ADDR-1:0] l_raddr; - reg l_cycle; - - always@(posedge clk) - begin - l_raddr <= addr; - l_cycle <= rd && cs ; - end - - - // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block - - wire [7:0] tmp_rdata; - assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff; - always@(*) rdata = tmp_rdata; - end -else - begin - // Read function gets old data if also a write cycle - always@(posedge clk) - if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; - else rdata <= 8'hff; - end -endgenerate - endmodule Index: Geda/src/cde_sram_be.v =================================================================== --- Geda/src/cde_sram_be.v (revision 134) +++ Geda/src/cde_sram_be.v (nonexistent) @@ -1,81 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - module - cde_sram_be - #( parameter - ADDR=10, - WIDTH=8, - WORDS=1024, - WRITETHRU=0 - ) - ( - - input wire clk, - input wire cs, - input wire rd, - input wire wr, - input wire be, - - input wire [ ADDR-1 : 0] addr, - input wire [ WIDTH-1 : 0] wdata, - output reg [ WIDTH-1 : 0] rdata); -// Memory Array -reg [WIDTH-1:0] mem[0:WORDS-1]; -// If used as Rom then load a memory image at startup -initial - begin - $display("SRAM be %m.mem"); - $display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); - end - -// Write function -always@(posedge clk) - if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; -generate -if( WRITETHRU) - begin - // Read function gets new data if also a write cycle - // latch the read addr for next cycle - reg [ADDR-1:0] l_raddr; - reg l_cycle; - - always@(posedge clk) - begin - l_raddr <= addr; - l_cycle <= rd && cs ; - end - - - // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block - - wire [7:0] tmp_rdata; - assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; - always@(*) rdata = tmp_rdata; - end -else - begin - // Read function gets old data if also a write cycle - always@(posedge clk) - if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; - else rdata <= {WIDTH{1'b1}; - end -endgenerate - endmodule Index: Geda/src/cde_sram_word.v =================================================================== --- Geda/src/cde_sram_word.v (revision 134) +++ Geda/src/cde_sram_word.v (nonexistent) @@ -1,85 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - module - cde_sram_word - #( parameter - ADDR=10, - WORDS=1024, - WRITETHRU=0 - ) - ( - input wire clk, - input wire cs, - input wire rd, - input wire wr, - input wire [ ADDR : 1] addr, - input wire [ 15 : 0] wdata, - input wire [ 1 : 0] be, - output reg [ 15 : 0] rdata); -// Memory Array -reg [7:0] meml[0:WORDS-1]; -reg [7:0] memh[0:WORDS-1]; -// If used as Rom then load a memory image at startup -initial - begin - $display("SRAM def %m.mem"); - $display(" AddrBits=%d DataBits = 16 Words = %d ",ADDR,WORDS); - end - -// Write function -always@(posedge clk) - if( wr && cs && be[0]) meml[addr[ADDR:1]] <= wdata[7:0]; - - - - always@(posedge clk) - if( wr && cs && be[1]) memh[addr[ADDR:1]] <= wdata[15:8]; - - - -generate -if( WRITETHRU) - begin - // Read function gets new data if also a write cycle - // latch the read addr for next cycle - reg [ADDR:1] l_raddr; - reg l_cycle; - - always@(posedge clk) - begin - l_raddr <= addr; - l_cycle <= rd && cs ; - end - - // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block - wire [15:0] tmp_rdata; - assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:16'hffff; - always@(*) rdata = tmp_rdata; - end -else - begin - // Read function gets old data if also a write cycle - always@(posedge clk) - if( rd && cs ) rdata <= {memh[{addr[ADDR:1]}],meml[{addr[ADDR:1]}]} ; - else rdata <= 16'hffff; - end -endgenerate - endmodule Index: Geda/sym/cde_sram_dp.sym =================================================================== --- Geda/sym/cde_sram_dp.sym (revision 134) +++ Geda/sym/cde_sram_dp.sym (nonexistent) @@ -1,62 +0,0 @@ -v 20100214 1 -B 300 0 3600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1850 5 10 1 1 0 0 1 1 -device=cde_sram_dp -T 400 2050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=wdata[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=waddr[ADDR-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 10 1 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=raddr[ADDR-1:0] -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=wr -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=rd -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=cs -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} -P 3900 200 4200 200 10 1 1 -{ -T 3800 200 5 10 1 1 0 7 1 1 -pinnumber=rdata[WIDTH-1:0] -T 3800 200 5 10 0 1 0 7 1 1 -pinseq=8 -} Index: Geda/sym/cde_sram_byte.sym =================================================================== --- Geda/sym/cde_sram_byte.sym (revision 134) +++ Geda/sym/cde_sram_byte.sym (nonexistent) @@ -1,62 +0,0 @@ -v 20100214 1 -B 300 0 2800 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1850 5 10 1 1 0 0 1 1 -device=cde_sram_byte -T 400 2050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=wdata[7:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=addr[ADDR-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=wr -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=rd -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=cs -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=be -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} -P 3100 200 3400 200 10 1 1 -{ -T 3000 200 5 10 1 1 0 7 1 1 -pinnumber=rdata[7:0] -T 3000 200 5 10 0 1 0 7 1 1 -pinseq=8 -} Index: Geda/sym/cde_sram_be.sym =================================================================== --- Geda/sym/cde_sram_be.sym (revision 134) +++ Geda/sym/cde_sram_be.sym (nonexistent) @@ -1,62 +0,0 @@ -v 20100214 1 -B 300 0 3600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1850 5 10 1 1 0 0 1 1 -device=cde_sram_be -T 400 2050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=wdata[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=addr[ADDR-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=wr -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=rd -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=cs -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=be -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} -P 3900 200 4200 200 10 1 1 -{ -T 3800 200 5 10 1 1 0 7 1 1 -pinnumber=rdata[WIDTH-1:0] -T 3800 200 5 10 0 1 0 7 1 1 -pinseq=8 -} Index: Geda/sym/cde_sram_word.sym =================================================================== --- Geda/sym/cde_sram_word.sym (revision 134) +++ Geda/sym/cde_sram_word.sym (nonexistent) @@ -1,62 +0,0 @@ -v 20100214 1 -B 300 0 2900 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1850 5 10 1 1 0 0 1 1 -device=cde_sram_word -T 400 2050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=wdata[15:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=be[1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 10 1 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=addr[ADDR-1:0] -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=wr -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=rd -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=cs -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 300 1400 0 1400 4 0 1 -{ -T 400 1400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1400 5 10 0 1 0 1 1 1 -pinseq=7 -} -P 3200 200 3500 200 10 1 1 -{ -T 3100 200 5 10 1 1 0 7 1 1 -pinnumber=rdata[15:0] -T 3100 200 5 10 0 1 0 7 1 1 -pinseq=8 -} Index: Geda/sym/cde_sram_def.sym =================================================================== --- Geda/sym/cde_sram_def.sym (revision 134) +++ Geda/sym/cde_sram_def.sym (nonexistent) @@ -1,55 +0,0 @@ -v 20100214 1 -B 300 0 3600 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1650 5 10 1 1 0 0 1 1 -device=cde_sram_def -T 400 1850 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=wdata[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 10 1 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=addr[ADDR-1:0] -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=wr -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 300 800 0 800 4 0 1 -{ -T 400 800 5 10 1 1 0 1 1 1 -pinnumber=rd -T 400 800 5 10 0 1 0 1 1 1 -pinseq=4 -} -P 300 1000 0 1000 4 0 1 -{ -T 400 1000 5 10 1 1 0 1 1 1 -pinnumber=cs -T 400 1000 5 10 0 1 0 1 1 1 -pinseq=5 -} -P 300 1200 0 1200 4 0 1 -{ -T 400 1200 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 1200 5 10 0 1 0 1 1 1 -pinseq=6 -} -P 3900 200 4200 200 10 1 1 -{ -T 3800 200 5 10 1 1 0 7 1 1 -pinnumber=rdata[WIDTH-1:0] -T 3800 200 5 10 0 1 0 7 1 1 -pinseq=7 -} Index: html/cde_sram_byte.html =================================================================== --- html/cde_sram_byte.html (revision 134) +++ html/cde_sram_byte.html (revision 135) @@ -1,111 +1,198 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- -
-
-

Theory of Operation

-Add description of how it works
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
ADDR
8

WORDS
256

WRITETHRU
1

+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
be
input

clk
input

cs
input

rd
input

wr
input

addr[ADDR-1:0]
input

wdata[7:0]
input

rdata[7:0]
output

+


+

+

Children

+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: html/cde_sram_def.html =================================================================== --- html/cde_sram_def.html (revision 134) +++ html/cde_sram_def.html (revision 135) @@ -1,47 +1,203 @@ - - - - - start - - - - - - - - - - - - -

SOCGEN Datasheet:

-
- -
-



-

-

Theory of -Operation

-

The synchronous ram modules provide a variety of memory storage -options.
Both reads and writes are synchronous to the rising edge -of clk.
Memory may be initialized from a bit file and later -overwritten by memory writes.
If WRITETHRU is set to 1 then a -simultaneous read/write to the same address will read the new data. -
If set to 0 it will return the old. - - - -

















































































-

- - + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
ADDR
8

WIDTH
8

WORDS
256

WRITETHRU
1

+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
be
input

clk
input

cs
input

rd
input

wr
input

addr[ ADDR-1:0]
input

wdata[ WIDTH-1:0]
input

rdata[ WIDTH-1:0]
output

+


+

+

Children

+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: html/cde_sram_dp.html =================================================================== --- html/cde_sram_dp.html (revision 134) +++ html/cde_sram_dp.html (revision 135) @@ -1,43 +1,203 @@ - - - - - start - - - - - - - - - - - - -

SOCGEN Datasheet:

-
- -
-



-

-

Theory of -Operation

-

The synchronous ram modules provide a variety of memory storage -options.
Both reads and writes are synchronous to the rising edge -of clk.
Memory may be initialized from a bit file and later -overwritten by memory writes.
If WRITETHRU is set to 1 then a -simultaneous read/write to the same address will read the new data. -
If set to 0 it will return the old.



















































































-

- - + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
ADDR
8

WIDTH
8

WORDS
256

WRITETHRU
1

+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
clk
input

cs
input

rd
input

wr
input

raddr[ADDR-1:0]
input

waddr[ADDR-1:0]
input

wdata[WIDTH-1:0]
input

rdata[WIDTH-1:0]
output

+


+

+

Children

+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: html/cde_sram_word.html =================================================================== --- html/cde_sram_word.html (revision 134) +++ html/cde_sram_word.html (revision 135) @@ -1,111 +1,198 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
-

-
- -
-
-

Theory of Operation

-Add description of how it works
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
ADDR
8

WORDS
256

WRITETHRU
1

+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
clk
input

cs
input

rd
input

wr
input

addr[ADDR:1]
input

be[1:0]
input

wdata[15:0]
input

rdata[15:0]
output

+


+

+

Children

+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: png/cde_sram_byte_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_byte_sch.png =================================================================== --- png/cde_sram_byte_sch.png (nonexistent) +++ png/cde_sram_byte_sch.png (revision 135)
png/cde_sram_byte_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_byte_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_byte_sym.png =================================================================== --- png/cde_sram_byte_sym.png (nonexistent) +++ png/cde_sram_byte_sym.png (revision 135)
png/cde_sram_byte_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_def_sch.png =================================================================== --- png/cde_sram_def_sch.png (nonexistent) +++ png/cde_sram_def_sch.png (revision 135)
png/cde_sram_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_def_sym.png =================================================================== --- png/cde_sram_def_sym.png (nonexistent) +++ png/cde_sram_def_sym.png (revision 135)
png/cde_sram_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_dp_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_dp_sch.png =================================================================== --- png/cde_sram_dp_sch.png (nonexistent) +++ png/cde_sram_dp_sch.png (revision 135)
png/cde_sram_dp_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_dp_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_dp_sym.png =================================================================== --- png/cde_sram_dp_sym.png (nonexistent) +++ png/cde_sram_dp_sym.png (revision 135)
png/cde_sram_dp_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_word_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_word_sch.png =================================================================== --- png/cde_sram_word_sch.png (nonexistent) +++ png/cde_sram_word_sch.png (revision 135)
png/cde_sram_word_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: png/cde_sram_word_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: png/cde_sram_word_sym.png =================================================================== --- png/cde_sram_word_sym.png (nonexistent) +++ png/cde_sram_word_sym.png (revision 135)
png/cde_sram_word_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sch/cde_sram_byte.sch =================================================================== --- sch/cde_sram_byte.sch (nonexistent) +++ sch/cde_sram_byte.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1600 300 1 0 0 in_port_vector.sym +{ +T 1600 300 5 10 1 1 0 6 1 1 +refdes=wdata[7:0] +} +C 1600 700 1 0 0 in_port_vector.sym +{ +T 1600 700 5 10 1 1 0 6 1 1 +refdes=addr[ADDR-1:0] +} +C 1600 1100 1 0 0 in_port.sym +{ +T 1600 1100 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1600 1500 1 0 0 in_port.sym +{ +T 1600 1500 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1600 1900 1 0 0 in_port.sym +{ +T 1600 1900 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1600 2300 1 0 0 in_port.sym +{ +T 1600 2300 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1600 2700 1 0 0 in_port.sym +{ +T 1600 2700 5 10 1 1 0 6 1 1 +refdes=be +} +C 3900 300 1 0 0 out_port_vector.sym +{ +T 4900 300 5 10 1 1 0 0 1 1 +refdes=rdata[7:0] +} Index: sch/cde_sram_def.sch =================================================================== --- sch/cde_sram_def.sch (nonexistent) +++ sch/cde_sram_def.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1900 300 1 0 0 in_port_vector.sym +{ +T 1900 300 5 10 1 1 0 6 1 1 +refdes=wdata[ WIDTH-1:0] +} +C 1900 700 1 0 0 in_port_vector.sym +{ +T 1900 700 5 10 1 1 0 6 1 1 +refdes=addr[ ADDR-1:0] +} +C 1900 1100 1 0 0 in_port.sym +{ +T 1900 1100 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1900 1500 1 0 0 in_port.sym +{ +T 1900 1500 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1900 1900 1 0 0 in_port.sym +{ +T 1900 1900 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1900 2300 1 0 0 in_port.sym +{ +T 1900 2300 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1900 2700 1 0 0 in_port.sym +{ +T 1900 2700 5 10 1 1 0 6 1 1 +refdes=be +} +C 4900 300 1 0 0 out_port_vector.sym +{ +T 5900 300 5 10 1 1 0 0 1 1 +refdes=rdata[ WIDTH-1:0] +} Index: sch/cde_sram_dp.sch =================================================================== --- sch/cde_sram_dp.sch (nonexistent) +++ sch/cde_sram_dp.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1800 300 1 0 0 in_port_vector.sym +{ +T 1800 300 5 10 1 1 0 6 1 1 +refdes=wdata[WIDTH-1:0] +} +C 1800 700 1 0 0 in_port_vector.sym +{ +T 1800 700 5 10 1 1 0 6 1 1 +refdes=waddr[ADDR-1:0] +} +C 1800 1100 1 0 0 in_port_vector.sym +{ +T 1800 1100 5 10 1 1 0 6 1 1 +refdes=raddr[ADDR-1:0] +} +C 1800 1500 1 0 0 in_port.sym +{ +T 1800 1500 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1800 1900 1 0 0 in_port.sym +{ +T 1800 1900 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1800 2300 1 0 0 in_port.sym +{ +T 1800 2300 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1800 2700 1 0 0 in_port.sym +{ +T 1800 2700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 4700 300 1 0 0 out_port_vector.sym +{ +T 5700 300 5 10 1 1 0 0 1 1 +refdes=rdata[WIDTH-1:0] +} Index: sch/cde_sram_word.sch =================================================================== --- sch/cde_sram_word.sch (nonexistent) +++ sch/cde_sram_word.sch (revision 135) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1400 300 1 0 0 in_port_vector.sym +{ +T 1400 300 5 10 1 1 0 6 1 1 +refdes=wdata[15:0] +} +C 1400 700 1 0 0 in_port_vector.sym +{ +T 1400 700 5 10 1 1 0 6 1 1 +refdes=be[1:0] +} +C 1400 1100 1 0 0 in_port_vector.sym +{ +T 1400 1100 5 10 1 1 0 6 1 1 +refdes=addr[ADDR:1] +} +C 1400 1500 1 0 0 in_port.sym +{ +T 1400 1500 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1400 1900 1 0 0 in_port.sym +{ +T 1400 1900 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1400 2300 1 0 0 in_port.sym +{ +T 1400 2300 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1400 2700 1 0 0 in_port.sym +{ +T 1400 2700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 3800 300 1 0 0 out_port_vector.sym +{ +T 4800 300 5 10 1 1 0 0 1 1 +refdes=rdata[15:0] +} Index: sym/cde_sram_byte.sym =================================================================== --- sym/cde_sram_byte.sym (nonexistent) +++ sym/cde_sram_byte.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 2800 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=cde_sram_byte +T 400 2050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2200 0 10 0 1 0 0 1 1 +library=cde +T 400 2200 0 10 0 1 0 0 1 1 +component=sram +T 400 2200 0 10 0 1 0 0 1 1 +version=byte +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[7:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=addr[ADDR-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=be +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 3100 200 3400 200 10 1 1 +{ +T 3000 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[7:0] +T 3000 200 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: sym/cde_sram_def.sym =================================================================== --- sym/cde_sram_def.sym (nonexistent) +++ sym/cde_sram_def.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 3800 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=cde_sram_def +T 400 2050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2200 0 10 0 1 0 0 1 1 +library=cde +T 400 2200 0 10 0 1 0 0 1 1 +component=sram +T 400 2200 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[ WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=addr[ ADDR-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=be +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 4100 200 4400 200 10 1 1 +{ +T 4000 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[ WIDTH-1:0] +T 4000 200 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: sym/cde_sram_dp.sym =================================================================== --- sym/cde_sram_dp.sym (nonexistent) +++ sym/cde_sram_dp.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 3600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=cde_sram_dp +T 400 2050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2200 0 10 0 1 0 0 1 1 +library=cde +T 400 2200 0 10 0 1 0 0 1 1 +component=sram +T 400 2200 0 10 0 1 0 0 1 1 +version=dp +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=waddr[ADDR-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=raddr[ADDR-1:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 3900 200 4200 200 10 1 1 +{ +T 3800 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[WIDTH-1:0] +T 3800 200 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: sym/cde_sram_word.sym =================================================================== --- sym/cde_sram_word.sym (nonexistent) +++ sym/cde_sram_word.sym (revision 135) @@ -0,0 +1,70 @@ +v 20100214 1 +B 300 0 2700 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=cde_sram_word +T 400 2050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 2200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 2200 0 10 0 1 0 0 1 1 +library=cde +T 400 2200 0 10 0 1 0 0 1 1 +component=sram +T 400 2200 0 10 0 1 0 0 1 1 +version=word +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[15:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=be[1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=addr[ADDR:1] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 3000 200 3300 200 10 1 1 +{ +T 2900 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[15:0] +T 2900 200 5 10 0 1 0 7 1 1 +pinseq=8 +}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.