URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/cde/ip/sram/rtl/xml
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/sram_be.xml
File deleted
/sram_word.design.xml
File deleted
/sram_def.xml
63,9 → 63,57
</spirit:busInterfaces> |
|
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
117,14 → 165,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
168,15 → 208,44
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
188,10 → 257,23
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
207,7 → 289,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/sram_byte.xml
16,15 → 16,60
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_byte</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
78,14 → 123,6
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{8'bxxxxxxxx}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
146,13 → 183,40
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
162,8 → 226,25
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
177,7 → 258,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/sram_dp.xml
16,15 → 16,54
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_dp</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
71,18 → 110,7
|
|
|
<spirit:modelParameters> |
|
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
|
</spirit:modelParameters> |
|
|
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
144,44 → 172,63
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:name>fs-sim</spirit:name> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
190,12 → 237,16
|
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
/sram_word.xml
108,9 → 108,53
</spirit:busInterfaces> |
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_word</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
162,13 → 206,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
181,7 → 218,7
<spirit:port><spirit:name>addr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:vector><spirit:left>ADDR</spirit:left><spirit:right>1</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
218,15 → 255,42
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
238,10 → 302,24
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
257,7 → 335,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|