URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common/opencores.org/cde/ip/sram/rtl
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/xml/sram_be.xml
File deleted
/xml/sram_word.design.xml
File deleted
/xml/sram_def.xml
63,9 → 63,57
</spirit:busInterfaces> |
|
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
117,14 → 165,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
168,15 → 208,44
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
188,10 → 257,23
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
207,7 → 289,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/xml/sram_byte.xml
16,15 → 16,60
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_byte</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
78,14 → 123,6
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{8'bxxxxxxxx}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
146,13 → 183,40
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
162,8 → 226,25
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
177,7 → 258,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/xml/sram_dp.xml
16,15 → 16,54
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_dp</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
71,18 → 110,7
|
|
|
<spirit:modelParameters> |
|
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
|
</spirit:modelParameters> |
|
|
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
144,44 → 172,63
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:name>fs-sim</spirit:name> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
190,12 → 237,16
|
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
/xml/sram_word.xml
108,9 → 108,53
</spirit:busInterfaces> |
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_word</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
162,13 → 206,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
181,7 → 218,7
<spirit:port><spirit:name>addr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:vector><spirit:left>ADDR</spirit:left><spirit:right>1</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
218,15 → 255,42
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
238,10 → 302,24
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
257,7 → 335,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/verilog/sram_be.v
File deleted
/verilog/sram_def
0,0 → 1,41
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
$display("SRAM def %m.mem"); |
$display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
|
|
/verilog/sram_word.v
23,9 → 23,8
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={16'hffff}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
55,12 → 54,6
if( wr && cs && be[1]) memh[addr[ADDR:1]] <= wdata[15:8]; |
|
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR:1] l_raddr; |
reg l_cycle; |
|
70,9 → 63,17
l_cycle <= rd && cs ; |
end |
|
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [15:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:DEFAULT; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:16'hffff; |
always@(*) rdata = tmp_rdata; |
end |
else |
80,7 → 81,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= {memh[{addr[ADDR:1]}],meml[{addr[ADDR:1]}]} ; |
else rdata <= DEFAULT; |
else rdata <= 16'hffff; |
end |
endgenerate |
endmodule |
/verilog/sram_def.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
47,11 → 46,8
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
61,9 → 57,16
l_cycle <= rd && cs ; |
end |
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
71,7 → 74,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/verilog/sram_dp
0,0 → 1,50
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
$display("SRAM dp %m.mem"); |
$display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); |
end |
|
|
|
|
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
|
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= raddr; |
l_cycle <= rd && cs ; |
end |
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
|
|
/verilog/sram_byte
0,0 → 1,44
// Memory Array |
reg [7:0] mem[0:WORDS-1]; |
|
initial |
begin |
$display("SRAM byte %m.mem"); |
$display(" AddrBits=%d DataBits = 8 Words = %d ",ADDR,WORDS); |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[7:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= 8'hff; |
end |
endgenerate |
|
|
|
/verilog/lint/sram_be.v
File deleted
/verilog/lint/sram_word.v
23,9 → 23,8
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={16'hffff}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
38,7 → 37,7
|
always@(posedge clk) |
if( rd && cs ) rdata <= wdata ; |
else rdata <= DEFAULT; |
else rdata <= 16'hffff; |
|
|
endmodule |
/verilog/lint/sram_def.v
4,10 → 4,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
19,5 → 17,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/verilog/lint/sram_byte.v
3,11 → 3,9
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}} |
WRITETHRU=0 |
) |
( |
input wire be, |
input wire clk, |
input wire cs, |
input wire be, |
19,5 → 17,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= 8'hff; |
endmodule |
/verilog/lint/sram_dp.v
4,10 → 4,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
20,5 → 18,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/verilog/sram_byte.v
23,8 → 23,7
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT=8'bxxxxxxxx |
WRITETHRU=0 |
) |
( |
|
49,11 → 48,7
// Write function |
always@(posedge clk) |
if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[7:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
64,10 → 59,18
end |
|
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff; |
always@(*) rdata = tmp_rdata; |
end |
else |
75,7 → 78,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= 8'hff; |
end |
endgenerate |
endmodule |
/verilog/sram_dp.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
48,11 → 47,7
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
62,9 → 57,16
l_cycle <= rd && cs ; |
end |
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
72,7 → 74,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/verilog/sram_word
0,0 → 1,55
// Memory Array |
reg [7:0] meml[0:WORDS-1]; |
reg [7:0] memh[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
$display("SRAM def %m.mem"); |
$display(" AddrBits=%d DataBits = 16 Words = %d ",ADDR,WORDS); |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs && be[0]) meml[addr[ADDR:1]] <= wdata[7:0]; |
|
|
|
always@(posedge clk) |
if( wr && cs && be[1]) memh[addr[ADDR:1]] <= wdata[15:8]; |
|
|
|
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR:1] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
|
|
generate |
if( WRITETHRU) |
begin |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [15:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:16'hffff; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= {memh[{addr[ADDR:1]}],meml[{addr[ADDR:1]}]} ; |
else rdata <= 16'hffff; |
end |
endgenerate |
|
|
|