OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/common/opencores.org/cde/ip/sync
    from Rev 134 to Rev 135
    ↔ Reverse comparison
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Rev 134 → Rev 135

/componentCfg.xml
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<socgen:componentConfiguration
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
/doc/Geda/png/cde_sync_def_sch.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
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doc/Geda/png/cde_sync_with_hysteresis_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_sync_with_reset_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_sync_with_reset_sym.png =================================================================== --- doc/Geda/png/cde_sync_with_reset_sym.png (revision 134) +++ doc/Geda/png/cde_sync_with_reset_sym.png (nonexistent)
doc/Geda/png/cde_sync_with_reset_sym.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_sync_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_sync_def_sym.png =================================================================== --- doc/Geda/png/cde_sync_def_sym.png (revision 134) +++ doc/Geda/png/cde_sync_def_sym.png (nonexistent)
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doc/Geda/png/cde_sync_with_hysteresis_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/png/cde_sync_with_reset_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Geda/png/cde_sync_with_reset_sch.png =================================================================== --- doc/Geda/png/cde_sync_with_reset_sch.png (revision 134) +++ doc/Geda/png/cde_sync_with_reset_sch.png (nonexistent)
doc/Geda/png/cde_sync_with_reset_sch.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/Geda/html/cde_sync_with_hysteresis.html =================================================================== --- doc/Geda/html/cde_sync_with_hysteresis.html (revision 134) +++ doc/Geda/html/cde_sync_with_hysteresis.html (nonexistent) @@ -1,197 +0,0 @@ - - - - - start - - - - - - - - - - -

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- - Index: doc/Geda/html/cde_sync_with_reset.html =================================================================== --- doc/Geda/html/cde_sync_with_reset.html (revision 134) +++ doc/Geda/html/cde_sync_with_reset.html (nonexistent) @@ -1,179 +0,0 @@ - - - - - start - - - - - - - - - - -

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- - Index: doc/Geda/html/cde_sync_def.html =================================================================== --- doc/Geda/html/cde_sync_def.html (revision 134) +++ doc/Geda/html/cde_sync_def.html (nonexistent) @@ -1,173 +0,0 @@ - - - - - start - - - - - - - - - - -

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- - Index: doc/Geda/src/cde_sync_with_hysteresis.v =================================================================== --- doc/Geda/src/cde_sync_with_hysteresis.v (revision 134) +++ doc/Geda/src/cde_sync_with_hysteresis.v (nonexistent) @@ -1,114 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - - - -module cde_sync_with_hysteresis -#( parameter WIDTH = 1, - parameter DEBOUNCE_SIZE = 4, - parameter DEBOUNCE_DELAY = 4'b1111 - ) - -( - -input wire clk, -input wire reset, - -input wire [WIDTH - 1:0] data_in, -output reg [WIDTH - 1:0] data_out, - -output reg [WIDTH - 1:0] data_rise, -output reg [WIDTH - 1:0] data_fall - - - -); - - -reg [WIDTH - 1:0] hysteresis_data; -reg [WIDTH - 1:0] clean_data; -reg [DEBOUNCE_SIZE-1:0] debounce_counter; - -always@(posedge clk ) - if(reset) - begin - data_out <= data_in; - data_rise <= {WIDTH{1'b0}}; - data_fall <= {WIDTH{1'b0}}; - end - else - begin - data_out <= clean_data; - data_rise <= clean_data &( data_out ^ clean_data); - data_fall <= data_out &( data_out ^ clean_data); - end - - - - - - - - -always@(posedge clk ) - if(reset) - begin - clean_data <= data_in; - hysteresis_data <= data_in; - debounce_counter <= {DEBOUNCE_SIZE{1'b0}}; - end - else - begin - // if the current input data differs from hysteresis - // then reset counter and update hysteresie - - if(data_in != hysteresis_data ) - begin - clean_data <= clean_data; - hysteresis_data <= data_in; - debounce_counter <= {DEBOUNCE_SIZE{1'b0}}; - end - // if counter reaches DEBOUNCE_DELAY then the signal is clean - else - if(debounce_counter == DEBOUNCE_DELAY) - begin - clean_data <= hysteresis_data; - hysteresis_data <= hysteresis_data; - debounce_counter <= debounce_counter; - end - // data_in did not change but counter did not reach limit. Increment counter - else - begin - clean_data <= clean_data; - hysteresis_data <= hysteresis_data; - debounce_counter <= debounce_counter+1; - end - end - - - - - - - - -endmodule - Index: doc/Geda/src/cde_sync_with_reset.v =================================================================== --- doc/Geda/src/cde_sync_with_reset.v (revision 134) +++ doc/Geda/src/cde_sync_with_reset.v (nonexistent) @@ -1,65 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - -module cde_sync_with_reset -#( parameter WIDTH = 1, - parameter DEPTH = 2, - parameter RST_VAL = 1'b0 - ) - -( - -input wire clk, -input wire reset_n, - -input wire [WIDTH - 1:0] data_in, -output wire [WIDTH - 1:0] data_out - - -); - - -reg [WIDTH - 1:0] sync_data [DEPTH:0]; - - -always @(*) - begin - sync_data[0] = data_in; - end - - - -integer i; -always @(posedge clk or negedge reset_n) - if (~reset_n) - begin - for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= RST_VAL; - end - - else - begin - for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= sync_data[i-1]; - end - -assign data_out = sync_data[DEPTH]; - -endmodule - Index: doc/Geda/src/cde_sync_def.v =================================================================== --- doc/Geda/src/cde_sync_def.v (revision 134) +++ doc/Geda/src/cde_sync_def.v (nonexistent) @@ -1,58 +0,0 @@ -/**********************************************************************/ -/* */ -/* */ -/* Copyright (c) 2012 Ouabache Design Works */ -/* */ -/* All Rights Reserved Worldwide */ -/* */ -/* Licensed under the Apache License,Version2.0 (the'License'); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in */ -/* writing, software distributed under the License is */ -/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ -/* OR CONDITIONS OF ANY KIND, either express or implied. */ -/* See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/**********************************************************************/ - - -module cde_sync_def -#( parameter WIDTH = 1, - parameter DEPTH = 2 - ) - -( - -input wire clk, -input wire [WIDTH - 1:0] data_in, -output wire [WIDTH - 1:0] data_out - - -); - - -reg [WIDTH - 1:0] sync_data [DEPTH:0]; - - -always @(*) - begin - sync_data[0] = data_in; - end - - - -integer i; - -always @(posedge clk) - begin - for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= sync_data[i-1]; - end - - -assign data_out = sync_data[DEPTH]; - -endmodule Index: doc/Geda/sym/cde_sync_with_hysteresis.sym =================================================================== --- doc/Geda/sym/cde_sync_with_hysteresis.sym (revision 134) +++ doc/Geda/sym/cde_sync_with_hysteresis.sym (nonexistent) @@ -1,48 +0,0 @@ -v 20100214 1 -B 300 0 4200 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1050 5 10 1 1 0 0 1 1 -device=cde_sync_with_hysteresis -T 400 1250 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=data_in[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=reset -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 4500 200 4800 200 10 1 1 -{ -T 4400 200 5 10 1 1 0 7 1 1 -pinnumber=data_rise[WIDTH-1:0] -T 4400 200 5 10 0 1 0 7 1 1 -pinseq=4 -} -P 4500 400 4800 400 10 1 1 -{ -T 4400 400 5 10 1 1 0 7 1 1 -pinnumber=data_out[WIDTH-1:0] -T 4400 400 5 10 0 1 0 7 1 1 -pinseq=5 -} -P 4500 600 4800 600 10 1 1 -{ -T 4400 600 5 10 1 1 0 7 1 1 -pinnumber=data_fall[WIDTH-1:0] -T 4400 600 5 10 0 1 0 7 1 1 -pinseq=6 -} Index: doc/Geda/sym/cde_sync_with_reset.sym =================================================================== --- doc/Geda/sym/cde_sync_with_reset.sym (revision 134) +++ doc/Geda/sym/cde_sync_with_reset.sym (nonexistent) @@ -1,34 +0,0 @@ -v 20100214 1 -B 300 0 4100 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 1050 5 10 1 1 0 0 1 1 -device=cde_sync_with_reset -T 400 1250 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=data_in[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=reset_n -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 300 600 0 600 4 0 1 -{ -T 400 600 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 600 5 10 0 1 0 1 1 1 -pinseq=3 -} -P 4400 200 4700 200 10 1 1 -{ -T 4300 200 5 10 1 1 0 7 1 1 -pinnumber=data_out[WIDTH-1:0] -T 4300 200 5 10 0 1 0 7 1 1 -pinseq=4 -} Index: doc/Geda/sym/cde_sync_def.sym =================================================================== --- doc/Geda/sym/cde_sync_def.sym (revision 134) +++ doc/Geda/sym/cde_sync_def.sym (nonexistent) @@ -1,27 +0,0 @@ -v 20100214 1 -B 300 0 4100 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 400 850 5 10 1 1 0 0 1 1 -device=cde_sync_def -T 400 1050 8 10 1 1 0 0 1 1 -refdes=U? -P 300 200 0 200 10 1 1 -{ -T 400 200 5 10 1 1 0 1 1 1 -pinnumber=data_in[WIDTH-1:0] -T 400 200 5 10 0 1 0 1 1 1 -pinseq=1 -} -P 300 400 0 400 4 0 1 -{ -T 400 400 5 10 1 1 0 1 1 1 -pinnumber=clk -T 400 400 5 10 0 1 0 1 1 1 -pinseq=2 -} -P 4400 200 4700 200 10 1 1 -{ -T 4300 200 5 10 1 1 0 7 1 1 -pinnumber=data_out[WIDTH-1:0] -T 4300 200 5 10 0 1 0 7 1 1 -pinseq=3 -} Index: doc/Geda/sch/cde_sync_with_hysteresis.sch =================================================================== --- doc/Geda/sch/cde_sync_with_hysteresis.sch (revision 134) +++ doc/Geda/sch/cde_sync_with_hysteresis.sch (nonexistent) @@ -1,31 +0,0 @@ -v 20100214 1 -C 2000 300 1 0 0 in_port_v.sym -{ -T 2000 300 5 10 1 1 0 6 1 1 -refdes=data_in[WIDTH-1:0] -} -C 2000 700 1 0 0 in_port.sym -{ -T 2000 700 5 10 1 1 0 6 1 1 -refdes=reset -} -C 2000 1100 1 0 0 in_port.sym -{ -T 2000 1100 5 10 1 1 0 6 1 1 -refdes=clk -} -C 5300 300 1 0 0 out_port_v.sym -{ -T 6300 300 5 10 1 1 0 0 1 1 -refdes=data_rise[WIDTH-1:0] -} -C 5300 700 1 0 0 out_port_v.sym -{ -T 6300 700 5 10 1 1 0 0 1 1 -refdes=data_out[WIDTH-1:0] -} -C 5300 1100 1 0 0 out_port_v.sym -{ -T 6300 1100 5 10 1 1 0 0 1 1 -refdes=data_fall[WIDTH-1:0] -} Index: doc/Geda/sch/cde_sync_with_reset.sch =================================================================== --- doc/Geda/sch/cde_sync_with_reset.sch (revision 134) +++ doc/Geda/sch/cde_sync_with_reset.sch (nonexistent) @@ -1,21 +0,0 @@ -v 20100214 1 -C 2000 300 1 0 0 in_port_v.sym -{ -T 2000 300 5 10 1 1 0 6 1 1 -refdes=data_in[WIDTH-1:0] -} -C 2000 700 1 0 0 in_port.sym -{ -T 2000 700 5 10 1 1 0 6 1 1 -refdes=reset_n -} -C 2000 1100 1 0 0 in_port.sym -{ -T 2000 1100 5 10 1 1 0 6 1 1 -refdes=clk -} -C 5200 300 1 0 0 out_port_v.sym -{ -T 6200 300 5 10 1 1 0 0 1 1 -refdes=data_out[WIDTH-1:0] -} Index: doc/Geda/sch/cde_sync_def.sch =================================================================== --- doc/Geda/sch/cde_sync_def.sch (revision 134) +++ doc/Geda/sch/cde_sync_def.sch (nonexistent) @@ -1,16 +0,0 @@ -v 20100214 1 -C 2000 300 1 0 0 in_port_v.sym -{ -T 2000 300 5 10 1 1 0 6 1 1 -refdes=data_in[WIDTH-1:0] -} -C 2000 700 1 0 0 in_port.sym -{ -T 2000 700 5 10 1 1 0 6 1 1 -refdes=clk -} -C 5200 300 1 0 0 out_port_v.sym -{ -T 6200 300 5 10 1 1 0 0 1 1 -refdes=data_out[WIDTH-1:0] -} Index: doc/html/cde_sync_def.html =================================================================== --- doc/html/cde_sync_def.html (revision 134) +++ doc/html/cde_sync_def.html (revision 135) @@ -1,224 +1,168 @@ - - - - - start - - - - - - - - - - -

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Theory of Operation

-cde_sync_with_hysteresis is a multistage filter with hystersis. Input -data must be stable for a programable number of clocks before the output -will change. It then requires the same number of clocks before it can -change again -
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SOCGEN Datasheet:
+

+
+ + + +
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Parameters

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
DEBOUNCE_DELAY
4'b1111

DEBOUNCE_SIZE
4

WIDTH
1

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+

Interface 
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+

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NAME
Type
Description
clk
input

reset
input

data_in[WIDTH-1:0]
input

data_fall[WIDTH-1:0]
output

data_out[WIDTH-1:0]
output

data_rise[WIDTH-1:0]
output

+


+

+

Children

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+ + + + + + + + + + + +
Instance
Vendor
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Component
Version
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+ + Index: doc/html/cde_sync_with_reset.html =================================================================== --- doc/html/cde_sync_with_reset.html (revision 134) +++ doc/html/cde_sync_with_reset.html (revision 135) @@ -1,230 +1,178 @@ - - - - - start - - - - - - - - - - -

SOCGEN Datasheet:
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Theory of Operation

-cde_sync_with_reset is a simple multistage metastable filter. Both data -width and the number of stages are set via parameters. All stages may -be reset to the same value using an asynchronous reset -
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- - + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
Name
default
Description
DEPTH
2

RST_VAL
1'b0

WIDTH
1

+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
clk
input

reset_n
input

data_in[WIDTH-1:0]
input

data_out[WIDTH-1:0]
output

+


+

+

Children

+
+ + + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
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+
+ + Index: doc/png/cde_sync_def_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_sync_def_sch.png =================================================================== --- doc/png/cde_sync_def_sch.png (nonexistent) +++ doc/png/cde_sync_def_sch.png (revision 135)
doc/png/cde_sync_def_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_sync_def_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_sync_def_sym.png =================================================================== --- doc/png/cde_sync_def_sym.png (nonexistent) +++ doc/png/cde_sync_def_sym.png (revision 135)
doc/png/cde_sync_def_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_sync_with_hysteresis_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_sync_with_hysteresis_sch.png =================================================================== --- doc/png/cde_sync_with_hysteresis_sch.png (nonexistent) +++ doc/png/cde_sync_with_hysteresis_sch.png (revision 135)
doc/png/cde_sync_with_hysteresis_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_sync_with_hysteresis_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_sync_with_hysteresis_sym.png =================================================================== --- doc/png/cde_sync_with_hysteresis_sym.png (nonexistent) +++ doc/png/cde_sync_with_hysteresis_sym.png (revision 135)
doc/png/cde_sync_with_hysteresis_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_sync_with_reset_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_sync_with_reset_sch.png =================================================================== --- doc/png/cde_sync_with_reset_sch.png (nonexistent) +++ doc/png/cde_sync_with_reset_sch.png (revision 135)
doc/png/cde_sync_with_reset_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/png/cde_sync_with_reset_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/png/cde_sync_with_reset_sym.png =================================================================== --- doc/png/cde_sync_with_reset_sym.png (nonexistent) +++ doc/png/cde_sync_with_reset_sym.png (revision 135)
doc/png/cde_sync_with_reset_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/sch/cde_sync_def.sch =================================================================== --- doc/sch/cde_sync_def.sch (nonexistent) +++ doc/sch/cde_sync_def.sch (revision 135) @@ -0,0 +1,16 @@ +v 20100214 1 +C 2000 300 1 0 0 in_port_vector.sym +{ +T 2000 300 5 10 1 1 0 6 1 1 +refdes=data_in[WIDTH-1:0] +} +C 2000 700 1 0 0 in_port.sym +{ +T 2000 700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 5200 300 1 0 0 out_port_vector.sym +{ +T 6200 300 5 10 1 1 0 0 1 1 +refdes=data_out[WIDTH-1:0] +} Index: doc/sch/cde_sync_with_hysteresis.sch =================================================================== --- doc/sch/cde_sync_with_hysteresis.sch (nonexistent) +++ doc/sch/cde_sync_with_hysteresis.sch (revision 135) @@ -0,0 +1,31 @@ +v 20100214 1 +C 2000 300 1 0 0 in_port_vector.sym +{ +T 2000 300 5 10 1 1 0 6 1 1 +refdes=data_in[WIDTH-1:0] +} +C 2000 700 1 0 0 in_port.sym +{ +T 2000 700 5 10 1 1 0 6 1 1 +refdes=reset +} +C 2000 1100 1 0 0 in_port.sym +{ +T 2000 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 5300 300 1 0 0 out_port_vector.sym +{ +T 6300 300 5 10 1 1 0 0 1 1 +refdes=data_rise[WIDTH-1:0] +} +C 5300 700 1 0 0 out_port_vector.sym +{ +T 6300 700 5 10 1 1 0 0 1 1 +refdes=data_out[WIDTH-1:0] +} +C 5300 1100 1 0 0 out_port_vector.sym +{ +T 6300 1100 5 10 1 1 0 0 1 1 +refdes=data_fall[WIDTH-1:0] +} Index: doc/sch/cde_sync_with_reset.sch =================================================================== --- doc/sch/cde_sync_with_reset.sch (nonexistent) +++ doc/sch/cde_sync_with_reset.sch (revision 135) @@ -0,0 +1,21 @@ +v 20100214 1 +C 2000 300 1 0 0 in_port_vector.sym +{ +T 2000 300 5 10 1 1 0 6 1 1 +refdes=data_in[WIDTH-1:0] +} +C 2000 700 1 0 0 in_port.sym +{ +T 2000 700 5 10 1 1 0 6 1 1 +refdes=reset_n +} +C 2000 1100 1 0 0 in_port.sym +{ +T 2000 1100 5 10 1 1 0 6 1 1 +refdes=clk +} +C 5200 300 1 0 0 out_port_vector.sym +{ +T 6200 300 5 10 1 1 0 0 1 1 +refdes=data_out[WIDTH-1:0] +} Index: doc/sym/cde_sync_def.sym =================================================================== --- doc/sym/cde_sync_def.sym (nonexistent) +++ doc/sym/cde_sync_def.sym (revision 135) @@ -0,0 +1,35 @@ +v 20100214 1 +B 300 0 4100 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 850 5 10 1 1 0 0 1 1 +device=cde_sync_def +T 400 1050 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1200 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1200 0 10 0 1 0 0 1 1 +library=cde +T 400 1200 0 10 0 1 0 0 1 1 +component=sync +T 400 1200 0 10 0 1 0 0 1 1 +version=def +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=data_in[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 4400 200 4700 200 10 1 1 +{ +T 4300 200 5 10 1 1 0 7 1 1 +pinnumber=data_out[WIDTH-1:0] +T 4300 200 5 10 0 1 0 7 1 1 +pinseq=3 +} Index: doc/sym/cde_sync_with_hysteresis.sym =================================================================== --- doc/sym/cde_sync_with_hysteresis.sym (nonexistent) +++ doc/sym/cde_sync_with_hysteresis.sym (revision 135) @@ -0,0 +1,56 @@ +v 20100214 1 +B 300 0 4200 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1050 5 10 1 1 0 0 1 1 +device=cde_sync_with_hysteresis +T 400 1250 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1400 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1400 0 10 0 1 0 0 1 1 +library=cde +T 400 1400 0 10 0 1 0 0 1 1 +component=sync +T 400 1400 0 10 0 1 0 0 1 1 +version=with_hysteresis +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=data_in[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 4500 200 4800 200 10 1 1 +{ +T 4400 200 5 10 1 1 0 7 1 1 +pinnumber=data_rise[WIDTH-1:0] +T 4400 200 5 10 0 1 0 7 1 1 +pinseq=4 +} +P 4500 400 4800 400 10 1 1 +{ +T 4400 400 5 10 1 1 0 7 1 1 +pinnumber=data_out[WIDTH-1:0] +T 4400 400 5 10 0 1 0 7 1 1 +pinseq=5 +} +P 4500 600 4800 600 10 1 1 +{ +T 4400 600 5 10 1 1 0 7 1 1 +pinnumber=data_fall[WIDTH-1:0] +T 4400 600 5 10 0 1 0 7 1 1 +pinseq=6 +} Index: doc/sym/cde_sync_with_reset.sym =================================================================== --- doc/sym/cde_sync_with_reset.sym (nonexistent) +++ doc/sym/cde_sync_with_reset.sym (revision 135) @@ -0,0 +1,42 @@ +v 20100214 1 +B 300 0 4100 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1050 5 10 1 1 0 0 1 1 +device=cde_sync_with_reset +T 400 1250 5 10 1 1 0 0 1 1 +refdes=U? +T 400 1400 0 10 0 1 0 0 1 1 +vendor=opencores.org +T 400 1400 0 10 0 1 0 0 1 1 +library=cde +T 400 1400 0 10 0 1 0 0 1 1 +component=sync +T 400 1400 0 10 0 1 0 0 1 1 +version=with_reset +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=data_in[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=reset_n +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 4400 200 4700 200 10 1 1 +{ +T 4300 200 5 10 1 1 0 7 1 1 +pinnumber=data_out[WIDTH-1:0] +T 4300 200 5 10 0 1 0 7 1 1 +pinseq=4 +} Index: rtl/xml/cde_sync_def.xml =================================================================== --- rtl/xml/cde_sync_def.xml (revision 134) +++ rtl/xml/cde_sync_def.xml (revision 135) @@ -2,45 +2,45 @@ - +xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014 +http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd"> -opencores.org -cde -sync -def default +opencores.org +cde +sync +def - + - - gen_verilog - 104.0 - none - common - ./tools/verilog/gen_verilog - - - destination - sync_def - - - + + gen_verilog + 104.0 + none + :*common:* + tools/verilog/gen_verilog + + + destination + sync_def + + + - + @@ -48,213 +48,239 @@ - + - + + + verilog + verilog + cde_sync_def + + - - verilog - - - - + WIDTH + 8 + + + + fs-sim + + + + + - - commoncommon - Verilog - - - fs-common - - + + rtl + verilog:Kactus2: + verilog + + + + verilog + + + + - - sim:*Simulation:* - Verilog - - - fs-sim - - + + common:*common:* + Verilog + + + fs-common + + - - syn:*Synthesis:* - Verilog - - - fs-syn - - + + sim:*Simulation:* + Verilog + + + fs-sim + + + + syn:*Synthesis:* + Verilog + + + fs-syn + + - - doc - - - - :*Documentation:* - Verilog - + + doc + + + + :*Documentation:* + Verilog + - - -WIDTH1 -DEPTH2 - + - -clk -wire -in - + +WIDTH1 +DEPTH2 + -data_in -wire -in -WIDTH-10 - + -data_out -wire -out -WIDTH-10 - +clk +wire +in + +data_in +wire +in +WIDTH-10 + +data_out +wire +out +WIDTH-10 + - - + + - + - - fs-common - - - ../verilog/sync_def - verilogSourcefragment - + + fs-common + + + ../verilog/sync_def + verilogSourcefragment + - + - - fs-sim - - - ../verilog/copyright - verilogSourceinclude - + + fs-sim - - - ../verilog/common/sync_def - verilogSourcemodule - + + + ../verilog/copyright + verilogSourceinclude + + + + + ../verilog/common/sync_def + verilogSourcemodule + + + - - dest_dir - ../views/sim/ - verilogSourcelibraryDir - + + dest_dir + ../views/sim/ + verilogSourcelibraryDir + - + - - fs-syn + + fs-syn - - - ../verilog/copyright - verilogSourceinclude - + + + ../verilog/copyright + verilogSourceinclude + - - - ../verilog/common/sync_def - verilogSourcemodule - + + + ../verilog/common/sync_def + verilogSourcemodule + - - dest_dir - ../views/syn/ - verilogSourcelibraryDir - + + dest_dir + ../views/syn/ + verilogSourcelibraryDir + - + - - fs-lint + + fs-lint - - dest_dir - ../views/syn/ - verilogSourcelibraryDir - + + dest_dir + ../views/syn/ + verilogSourcelibraryDir + - + - + @@ -265,4 +291,4 @@ - +
/rtl/xml/cde_sync_with_hysteresis.xml
2,256 → 2,279
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
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</ipxact:view>
 
 
<ipxact:view>
<ipxact:name>doc</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="documentation"/>
</ipxact:vendorExtensions>
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
</ipxact:view>
 
 
 
</spirit:views>
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEBOUNCE_SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEBOUNCE_DELAY</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
</ipxact:views>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>1</ipxact:value></ipxact:modelParameter>
<ipxact:modelParameter><ipxact:name>DEBOUNCE_SIZE</ipxact:name><ipxact:value>4</ipxact:value></ipxact:modelParameter>
<ipxact:modelParameter><ipxact:name>DEBOUNCE_DELAY</ipxact:name><ipxact:value>4'b1111</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
 
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<ipxact:ports>
 
<spirit:port><spirit:name>data_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>clk</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>data_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>reset</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>data_rise</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>data_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<spirit:port><spirit:name>data_fall</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:port><ipxact:name>data_out</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
</spirit:ports>
<ipxact:port><ipxact:name>data_rise</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
</spirit:model>
<ipxact:port><ipxact:name>data_fall</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>reg</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
</ipxact:ports>
 
</ipxact:model>
 
 
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:fileSets>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sync_with_hysteresis</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
 
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/sync_with_hysteresis</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
</ipxact:fileSet>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
 
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/sync_with_hysteresis</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/copyright</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/sync_with_hysteresis</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
</spirit:fileSet>
 
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName>
<ipxact:name>../views/sim/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
</ipxact:fileSet>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:fileSet>
<ipxact:name>fs-syn</ipxact:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/sync_with_hysteresis</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/copyright</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/sync_with_hysteresis</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName>
<ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName>
<ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</ipxact:fileSet>
 
 
 
</spirit:fileSets>
 
 
</ipxact:fileSets>
 
 
 
264,4 → 287,6
 
 
 
</spirit:component>
 
 
</ipxact:component>
/rtl/xml/cde_sync_with_reset.xml
2,252 → 2,358
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>sync</spirit:name>
<spirit:version>with_reset</spirit:version> <spirit:configuration>default</spirit:configuration>
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>sync</ipxact:name>
<ipxact:version>with_reset</ipxact:version>
 
 
 
<ipxact:busInterfaces>
 
<spirit:componentGenerators>
<ipxact:busInterface><ipxact:name>clk</ipxact:name>
<ipxact:busType vendor="opencores.org" library="Busdefs" name="clock" version="def"/>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="opencores.org" library="Busdefs" name="clock" version="rtl"/>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort><ipxact:name>clk</ipxact:name></ipxact:logicalPort>
<ipxact:physicalPort><ipxact:name>clk</ipxact:name></ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave/>
</ipxact:busInterface>
 
 
<ipxact:busInterface><ipxact:name>reset_n</ipxact:name>
<ipxact:busType vendor="opencores.org" library="Busdefs" name="reset" version="def"/>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="opencores.org" library="Busdefs" name="reset" version="rtl"/>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort><ipxact:name>reset_n</ipxact:name></ipxact:logicalPort>
<ipxact:physicalPort><ipxact:name>reset_n</ipxact:name></ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave/>
</ipxact:busInterface>
 
 
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>sync_with_reset</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
<ipxact:busInterface><ipxact:name>data_in</ipxact:name>
<ipxact:busType vendor="opencores.org" library="Busdefs" name="adhoc" version="def"/>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="opencores.org" library="Busdefs" name="adhoc" version="rtl"/>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort><ipxact:name>adhoc</ipxact:name></ipxact:logicalPort>
<ipxact:physicalPort><ipxact:name>data_in</ipxact:name></ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave/>
</ipxact:busInterface>
 
 
</spirit:componentGenerators>
 
<ipxact:busInterface><ipxact:name>data_out</ipxact:name>
<ipxact:busType vendor="opencores.org" library="Busdefs" name="adhoc" version="def"/>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="opencores.org" library="Busdefs" name="adhoc" version="rtl"/>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort><ipxact:name>adhoc</ipxact:name></ipxact:logicalPort>
<ipxact:physicalPort><ipxact:name>data_out</ipxact:name></ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:master/>
</ipxact:busInterface>
 
 
<spirit:model>
 
<spirit:views>
</ipxact:busInterfaces>
 
 
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
 
<ipxact:componentGenerators>
 
 
 
 
<ipxact:componentGenerator>
<ipxact:name>gen_verilog</ipxact:name>
<ipxact:phase>104.0</ipxact:phase>
<ipxact:apiType>none</ipxact:apiType>
<ipxact:vendorExtensions><socgen:envIdentifier>:*common:*</socgen:envIdentifier></ipxact:vendorExtensions>
<ipxact:generatorExe>tools/verilog/gen_verilog</ipxact:generatorExe>
<ipxact:parameters>
<ipxact:parameter>
<ipxact:name>destination</ipxact:name>
<ipxact:value>sync_with_reset</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:componentGenerator>
 
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</ipxact:componentGenerators>
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<ipxact:model>
 
 
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>verilog</ipxact:name>
<ipxact:language>verilog</ipxact:language>
<ipxact:moduleName>cde_sync_with_reset</ipxact:moduleName>
<ipxact:moduleParameters>
<ipxact:moduleParameter parameterId="WIDTH" usageCount="1" usageType="nontyped">
<ipxact:name>WIDTH</ipxact:name>
<ipxact:value>8</ipxact:value>
</ipxact:moduleParameter>
</ipxact:moduleParameters>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:componentInstantiation>
</ipxact:instantiations>
 
<ipxact:views>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
<ipxact:view>
<ipxact:name>rtl</ipxact:name>
<ipxact:envIdentifier>verilog:Kactus2:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>verilog</ipxact:componentInstantiationRef>
</ipxact:view>
<ipxact:view>
<ipxact:name>verilog</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="verilog"/>
</ipxact:vendorExtensions>
</ipxact:view>
 
 
 
 
</spirit:views>
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEPTH</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
<ipxact:view>
<ipxact:name>common</ipxact:name><ipxact:envIdentifier>:*common:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-common</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>reset_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<ipxact:view>
<ipxact:name>sim</ipxact:name><ipxact:envIdentifier>:*Simulation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-sim</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:port><spirit:name>data_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<ipxact:view>
<ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
<ipxact:modelName></ipxact:modelName>
<ipxact:fileSetRef>
<ipxact:localName>fs-syn</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:view>
 
<spirit:port><spirit:name>data_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
 
 
 
</spirit:ports>
 
</spirit:model>
 
<ipxact:view>
<ipxact:name>doc</ipxact:name>
<ipxact:vendorExtensions>
<ipxact:componentRef ipxact:vendor="opencores.org"
ipxact:library="Testbench"
ipxact:name="toolflow"
ipxact:version="documentation"/>
</ipxact:vendorExtensions>
<ipxact:envIdentifier>:*Documentation:*</ipxact:envIdentifier>
<ipxact:language>Verilog</ipxact:language>
</ipxact:view>
 
 
 
<spirit:fileSets>
 
</ipxact:views>
 
<ipxact:modelParameters>
<ipxact:modelParameter><ipxact:name>WIDTH</ipxact:name><ipxact:value>1</ipxact:value></ipxact:modelParameter>
<ipxact:modelParameter><ipxact:name>DEPTH</ipxact:name><ipxact:value>2</ipxact:value></ipxact:modelParameter>
</ipxact:modelParameters>
 
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<ipxact:ports>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sync_with_reset</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
<ipxact:port><ipxact:name>clk</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
<ipxact:port><ipxact:name>reset_n</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction></ipxact:wire>
</ipxact:port>
 
 
<ipxact:port><ipxact:name>data_in</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
<ipxact:port><ipxact:name>data_out</ipxact:name>
<ipxact:wire><ipxact:wireTypeDefs><ipxact:wireTypeDef><ipxact:typeName>wire</ipxact:typeName></ipxact:wireTypeDef></ipxact:wireTypeDefs>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors><ipxact:vector><ipxact:left>WIDTH-1</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:vectors></ipxact:wire>
</ipxact:port>
 
</spirit:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
</ipxact:ports>
 
</ipxact:model>
 
 
 
 
<ipxact:fileSets>
 
 
 
<ipxact:fileSet>
<ipxact:name>fs-common</ipxact:name>
 
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/sync_with_reset</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>fragment</ipxact:userFileType>
</ipxact:file>
 
 
 
 
 
</ipxact:fileSet>
 
 
 
<ipxact:fileSet>
<ipxact:name>fs-sim</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/copyright</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/sync_with_reset</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/sync_with_reset</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName>
<ipxact:name>../views/sim/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-syn</ipxact:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/copyright</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/copyright</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>include</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/sync_with_reset</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName></ipxact:logicalName>
<ipxact:name>../verilog/common/sync_with_reset</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType><ipxact:userFileType>module</ipxact:userFileType>
</ipxact:file>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName>
<ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
 
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<ipxact:fileSet>
<ipxact:name>fs-lint</ipxact:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../views/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
<ipxact:file>
<ipxact:logicalName>dest_dir</ipxact:logicalName>
<ipxact:name>../views/syn/</ipxact:name>
<ipxact:fileType>verilogSource</ipxact:fileType>
<ipxact:userFileType>libraryDir</ipxact:userFileType>
</ipxact:file>
 
</spirit:fileSet>
</ipxact:fileSet>
 
 
 
 
</spirit:fileSets>
</ipxact:fileSets>
 
 
 
258,4 → 364,4
 
 
 
</spirit:component>
</ipxact:component>

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