URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/common
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/opencores.org/Testbench/mt45w8mw12/rtl/xml/mt45w8mw12_def.xml
0,0 → 1,277
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>mt45w8mw12</spirit:name> |
<spirit:version>def</spirit:version> <spirit:configuration>default</spirit:configuration> |
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<spirit:componentGenerators> |
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<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
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</spirit:componentGenerators> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
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<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
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<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
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<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
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</spirit:views> |
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR_BITS</spirit:name><spirit:value>23</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DQ_BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>MEM_BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
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<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>adv_n</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>cre</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>o_wait</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>ce_n</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>oe_n</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>we_n</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>lb_n</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>ub_n</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>addr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>ADDR_BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
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<spirit:port><spirit:name>dq</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>inout</spirit:direction> |
<spirit:vector><spirit:left>DQ_BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
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</spirit:ports> |
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</spirit:model> |
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</spirit:component> |
/opencores.org/Testbench/mt45w8mw12/rtl/verilog/top.sim
0,0 → 1,54
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|
module mt45w8mw12_def |
#( |
parameter ADDR_BITS = 23, |
parameter DQ_BITS = 16, |
parameter MEM_BITS = 16 |
) |
|
( |
input wire clk, |
input wire adv_n, |
input wire cre, |
output wire o_wait, |
input wire ce_n, |
input wire oe_n, |
input wire we_n, |
input wire lb_n, |
input wire ub_n, |
input wire [ADDR_BITS-1 : 0] addr, |
inout wire [DQ_BITS-1 : 0] dq |
); |
|
reg [7:0] memoryl [1<<MEM_BITS-1:0]; |
reg [7:0] memoryu [1<<MEM_BITS-1:0]; |
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reg [DQ_BITS-1 : 0] dq_out; |
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// Write Memory |
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always@(*) |
if(!ce_n && !we_n && !lb_n) memoryl[addr] = dq[7:0]; |
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always@(*) |
if(!ce_n && !we_n && !ub_n) memoryu[addr] = dq[15:8]; |
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// Read Memory |
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always@(*) dq_out[7:0] = memoryl[addr]; |
always@(*) dq_out[15:8] = memoryu[addr]; |
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// Tristate output |
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assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}}; |
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endmodule |
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/opencores.org/Testbench/mt45w8mw12/rtl/verilog/top.syn
0,0 → 1,49
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|
module mt45w8mw12_def |
#( |
parameter ADDR_BITS = 23, |
parameter DQ_BITS = 16, |
parameter MEM_BITS = 16 |
|
) |
|
( |
input wire clk, |
input wire adv_n, |
input wire cre, |
output wire o_wait, |
input wire ce_n, |
input wire oe_n, |
input wire we_n, |
input wire lb_n, |
input wire ub_n, |
input wire [ADDR_BITS-1 : 0] addr, |
inout wire [DQ_BITS-1 : 0] dq |
); |
|
reg [7:0] memoryl [1<<MEM_BITS-1:0]; |
reg [7:0] memoryu [1<<MEM_BITS-1:0]; |
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reg [DQ_BITS-1 : 0] dq_out; |
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// Write Memory |
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// Read Memory |
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always@(*) dq_out[7:0] = 8'h0; |
always@(*) dq_out[15:8] = 8'h0; |
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// Tristate output |
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// assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}}; |
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endmodule |
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/opencores.org/Testbench/mt45w8mw12/rtl/verilog/copyright.v
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* psram behavioral model for sims */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/mt45w8mw12/componentCfg.xml
0,0 → 1,31
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
|
--> |
<socgen:componentConfiguration |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
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<socgen:vendor>opencores.org</socgen:vendor> |
<socgen:library>Testbench</socgen:library> |
<socgen:component>mt45w8mw12</socgen:component> |
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<socgen:ip_name_depth>2</socgen:ip_name_depth> |
<socgen:ip_name_vendor_sep>_</socgen:ip_name_vendor_sep> |
<socgen:ip_name_library_sep>_</socgen:ip_name_library_sep> |
<socgen:ip_name_version_sep>_</socgen:ip_name_version_sep> |
<socgen:ip_name_base_macro>VARIANT</socgen:ip_name_base_macro> |
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<socgen:doc> |
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<socgen:library_path>/doc</socgen:library_path> |
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</socgen:doc> |
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</socgen:componentConfiguration> |
/opencores.org/Testbench/mt45w8mw12/bin/Makefile
0,0 → 1,2
include ../../../bin/Makefile.root |
|
/opencores.org/Testbench/doc/Geda/html/or1200_dbg_model_def.html
119,13 → 119,6
<td style="vertical-align: top;">Component<br></td> |
<td style="vertical-align: top;">Version<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/Testbench/doc/Geda/html/ps2_host_def.html
47,7 → 47,7
</li> |
</ul> |
</div> |
<img style="width: 573px; height: 326px;" alt="" src="../png/ps2_host_def_sym.png"><br> |
<img style="width: 623px; height: 374px;" alt="" src="../png/ps2_host_def_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
110,6 → 110,12
</tr> |
|
<tr> |
<td style="vertical-align: top;">rx_data[7:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rx_frame_error<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
146,6 → 152,18
</tr> |
|
<tr> |
<td style="vertical-align: top;">tx_ack_error<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">tx_data[7:0 ]<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">tx_write<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
168,12 → 186,19
<td style="vertical-align: top;">Version<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">tx_ack_err_tpb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">def<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">rcv_byte_tpb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
186,7 → 211,7
<br> |
<br> |
<br> |
<img style="width: 573px; height: 326px;" alt="" src="../png/ps2_host_def_sch.png"><br> |
<img style="width: 623px; height: 374px;" alt="" src="../png/ps2_host_def_sch.png"><br> |
<b><br> |
<br> |
<br> |
/opencores.org/Testbench/doc/Geda/html/uart_host_def.html
47,7 → 47,7
</li> |
</ul> |
</div> |
<img style="width: 663px; height: 254px;" alt="" src="../png/uart_host_def_sym.png"><br> |
<img style="width: 703px; height: 326px;" alt="" src="../png/uart_host_def_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
110,6 → 110,30
</tr> |
|
<tr> |
<td style="vertical-align: top;">rxd_data_avail_stb<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rxd_data_out[7:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rxd_force_parity<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rxd_parity<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rxd_parity_error<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
122,6 → 146,12
</tr> |
|
<tr> |
<td style="vertical-align: top;">txd_break<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">txd_buffer_empty<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
128,6 → 158,12
</tr> |
|
<tr> |
<td style="vertical-align: top;">txd_data_in[7:0 ]<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">txd_force_parity<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
134,6 → 170,12
</tr> |
|
<tr> |
<td style="vertical-align: top;">txd_load<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">txd_parity<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
156,12 → 198,26
<td style="vertical-align: top;">Version<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">rxd_data_out_prb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">def<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">rxd_stop_error_prb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">rxd_parity_error_prb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
174,7 → 230,7
<br> |
<br> |
<br> |
<img style="width: 663px; height: 254px;" alt="" src="../png/uart_host_def_sch.png"><br> |
<img style="width: 703px; height: 326px;" alt="" src="../png/uart_host_def_sch.png"><br> |
<b><br> |
<br> |
<br> |
/opencores.org/Testbench/doc/Geda/html/micro_bus16_model_def.html
47,7 → 47,7
</li> |
</ul> |
</div> |
<img style="width: 513px; height: 278px;" alt="" src="../png/micro_bus16_model_def_sym.png"><br> |
<img style="width: 583px; height: 278px;" alt="" src="../png/micro_bus16_model_def_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
61,14 → 61,14
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">OUT_DELAY<br> </td> |
<td style="vertical-align: top;">DELAY<br> </td> |
<td style="vertical-align: top;">15<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">OUT_WIDTH<br> </td> |
<td style="vertical-align: top;">10<br> </td> |
<td style="vertical-align: top;">WIDTH<br> </td> |
<td style="vertical-align: top;">16<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
110,6 → 110,12
</tr> |
|
<tr> |
<td style="vertical-align: top;">cs[1:0 ]<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">lb<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
123,7 → 129,7
|
<tr> |
<td style="vertical-align: top;">rdata[15:0 ]<br> </td> |
<td style="vertical-align: top;">inout<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
168,11 → 174,11
<td style="vertical-align: top;">Version<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">rdata_tpb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">def<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
</tbody> |
</table> |
186,7 → 192,7
<br> |
<br> |
<br> |
<img style="width: 513px; height: 278px;" alt="" src="../png/micro_bus16_model_def_sch.png"><br> |
<img style="width: 583px; height: 278px;" alt="" src="../png/micro_bus16_model_def_sch.png"><br> |
<b><br> |
<br> |
<br> |
/opencores.org/Testbench/doc/Geda/html/vga_model_def.html
144,12 → 144,19
<td style="vertical-align: top;">Version<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">device_rx_data_tpb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">def<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">device_rx_parity_tpb<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">Testbench<br></td> |
<td style="vertical-align: top;">io_probe<br></td> |
<td style="vertical-align: top;">in<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/Testbench/doc/Geda/src/vga_model_def.v
50,6 → 50,26
input wire [ 1 : 0] blue, |
input wire [ 2 : 0] green, |
input wire [ 2 : 0] red); |
reg exp_device_rx_parity; |
reg mask_device_rx_parity; |
reg [ 7 : 0] exp_device_rx_data; |
reg [ 7 : 0] mask_device_rx_data; |
wire drv_device_rx_parity; |
wire prb_device_rx_parity; |
wire [ 7 : 0] drv_device_rx_data; |
wire [ 7 : 0] prb_device_rx_data; |
assign prb_device_rx_data = 8'h00; |
assign prb_device_rx_parity = 1'b0; |
always@(posedge clk) |
if(reset) |
mask_device_rx_parity <= 1'b0; |
else |
mask_device_rx_parity <= 1'b0; |
always@(posedge clk) |
if(reset) |
mask_device_rx_data <= 8'b0; |
else |
mask_device_rx_data <= 8'b0; |
reg [23:0] red_h_cnt; |
reg [23:0] green_h_cnt; |
reg [23:0] blue_h_cnt; |
/opencores.org/Testbench/bfms/mt45w8mw12/rtl/xml/mt45w8mw12_def.xml
48,40 → 48,32
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>mt45w8mw12_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>mt45w8mw12_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
88,68 → 80,25
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
268,10 → 217,80
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/mt45w8mw12_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/mt45w8mw12_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* psram behavioral model for sims */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.sim
1,26 → 1,5
|
|
module mt45w8mw12_def |
#( |
parameter ADDR_BITS = 23, |
parameter DQ_BITS = 16, |
parameter MEM_BITS = 16 |
) |
|
( |
input wire clk, |
input wire adv_n, |
input wire cre, |
output wire o_wait, |
input wire ce_n, |
input wire oe_n, |
input wire we_n, |
input wire lb_n, |
input wire ub_n, |
input wire [ADDR_BITS-1 : 0] addr, |
inout wire [DQ_BITS-1 : 0] dq |
); |
|
reg [7:0] memoryl [1<<MEM_BITS-1:0]; |
reg [7:0] memoryu [1<<MEM_BITS-1:0]; |
|
49,6 → 28,5
|
|
|
endmodule |
|
|
/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.syn
1,27 → 1,4
|
|
module mt45w8mw12_def |
#( |
parameter ADDR_BITS = 23, |
parameter DQ_BITS = 16, |
parameter MEM_BITS = 16 |
|
) |
|
( |
input wire clk, |
input wire adv_n, |
input wire cre, |
output wire o_wait, |
input wire ce_n, |
input wire oe_n, |
input wire we_n, |
input wire lb_n, |
input wire ub_n, |
input wire [ADDR_BITS-1 : 0] addr, |
inout wire [DQ_BITS-1 : 0] dq |
); |
|
reg [7:0] memoryl [1<<MEM_BITS-1:0]; |
reg [7:0] memoryu [1<<MEM_BITS-1:0]; |
|
44,6 → 21,3
|
|
|
endmodule |
|
|
/opencores.org/Testbench/bfms/or1200_dbg_model/rtl/xml/or1200_dbg_model_def.xml
320,14 → 320,6
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:version="in.design"/> |
</spirit:view> |
|
|
|
/opencores.org/Testbench/bfms/ps2_host/componentCfg.xml
26,6 → 26,6
</socgen:doc> |
|
|
</socgen:componentConfiguration> |
|
|
</socgen:componentConfiguration> |
|
/opencores.org/Testbench/bfms/ps2_host/rtl/xml/ps2_host_def.design.xml
0,0 → 1,168
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>ps2_host</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
<socgen:node><spirit:name>exp_rcv_byte</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
|
|
|
<socgen:node><spirit:name>mask_rcv_byte</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
|
|
<socgen:node><spirit:name>exp_tx_ack_err</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
<socgen:node><spirit:name>mask_tx_ack_err</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>exp_rcv_byte</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rcv_byte" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_tx_ack_err</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_tx_ack_err" /> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>mask_rcv_byte</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rcv_byte" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mask_tx_ack_err</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_tx_ack_err" /> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rcv_byte_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tx_ack_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="tx_ack_error" /> |
<spirit:internalPortReference spirit:componentRef="tx_ack_err_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>tx_ack_err_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2_host tx_ack Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>rcv_byte_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2_host receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/opencores.org/Testbench/bfms/ps2_host/rtl/xml/ps2_host_def.xml
41,119 → 41,78
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>ps2_host_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>ps2_host_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="ps2_host" |
spirit:version="def.design"/> |
</spirit:view> |
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
163,7 → 122,6
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
231,6 → 189,11
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>tx_ack_error</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rx_frame_error</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
237,31 → 200,108
</spirit:port> |
|
<spirit:port><spirit:name>rx_clr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>tx_write</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>tx_write</spirit:name> |
<spirit:port> |
<spirit:name>tx_data</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port> |
<spirit:name>rx_data</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
<spirit:wire><spirit:direction>in</spirit:direction><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
|
</spirit:ports> |
|
</spirit:model> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/ps2_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/ps2_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/ps2_host/rtl/verilog/tasks
0,0 → 1,53
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
task clear_rx_host; |
begin |
rx_clr <= 1'b1; |
next(1); |
rx_clr <= 1'b0; |
end |
endtask |
|
|
|
|
task send_byte; |
input [7:0] byte_out; |
begin |
$display("%t %m %2h",$realtime ,byte_out ); |
tx_data <= byte_out; |
next(1); |
tx_write <= 1'b1; |
next(1); |
tx_write <= 1'b0; |
next(1); |
while(busy) next(1); |
mask_tx_ack_err <= 1'b1; |
next(1); |
mask_tx_ack_err <= 1'b0; |
end |
endtask // send_byte |
|
|
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rcv_byte <= byte_in; |
|
while(!rx_read) next(1); |
$display("%t checking %h",$realtime,byte_in); |
mask_rcv_byte <= 8'hff; |
next(1); |
mask_rcv_byte <= 8'h00; |
end |
endtask |
|
|
|
/opencores.org/Testbench/bfms/ps2_host/rtl/verilog/copyright
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* ps2 host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/opencores.org/Testbench/bfms/ps2_host/rtl/verilog/top.sim
1,49 → 1,3
|
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* ps2 host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
module ps2_host_def |
|
( |
51,7 → 5,7
input wire reset, |
input wire busy, |
|
inout wire [7:0] rx_data, |
input wire [7:0] rx_data, |
input wire rx_read, |
input wire rx_full, |
input wire rx_parity_error, |
65,21 → 19,53
output reg tx_write |
); |
|
|
reg exp_tx_ack_err; |
reg mask_tx_ack_err; |
|
reg [7:0] exp_rcv_byte; |
reg [7:0] mask_rcv_byte; |
|
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
io_probe_in |
#( .MESG("ps2_host tx_ack error") |
) |
tx_ack_err_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_tx_ack_err ), |
.mask ( mask_tx_ack_err ), |
.signal ( tx_ack_error ) |
); |
|
|
|
|
|
|
|
|
|
io_probe_in |
#( .MESG("ps2_host receive error"), |
.WIDTH (8) |
) |
rcv_byte_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_rcv_byte ), |
.mask ( mask_rcv_byte ), |
.signal ( rx_data ) |
); |
|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
90,12 → 76,19
mask_tx_ack_err <= 1'b0; |
exp_rcv_byte <= 8'h00; |
mask_rcv_byte <= 8'h00; |
end |
|
|
|
end |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
task clear_rx_host; |
begin |
rx_clr <= 1'b1; |
105,7 → 98,19
endtask |
|
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rcv_byte <= byte_in; |
|
while(!rx_read) next(1); |
$display("%t checking %h",$realtime,byte_in); |
mask_rcv_byte <= 8'hff; |
next(1); |
mask_rcv_byte <= 8'h00; |
end |
endtask |
|
task send_byte; |
input [7:0] byte_out; |
127,53 → 132,6
|
|
|
io_probe_def |
#( .MESG("ps2_host tx_ack error") |
) |
tx_ack_err_tpb |
( |
.clk ( clk ), |
.drive_value ( 1'bz ), |
.expected_value ( exp_tx_ack_err ), |
.mask ( mask_tx_ack_err ), |
.signal ( tx_ack_error ) |
); |
|
|
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rcv_byte <= byte_in; |
|
while(!rx_read) next(1); |
$display("%t checking %h",$realtime,byte_in); |
mask_rcv_byte <= 8'hff; |
next(1); |
mask_rcv_byte <= 8'h00; |
end |
endtask |
|
|
|
|
io_probe_def |
#( .MESG("ps2_host receive error"), |
.WIDTH (8) |
) |
rcv_byte_tpb |
( |
.clk ( clk ), |
.drive_value ( {8{1'bz}} ), |
.expected_value ( exp_rcv_byte ), |
.mask ( mask_rcv_byte ), |
.signal ( rx_data ) |
); |
|
|
|
|
endmodule |
|
/opencores.org/Testbench/bfms/ps2_host/rtl/verilog/top.syn
1,49 → 1,3
|
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* ps2 host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
module ps2_host_def |
|
( |
51,7 → 5,7
input wire reset, |
input wire busy, |
|
inout wire [7:0] rx_data, |
input wire [7:0] rx_data, |
input wire rx_read, |
input wire rx_full, |
input wire rx_parity_error, |
73,9 → 27,6
reg [7:0] mask_rcv_byte; |
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
/opencores.org/Testbench/bfms/ps2_host/rtl/verilog/logic
0,0 → 1,14
always@(posedge clk) |
if(reset) |
begin |
tx_data <= 8'h00; |
tx_write <= 1'b0; |
rx_clr <= 1'b0; |
exp_tx_ack_err <= 1'b0; |
mask_tx_ack_err <= 1'b0; |
exp_rcv_byte <= 8'h00; |
mask_rcv_byte <= 8'h00; |
end |
|
|
|
/opencores.org/Testbench/bfms/micro_bus_model/rtl/xml/micro_bus_model_def.xml
99,30 → 99,9
|
</spirit:busInterfaces> |
|
|
|
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
131,12 → 110,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>micro_bus_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
152,57 → 127,12
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top</spirit:value> |
<spirit:value>micro_bus_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
|
226,7 → 156,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top</spirit:name> |
<spirit:name>../verilog/sim/micro_bus_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
259,7 → 189,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top</spirit:name> |
<spirit:name>../verilog/syn/micro_bus_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
293,6 → 223,23
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
/opencores.org/Testbench/bfms/clock_gen/rtl/xml/clock_gen_def.xml
52,7 → 52,7
<spirit:portMap> |
<spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
</spirit:physicalPort> |
</spirit:portMap> |
|
87,38 → 87,36
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gen_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gen_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
132,39 → 130,24
|
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
245,11 → 228,87
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gen_sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/clock_gen_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gen_syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/clock_gen_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
</spirit:fileSets> |
|
|
|
|
|
|
</spirit:component> |
|
|
/opencores.org/Testbench/bfms/clock_gen/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/bfms/clock_gen/rtl/verilog/clock_gen_sim
0,0 → 1,80
reg task_reset; |
reg task_FAIL; |
reg task_FINISH; |
|
|
always@(posedge clk or negedge START) |
if(!START) FINISH <= 0; |
else FINISH <= (|STOP) || FINISH || task_FINISH; |
|
|
|
always@(posedge clk or negedge START) |
if(!START) FAIL <= 0; |
else FAIL <= task_FAIL || (|BAD); |
|
|
always@(posedge clk or negedge START) |
if(!START) reset <= 1'b1; |
else reset <= task_reset; |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask // next |
|
|
|
|
|
initial |
begin |
task_FINISH <= 0; |
task_FAIL <= 0; |
task_reset <= 0; |
end |
|
|
|
task reset_on; |
task_reset = 1; |
endtask // reset_on |
|
task reset_off; |
begin |
task_reset = 0; |
end |
endtask // reset_off |
|
|
|
|
task automatic fail; |
input [799:0] message; |
begin |
task_FAIL <= 1; |
$display("%t Simulation FAILURE: %s ",$realtime,message ); |
@(posedge clk); |
task_FAIL <= 0; |
end |
endtask |
|
task exit; |
begin |
@(posedge clk); |
task_FINISH <= 1; |
@(posedge clk); |
@(posedge clk); |
@(posedge clk); |
@(posedge clk); |
end |
endtask |
|
|
|
|
|
/opencores.org/Testbench/bfms/clock_gen/rtl/verilog/clock_gen_syn
0,0 → 1,16
|
always@(posedge clk or negedge START) |
if(!START) FINISH <= 0; |
else FINISH <= (|STOP) || FINISH; |
|
|
|
always@(posedge clk or negedge START) |
if(!START) FAIL <= 0; |
else FAIL <= (|BAD); |
|
|
always@(posedge clk or negedge START) |
if(!START) reset <= 1'b1; |
else reset <= 1'b0; |
|
/opencores.org/Testbench/bfms/ps2_model/componentCfg.xml
27,4 → 27,21
|
|
|
<socgen:configurations> |
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>CLKCNT</socgen:name><socgen:value>10'h1f0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>10</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
</socgen:configurations> |
|
|
|
|
</socgen:componentConfiguration> |
/opencores.org/Testbench/bfms/ps2_model/rtl/xml/ps2_model_def.xml
39,29 → 39,8
<spirit:name>ps2_model</spirit:name> |
<spirit:version>def</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
|
<spirit:componentGenerators> |
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
71,12 → 50,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>ps2_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
90,54 → 65,13
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>ps2_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
|
149,13 → 83,13
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:name>../verilog/sim/ps2_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
191,7 → 125,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
198,7 → 132,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:name>../verilog/syn/ps2_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
240,6 → 174,24
spirit:version="def.design"/> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
/opencores.org/Testbench/bfms/ps2_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/bfms/display_model/componentCfg.xml
27,4 → 27,5
|
|
|
|
</socgen:componentConfiguration> |
/opencores.org/Testbench/bfms/display_model/rtl/xml/display_model_def.xml
39,184 → 39,57
<spirit:name>display_model</spirit:name> |
<spirit:version>def</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>display_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
<spirit:model> |
<spirit:views> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
309,11 → 182,93
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/display_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/display_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/display_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/bfms/jtag_model/componentCfg.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
28,6 → 28,20
</socgen:doc> |
|
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>DIVCNT</socgen:name><socgen:value>4'h1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
</socgen:configurations> |
|
|
</socgen:componentConfiguration> |
/opencores.org/Testbench/bfms/jtag_model/rtl/xml/jtag_model_def.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
46,9 → 46,23
|
|
<spirit:componentGenerators> |
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_model_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
100,9 → 114,24
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_model</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_model_def.v</spirit:name> |
<spirit:name>../verilog/sim/jtag_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
126,7 → 155,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_model_def.v</spirit:name> |
<spirit:name>../verilog/sim/jtag_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
152,8 → 181,21
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
/opencores.org/Testbench/bfms/jtag_model/rtl/verilog/jtag_model
0,0 → 1,172
reg tclk_enable; |
reg [SIZE-1:0] tclk_counter; |
wire next_tclk_edge; |
wire next_tclk_pos_edge; |
wire next_tclk_neg_edge; |
assign next_tclk_edge = (tclk_counter == 4'h0); |
assign next_tclk_pos_edge = next_tclk_edge && (!tclk) ; |
assign next_tclk_neg_edge = next_tclk_edge && ( tclk) ; |
always@(posedge clk) |
if(reset) tclk_counter <= DIVCNT; |
else |
if(|tclk_counter) tclk_counter <= tclk_counter-4'h1; |
else tclk_counter <= DIVCNT; |
always@(posedge clk) |
if(reset) tclk <= 1'b0; |
else |
if(!tclk_enable) tclk <= tclk; |
else |
if( next_tclk_pos_edge ) tclk <= 1'b1; |
else |
if( next_tclk_neg_edge ) tclk <= 1'b0; |
else tclk <= tclk; |
|
reg actual; |
initial |
begin |
tclk_enable <= 1'b0; |
tclk <= 1'b0; |
tdo <= 1'b1; |
tms <= 1'b1; |
trst_n <= 1'b0; |
end |
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
task enable_tclk; |
begin |
tclk_enable <= 1'b1; |
end |
endtask |
task enable_trst_n; |
begin |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
Clk_bit(1,1,actual); |
trst_n <= 1'b1; |
Clk_bit(1,1,actual); |
end |
endtask |
task enable_reset; |
begin |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
Clk_bit(1,0,actual); |
end |
endtask |
task init; |
begin |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
Clk_bit(0,0,actual); |
end |
endtask |
|
task Clk_bit; |
input TMS; |
input TDO; |
output ACT; |
begin |
while (next_tclk_neg_edge != 1) |
begin |
next(1); |
end |
if(TMS) tms <= 1'b1; |
else tms <= 1'b0; |
if ( TDO == 1 ) tdo <= 1'b1; |
else if( TDO == 0 ) tdo <= 1'b0; |
else tdo <= 1'bx; |
while (next_tclk_pos_edge != 1) |
begin |
next(1); |
end |
ACT = tdi; |
end |
endtask |
/******************************************************************************/ |
/* LoadTapInst (<Inst>); */ |
/******************************************************************************/ |
task LoadTapInst; // Load a Tap Instruction that uses the Boundary Register |
parameter [15:0] JTAG_INST_LENGTH = 4; |
input [JTAG_INST_LENGTH:1] Inst; // This task starts & ends with the Tap in the RT_IDLE state |
input [JTAG_INST_LENGTH:1] Inst_Return; // |
integer i; |
reg [JTAG_INST_LENGTH:1] Ack; |
begin |
Clk_bit(1'b1,1'b0,actual); // Transition from RT_IDLE to SELECT_DR |
Clk_bit(1'b1,1'b0,actual); // Transition from SELECT_DR to SELECT_IR |
Clk_bit(1'b0,1'b0,actual); // Transition from SELECT_IR to CAPTURE_IR |
Clk_bit(1'b0,1'b0,actual); // Transition from CAPTURE_IR to SHIFT_IR |
for (i = 1; i <= JTAG_INST_LENGTH; i = i+1) // Shift in Inst |
begin |
Clk_bit(( i == JTAG_INST_LENGTH),Inst[i],Ack[i]); |
end |
$display ("%t %m LoadTapInst %b Expected %b Received %b " ,$realtime,Inst, Inst_Return, Ack ); |
if (Ack !== Inst_Return) |
begin |
cg.fail (" LoadTapInst receive error "); |
end |
Clk_bit(1'b1,1'b0,actual); // Transition from EXIT1_IR to UPDATE_IR |
Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE_IR to RT_IDLE |
end |
endtask // LoadTapInst |
//***************************************************************************/ |
//* Shift Register |
//***************************************************************************/ |
task automatic Shift_Register; // Initialize boundary register with outputs disabled |
// This tasks starts at RT_IDLE and ends at SHIFT_DR |
parameter [15:0] LENGTH = 100; |
input length; |
input [LENGTH:1] Dataout; |
integer length; |
integer i; |
reg [LENGTH:1] DataBack; |
begin |
Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR |
for (i = 1; i <= length; i = i+1) |
Clk_bit((i==length),Dataout[i],DataBack[i]); |
$display ("%t %m Shift_data -%d wr-%h rd-%h ",$realtime,length,Dataout[LENGTH:1],DataBack[LENGTH:1]); |
Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR |
Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE |
end |
endtask // ShiftRegister |
task automatic Shift_Cmp_32; // Initialize boundary register with outputs disabled |
// This tasks starts at RT_IDLE and ends at SHIFT_DR |
parameter [15:0] LENGTH = 32; |
input [LENGTH:1] Dataout; |
input [LENGTH:1] DataExp; |
integer i; |
reg [LENGTH:1] DataBack; |
begin |
Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR |
Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR |
for (i = 1; i <= LENGTH; i = i+1) |
Clk_bit((i==LENGTH),Dataout[i],DataBack[i]); |
$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack ); |
if (DataBack !== DataExp ) |
begin |
cg.fail (" Shift_cmp receive error "); |
end |
Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR |
Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE |
end |
endtask // ShiftRegister |
|
|
|
/opencores.org/Testbench/bfms/jtag_model/rtl/verilog/copyright.v
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* JTAG Hoset model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010-2015> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/opencores.org/Testbench/bfms/uart_host/rtl/xml/uart_host_def.xml
41,7 → 41,44
|
<spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>uart_host_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>uart_host_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
80,75 → 117,22
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:name="uart_host" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
199,6 → 183,28
</spirit:port> |
|
|
|
|
<spirit:port><spirit:name>txd_data_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire> |
<spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector> |
</spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_data_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector> |
</spirit:wire> |
</spirit:port> |
|
|
|
|
<spirit:port><spirit:name>parity_enable</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
219,6 → 225,38
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>txd_load</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>txd_break</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_parity</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_force_parity</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>rxd_data_avail_stb</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
|
|
<spirit:port><spirit:name>rxd_data_avail</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
236,22 → 274,95
|
|
|
output reg [7:0] txd_data_in, |
output reg txd_load, |
output reg txd_break, |
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
|
|
</spirit:ports> |
|
</spirit:model> |
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/code</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/uart_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/code</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/uart_host_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/uart_host/rtl/xml/uart_host_def.design.xml
0,0 → 1,209
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>uart_host</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>exp_rxd_data_out</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>mask_rxd_data_out</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>exp_rxd_parity_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
<socgen:node><spirit:name>mask_rxd_parity_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
<socgen:node><spirit:name>exp_rxd_stop_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
<socgen:node><spirit:name>mask_rxd_stop_error</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
|
|
|
|
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="clk"/> |
|
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>mask_rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mask_rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>mask_rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_data_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_data_out" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rxd_data_out_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_stop_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_stop_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_stop_error_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>rxd_parity_error</spirit:name> |
<spirit:externalPortReference spirit:portRef="rxd_parity_error" /> |
<spirit:internalPortReference spirit:componentRef="rxd_parity_error_prb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
</spirit:adHocConnections> |
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>rxd_data_out_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>rxd_stop_error_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host stop Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>rxd_parity_error_prb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"uart_host parity Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/opencores.org/Testbench/bfms/uart_host/rtl/verilog/tasks
0,0 → 1,60
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
|
|
task clear_rx_host; |
begin |
next(1); |
end |
endtask |
|
|
|
|
task send_byte; |
input [7:0] byte_out; |
|
begin |
while(!txd_buffer_empty) next(1); |
$display("%t %m %2h",$realtime ,byte_out); |
txd_data_in <= byte_out; |
next(1); |
txd_load <= 1'b1; |
next(1); |
txd_load <= 1'b0; |
next(1); |
end |
endtask // send_byte |
|
|
|
task rcv_byte; |
input [7:0] byte_in; |
begin |
exp_rxd_data_out <= byte_in; |
while(!rxd_data_avail) next(1); |
$display("%t %m checking %h",$realtime,byte_in); |
mask_rxd_stop_error <= 1'b1; |
mask_rxd_parity_error <= 1'b1; |
mask_rxd_data_out <= 8'hff; |
next(1); |
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
rxd_data_avail_stb <= 1'b1; |
next(1); |
rxd_data_avail_stb <= 1'b0; |
next(1); |
end |
endtask |
|
|
|
|
/opencores.org/Testbench/bfms/uart_host/rtl/verilog/copyright
0,0 → 1,43
|
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* uart host model for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/opencores.org/Testbench/bfms/uart_host/rtl/verilog/top.sim
47,40 → 47,70
module uart_host_def ( |
input wire clk, |
input wire reset, |
output reg parity_enable, |
output reg txd_parity, |
input wire rxd_data_avail, |
input wire rxd_stop_error, |
input wire rxd_parity_error, |
input wire txd_buffer_empty, |
input wire [7:0] rxd_data_out, |
output reg parity_enable, |
output reg rxd_data_avail_stb, |
output reg rxd_force_parity, |
output reg rxd_parity, |
output reg txd_break, |
output reg txd_force_parity, |
output reg [7:0] txd_data_in, |
input wire txd_buffer_empty, |
output reg txd_load, |
output reg txd_break, |
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
input wire rxd_data_avail, |
inout wire rxd_stop_error, |
inout wire rxd_parity_error |
output reg txd_parity, |
output reg [7:0] txd_data_in |
|
); |
|
reg exp_rxd_stop_error; |
reg exp_rxd_parity_error; |
reg exp_rxd_stop_error; |
reg exp_rxd_parity_error; |
reg [7:0] exp_rxd_data_out; |
|
reg mask_rxd_stop_error; |
reg mask_rxd_parity_error; |
reg mask_rxd_stop_error; |
reg mask_rxd_parity_error; |
reg [7:0] mask_rxd_data_out; |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
io_probe_in |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
); |
|
io_probe_in |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
); |
|
|
|
|
io_probe_in |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
|
|
); |
|
|
always@(posedge clk) |
if(reset) |
106,6 → 136,17
end |
|
|
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask |
|
|
|
|
task clear_rx_host; |
begin |
next(1); |
152,60 → 193,6
end |
endtask |
|
|
io_probe_def |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
|
|
); |
|
|
|
|
|
|
io_probe_def |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
|
|
); |
|
|
|
|
io_probe_def |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
|
|
); |
|
|
|
|
|
|
|
endmodule |
|
/opencores.org/Testbench/bfms/uart_host/rtl/verilog/top.syn
57,10 → 57,10
output reg rxd_parity, |
output reg rxd_force_parity, |
output reg rxd_data_avail_stb, |
inout wire [7:0] rxd_data_out, |
input wire [7:0] rxd_data_out, |
input wire rxd_data_avail, |
inout wire rxd_stop_error, |
inout wire rxd_parity_error |
input wire rxd_stop_error, |
input wire rxd_parity_error |
); |
|
reg exp_rxd_stop_error; |
73,44 → 73,12
|
|
|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
|
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
|
|
end |
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host receive error"), |
.WIDTH(8)) |
rxd_data_out_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz ), |
.expected_value ( exp_rxd_data_out ), |
.mask ( mask_rxd_data_out ), |
.signal ( rxd_data_out ) |
123,12 → 91,11
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host stop error")) |
rxd_stop_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_rxd_stop_error ), |
.mask ( mask_rxd_stop_error ), |
.signal ( rxd_stop_error ) |
139,12 → 106,11
|
|
|
io_probe_def |
io_probe_in |
#(.MESG("uart_host parity error")) |
rxd_parity_error_prb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.clk ( clk ), |
.expected_value ( exp_rxd_parity_error ), |
.mask ( mask_rxd_parity_error ), |
.signal ( rxd_parity_error ) |
152,8 → 118,34
|
); |
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
|
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
|
|
end |
|
|
|
|
|
|
|
/opencores.org/Testbench/bfms/uart_host/rtl/verilog/code
0,0 → 1,26
assign drive_8 = 8'bzzzzzzzz; |
assign drive_1 = 1'bz; |
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
parity_enable <= 1'b0; |
txd_data_in <= 8'h00; |
txd_parity <= 1'b0; |
txd_force_parity <= 1'b0; |
txd_load <= 1'b0; |
txd_break <= 1'b0; |
rxd_parity <= 1'b0; |
rxd_force_parity <= 1'b0; |
rxd_data_avail_stb <= 1'b0; |
exp_rxd_stop_error <= 1'b0; |
exp_rxd_parity_error <= 1'b0; |
exp_rxd_data_out <= 8'h00; |
mask_rxd_stop_error <= 1'b0; |
mask_rxd_parity_error <= 1'b0; |
mask_rxd_data_out <= 8'h00; |
end |
|
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/xml/micro_bus16_model_def.xml
48,39 → 48,31
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>micro_bus16_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>micro_bus16_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
89,61 → 81,7
|
|
|
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
152,12 → 90,25
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:name="micro_bus16_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
199,8 → 150,8
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>OUT_DELAY</spirit:name><spirit:value>15</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>OUT_WIDTH</spirit:name><spirit:value>10</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DELAY</spirit:name><spirit:value>15</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
250,13 → 201,100
|
<spirit:port><spirit:name>rdata</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>inout</spirit:direction> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>cs</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/micro_bus16_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/logic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/micro_bus16_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/xml/micro_bus16_model_def.design.xml
0,0 → 1,133
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>micro_bus16_model</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>exp_rdata</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>mask_rdata</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>exp_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>mask_rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>rdata</spirit:name> |
<spirit:externalPortReference spirit:portRef="rdata" spirit:left="15" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="rdata_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>rdata_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"micro 16 rdata Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/verilog/tasks
0,0 → 1,116
// Tasks |
|
|
|
task automatic next; |
input [31:0] num; |
repeat (num) @ (posedge clk); |
endtask // next |
|
|
|
|
// idle cycle |
task u_idle; |
begin |
addr <= 24'h000000; |
wdata <= 16'h0000; |
rd <= 1'b0; |
cs <= 2'b00; |
wr <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
mask_rdata <= 16'h0000; |
next(1); |
end |
endtask |
|
|
|
|
// write cycle |
task u_write; |
input [23:0] a; |
input [15:0] d; |
|
begin |
|
$display("%t %m cycle %x %x",$realtime,a,d ); |
|
addr <= a; |
wdata <= d; |
rd <= 1'b0; |
cs <= 2'b01; |
wr <= 1'b1; |
ub <= 1'b1; |
lb <= 1'b1; |
next(4); |
rd <= 1'b0; |
cs <= 2'b00; |
wr <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
next(1); |
|
end |
endtask |
|
// read cycle |
task u_read; |
input [23:0] a; |
output [15:0] d; |
|
begin |
|
addr <= a; |
wdata <= 16'h0000; |
rd <= 1'b1; |
cs <= 2'b01; |
wr <= 1'b0; |
ub <= 1'b1; |
lb <= 1'b1; |
|
next(4); |
|
d <= rdata; |
$display("%t %m cycle %x %x",$realtime,a,rdata ); |
rd <= 1'b1; |
next(1); |
rd <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
cs <= 2'b00; |
next(1); |
end |
endtask |
|
// Compare cycle (read data from location and compare with expected data) |
task u_cmp; |
input [23:0] a; |
input [15:0] d_exp; |
|
begin |
addr <= a; |
wdata <= 16'h0000; |
rd <= 1'b1; |
ub <= 1'b1; |
lb <= 1'b1; |
cs <= 2'b01; |
wr <= 1'b0; |
exp_rdata <= d_exp; |
|
next(5); |
mask_rdata <= 16'hffff; |
|
|
next(1); |
$display("%t %m cycle %x %x",$realtime,a,d_exp ); |
mask_rdata <= 16'h0000; |
rd <= 1'b0; |
ub <= 1'b0; |
lb <= 1'b0; |
cs <= 2'b00; |
next(1); |
end |
endtask |
|
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/verilog/copyright
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Microprocessor bus functional model (BFM) for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/verilog/top.sim
1,54 → 1,6
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Microprocessor bus functional model (BFM) for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
|
|
|
module micro_bus16_model_def |
#(parameter OUT_DELAY = 15, |
parameter OUT_WIDTH = 10 |
#(parameter DELAY = 15, |
parameter WIDTH = 16 |
) |
|
|
55,6 → 7,7
( |
input wire clk, |
input wire reset, |
input wire [15:0] rdata, |
|
output reg [23:0] addr, |
output reg [15:0] wdata, |
62,16 → 15,41
output reg rd, |
output reg wr, |
output reg ub, |
output reg lb, |
output reg lb |
|
|
inout wire [15:0] rdata |
); |
|
|
reg [15:0] exp_rdata; |
reg [15:0] mask_rdata; |
|
|
|
io_probe_in |
#(.MESG ("micro rdata Error"), |
.WIDTH (WIDTH), |
.IN_DELAY (DELAY) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
|
|
|
|
|
|
|
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
88,21 → 66,6
|
|
|
io_probe_def |
#(.MESG ("micro rdata Error"), |
.WIDTH (16), |
.RESET ({16{1'bz}}), |
.OUT_DELAY (OUT_DELAY), |
.OUT_WIDTH (OUT_WIDTH) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.drive_value (16'bzzzzzzzzzzzzzzzz ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
// Tasks |
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/verilog/top.syn
1,54 → 1,6
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Microprocessor bus functional model (BFM) for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
|
|
|
|
|
module micro_bus16_model_def |
#(parameter OUT_DELAY = 15, |
parameter OUT_WIDTH = 10 |
#(parameter DELAY = 15, |
parameter WIDTH = 10 |
) |
|
|
55,6 → 7,7
( |
input wire clk, |
input wire reset, |
input wire [15:0] rdata, |
|
output reg [23:0] addr, |
output reg [15:0] wdata, |
62,10 → 15,10
output reg rd, |
output reg wr, |
output reg ub, |
output reg lb, |
output reg lb |
|
|
inout wire [15:0] rdata |
|
); |
|
|
72,10 → 25,26
reg [15:0] exp_rdata; |
reg [15:0] mask_rdata; |
|
|
|
|
io_probe_in |
#(.MESG ("micro rdata Error"), |
.WIDTH (16) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
always@(posedge clk) |
if(reset) |
begin |
addr <= 24'h0000; |
addr <= 24'h000000; |
wdata <= 16'h0000; |
wr <= 1'b0; |
rd <= 1'b0; |
88,27 → 57,9
|
|
|
io_probe_def |
#(.MESG ("micro rdata Error"), |
.WIDTH (16), |
.RESET ({16{1'bz}}), |
.OUT_DELAY (OUT_DELAY), |
.OUT_WIDTH (OUT_WIDTH) |
) |
rdata_tpb |
( |
.clk ( clk ), |
.drive_value (16'bzzzzzzzzzzzzzzzz ), |
.expected_value ( exp_rdata ), |
.mask ( mask_rdata ), |
.signal ( rdata ) |
); |
|
|
|
|
|
|
|
endmodule |
|
/opencores.org/Testbench/bfms/micro_bus16_model/rtl/verilog/logic
0,0 → 1,14
always@(posedge clk) |
if(reset) |
begin |
addr <= 24'h0000; |
wdata <= 16'h0000; |
wr <= 1'b0; |
rd <= 1'b0; |
cs <= 2'b00; |
ub <= 1'b0; |
lb <= 1'b0; |
exp_rdata <= 16'h0000; |
mask_rdata <= 16'h0000; |
end |
|
/opencores.org/Testbench/bfms/uart_model/rtl/xml/uart_model_def.xml
46,23 → 46,7
|
|
<spirit:componentGenerators> |
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
72,12 → 56,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>uart_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
91,57 → 71,121
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>uart_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="uart_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
|
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>CLKCNT</spirit:name><spirit:value>4'h5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>txd_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rxd_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
|
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
149,31 → 193,32
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:name>../verilog/top.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.tasks</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
<spirit:name>../verilog/sim/uart_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
216,30 → 261,34
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
<spirit:name>../verilog/syn/uart_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_xmit</spirit:name> |
273,101 → 322,10
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="uart_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
</spirit:view> |
|
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>CLKCNT</spirit:name><spirit:value>4'h5</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>txd_in</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rxd_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/uart_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/bfms/vga_model/rtl/xml/vga_model_def.design.xml
0,0 → 1,190
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>Testbench</spirit:library> |
<spirit:name>vga_model</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>exp_device_rx_data</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>mask_device_rx_data</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire> |
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>exp_device_rx_parity</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>drv_device_rx_parity</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
|
|
|
<socgen:node><spirit:name>mask_device_rx_parity</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
|
|
|
|
|
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="slave_clk_clk"/> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>exp_device_rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_device_rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>exp_device_rx_parity</spirit:name> |
<spirit:externalPortReference spirit:portRef="exp_device_rx_parity" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="expected_value"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>mask_device_rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_device_rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>mask_device_rx_parity</spirit:name> |
<spirit:externalPortReference spirit:portRef="mask_device_rx_parity" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="mask"/> |
</spirit:adHocConnection> |
|
|
|
|
|
<spirit:adHocConnection> |
<spirit:name>prb_device_rx_data</spirit:name> |
<spirit:externalPortReference spirit:portRef="prb_device_rx_data" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_data_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>prb_device_rx_parity</spirit:name> |
<spirit:externalPortReference spirit:portRef="prb_device_rx_parity" /> |
<spirit:internalPortReference spirit:componentRef="device_rx_parity_tpb" spirit:portRef="signal"/> |
</spirit:adHocConnection> |
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
|
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>device_rx_data_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2 data receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>device_rx_parity_tpb</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="io_probe" spirit:version="in" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MESG">"ps2 parity receive Error"</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
|
</spirit:componentInstances> |
|
|
</spirit:design> |
/opencores.org/Testbench/bfms/vga_model/rtl/xml/vga_model_def.xml
56,12 → 56,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>vga_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
75,157 → 71,51
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>vga_model_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="vga_model" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>Hierarchical</spirit:name> |
|
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="io_probe" |
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
325,9 → 215,95
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/vga_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/vga_model_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.rtl</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/vga_model/rtl/verilog/top.rtl
1,8 → 1,23
|
|
assign prb_device_rx_data = 8'h00; |
|
assign prb_device_rx_parity = 1'b0; |
|
always@(posedge clk) |
if(reset) |
mask_device_rx_parity <= 1'b0; |
else |
mask_device_rx_parity <= 1'b0; |
|
always@(posedge clk) |
if(reset) |
mask_device_rx_data <= 8'b0; |
else |
mask_device_rx_data <= 8'b0; |
|
|
|
reg [23:0] red_h_cnt; |
reg [23:0] green_h_cnt; |
reg [23:0] blue_h_cnt; |
84,7 → 99,7
|
|
/* |
io_probe_def |
io_probe_in |
#(.MESG ("vga data receive error"), |
.WIDTH (8) |
) |
91,7 → 106,6
rx_shift_buffer_prb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz), |
.expected_value( exp_rx_shift_buffer), |
.mask ( mask_rx_shift_buffer), |
.signal ( prb_rx_shift_buffer) |
98,12 → 112,11
); |
|
|
io_probe_def |
io_probe_in |
#(.MESG ("vga parity error")) |
rx_parity_err_prb |
( |
.clk ( clk ), |
.drive_value (1'bz), |
.expected_value( exp_rx_parity_err), |
.mask ( mask_rx_parity_err), |
.signal ( prb_rx_parity_err) |
/opencores.org/Testbench/bfms/vga_model/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Clock and Reset generator for simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/bfms/io_probe/componentCfg.xml
27,5 → 27,38
|
|
|
<socgen:configurations> |
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>MESG</socgen:name><socgen:value>" "</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>RESET</socgen:name><socgen:value>{WIDTH{1'bz}}</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>IN_DELAY</socgen:name><socgen:value>5</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>OUT_DELAY</socgen:name><socgen:value>15</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>OUT_WIDTH</socgen:name><socgen:value>10</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
|
<socgen:configuration> |
<socgen:name>in</socgen:name> |
<socgen:version>in</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>MESG</socgen:name><socgen:value>" "</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>IN_DELAY</socgen:name><socgen:value>5</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
</socgen:configurations> |
|
|
|
|
|
|
</socgen:componentConfiguration> |
/opencores.org/Testbench/bfms/io_probe/rtl/xml/io_probe_in.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
39,35 → 39,9
<spirit:name>io_probe</spirit:name> |
<spirit:version>in</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
76,12 → 50,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.in.sim</spirit:value> |
<spirit:value>io_probe_in</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
94,12 → 64,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.in.syn</spirit:value> |
<spirit:value>io_probe_in</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
145,85 → 111,29
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.in.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body.in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.in.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
307,6 → 217,76
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/io_probe_in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body.in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/io_probe_in</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/io_probe/rtl/xml/io_probe_def.xml
48,24 → 48,6
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
|
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
74,12 → 56,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.sim</spirit:value> |
<spirit:value>io_probe_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
93,138 → 71,41
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.out.syn</spirit:value> |
<spirit:value>io_probe_def</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/top.out.sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/top.out.syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
315,9 → 196,78
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/io_probe_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/top.body</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/io_probe_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/Testbench/bfms/io_probe/rtl/verilog/copyright
0,0 → 1,43
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* io_probe for handling timing delays in dut */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
/opencores.org/Testbench/toolflows/toolflow/xml/ise.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
// // |
// Author : John Eaton Ouabache Designworks // |
41,31 → 41,7
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_root</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_root</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
73,10 → 49,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
83,28 → 55,10
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
117,25 → 71,12
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
<spirit:model> |
|
|
|
|
<spirit:views> |
|
|
|
<spirit:view> |
<spirit:name>syn</spirit:name> |
<spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
143,14 → 84,8
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
</spirit:views> |
|
|
|
</spirit:model> |
|
</spirit:component> |
/opencores.org/Testbench/toolflows/toolflow/xml/icarus.xml
43,6 → 43,27
|
|
<spirit:componentGenerator> |
<spirit:name>gen_elab_filelists</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions> |
<socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier> |
<socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier> |
</spirit:vendorExtensions> |
<spirit:generatorExe>./tools/sys/gen_elab_child_filelist</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>top_file</spirit:name> |
<spirit:value>./TestBench</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_filelists</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
63,6 → 84,8
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_cov_filelist</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
101,10 → 124,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
120,10 → 139,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
139,10 → 154,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>lint</spirit:value> |
</spirit:parameter> |
/opencores.org/Testbench/toolflows/toolflow/xml/verilator.xml
102,10 → 102,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
122,10 → 118,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>lint</spirit:value> |
</spirit:parameter> |
/opencores.org/Testbench/toolflows/toolflow/xml/verilog.xml
42,31 → 42,7
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_root</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_root</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.5</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
</spirit:componentGenerator> |
|
|
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
74,10 → 50,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
94,10 → 66,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
/opencores.org/Testbench/toolflows/toolflow/xml/rtl_check.xml
71,13 → 71,6
<spirit:vendorExtensions><socgen:envIdentifier>:*Lint:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
92,10 → 85,6
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../views</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>lint</spirit:value> |
</spirit:parameter> |
/opencores.org/cde/testbenches/xml/lifo_def_duth.design.xml
0,0 → 1,36
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library cde -component lifo -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>lifo</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="lifo" spirit:version="def" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="SIZE">SIZE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WRITETHRU">WRITETHRU</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/opencores.org/cde/ip/serial/componentCfg.xml
29,8 → 29,43
|
|
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>rcvr</socgen:name> |
<socgen:version>rcvr</socgen:version> |
<socgen:version>both_tb</socgen:version> |
<socgen:version>rcvr_lint</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>BREAK</socgen:name><socgen:value>0</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>STOP_VALUE</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
<socgen:configuration> |
<socgen:name>xmit</socgen:name> |
<socgen:version>xmit</socgen:version> |
<socgen:version>both_tb</socgen:version> |
<socgen:version>xmit_lint</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
|
|
</socgen:configurations> |
|
|
|
|
<socgen:sim> |
|
|
/opencores.org/cde/ip/serial/rtl/xml/cde_serial_rcvr.xml
19,8 → 19,25
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>serial_rcvr</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
32,6 → 49,29
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
142,6 → 182,8
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
|
<spirit:port><spirit:name>frame_err</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
148,6 → 190,11
</spirit:port> |
|
|
<spirit:port><spirit:name>break_detect</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
158,13 → 205,41
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_rcvr</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/serial_rcvr</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
174,9 → 249,26
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/serial_rcvr</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
189,7 → 281,7
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/serial/rtl/xml/cde_serial_xmit.xml
17,10 → 17,25
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>serial_xmit</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
31,7 → 46,39
|
<spirit:model> |
<spirit:views> |
|
|
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
156,13 → 203,42
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/serial_xmit</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/serial_xmit</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
172,9 → 248,25
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/serial_xmit</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/serial/rtl/verilog/copyright.v
File deleted
\ No newline at end of file
/opencores.org/cde/ip/serial/rtl/verilog/serial_xmit
0,0 → 1,114
reg [SIZE-1:0] shift_cnt; |
reg [WIDTH-1:0] shift_buffer; |
reg parity_calc; |
reg delayed_edge_enable; |
|
|
// |
// shift_cnt controls the serial bit out |
// |
// 0 Start bit |
// 1-> WIDTH Data bit lsb first |
// WIDTH+1 Parity bit if enabled |
// 2^SIZE-1 Last stop bit and idle |
|
always@(posedge clk) |
if(reset || buffer_empty) shift_cnt <= {SIZE{1'b1}}; |
else |
if(!edge_enable) shift_cnt <= shift_cnt; |
else |
if(( shift_cnt == {SIZE{1'b1}} ) && ! buffer_empty ) shift_cnt <= {SIZE{1'b0}}; |
else |
if ( shift_cnt == WIDTH) |
case(parity_enable) |
(1'b0): shift_cnt <= {SIZE{1'b1}}; |
(1'b1): shift_cnt <= shift_cnt + 1'b1; |
endcase // case ({two_stop_enable,parity_enable}) |
else |
if ( shift_cnt == (WIDTH+1)) shift_cnt <= {SIZE{1'b1}}; |
else shift_cnt <= shift_cnt + 1'b1; |
|
// |
// |
// Clear buffer_empty upon load pulse |
// set it back at the start of the final stop pulse |
// if load happens BEFORE the next edge_enable then data transfer will have no pauses |
// logic ensures that having load happen on a edge_enable will work |
// |
|
always@(posedge clk) |
if(reset) delayed_edge_enable <= 1'b0; |
else delayed_edge_enable <= edge_enable && ! load; |
|
|
always@(posedge clk) |
if(reset) buffer_empty <= 1'b1; |
else |
if(load) buffer_empty <= 1'b0; |
else |
if((shift_cnt == {SIZE{1'b1}}) && delayed_edge_enable) |
buffer_empty <= 1'b1; |
else buffer_empty <= buffer_empty; |
|
|
|
|
|
// |
// |
// load shift_buffer during start_bit |
// shift down every bit |
// |
// |
always@(posedge clk) |
if(reset) shift_buffer <= {WIDTH{1'b0}}; |
else |
if(load) shift_buffer <= data; |
else |
if(!edge_enable) shift_buffer <= shift_buffer; |
else |
if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= shift_buffer; |
else |
if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= shift_buffer; |
else shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]}; |
|
|
|
|
|
|
// |
// |
// calculate parity on the fly |
// seed reg with 0 for odd and 1 for even |
// force reg to 0 or 1 if needed |
// |
always@(posedge clk) |
if(reset) parity_calc <= 1'b0; |
else |
if(!edge_enable) parity_calc <= parity_calc; |
else |
if(parity_force || (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type; |
else parity_calc <= parity_calc ^ shift_buffer[0]; |
|
|
// send start_bit,data,parity and stop based on shift_cnt |
|
|
always@(posedge clk) |
if(reset) ser_out <= stop_value; |
else |
if( shift_cnt == {SIZE{1'b0}} ) ser_out <= start_value; |
else |
if( shift_cnt == {SIZE{1'b1}} ) ser_out <= stop_value; |
else |
if( shift_cnt == ({SIZE{1'b1}}+1'b1) ) ser_out <= stop_value; |
else |
if( shift_cnt == (WIDTH+1) ) ser_out <= parity_calc; |
else ser_out <= shift_buffer[0]; |
|
|
|
|
|
|
/opencores.org/cde/ip/serial/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/serial/rtl/verilog/serial_rcvr
0,0 → 1,157
reg [SIZE-1:0] shift_cnt; |
|
// |
// shift_cnt controls the serial bit out |
// |
// 0 Start bit |
// 1-> WIDTH Data bit lsb first |
// WIDTH+1 Parity bit if enabled |
// 2^SIZE-1 Last stop bit and idle |
|
always@(posedge clk) |
if( break_detect) |
begin |
shift_cnt <= {SIZE{1'b1}}; |
last_cnt <= 1'b0; |
end |
else |
if(!edge_enable) |
begin |
shift_cnt <= shift_cnt; |
last_cnt <= 1'b0; |
end |
else |
if(( shift_cnt == {SIZE{1'b1}})) |
begin |
shift_cnt <= {SIZE{1'b0}}; |
last_cnt <= 1'b0; |
end |
else |
if ( shift_cnt == WIDTH) |
case( parity_enable ) |
(1'b0): |
begin |
shift_cnt <= {SIZE{1'b1}}; |
last_cnt <= 1'b1; |
end |
|
(1'b1): |
begin |
shift_cnt <= shift_cnt + 1'b1; |
last_cnt <= 1'b0; |
end |
endcase // case (parity_enable) |
else |
if ( shift_cnt == (WIDTH+1)) |
begin |
shift_cnt <= {SIZE{1'b1}}; |
last_cnt <= 1'b1; |
end |
else |
begin |
shift_cnt <= shift_cnt + 1'b1; |
last_cnt <= 1'b0; |
end |
// |
// |
// load shift_buffer during start_bit |
// shift down every bit |
// |
// |
always@(posedge clk) |
if(reset) shift_buffer <= {WIDTH{1'b0}}; |
else |
if(!edge_enable) shift_buffer <= shift_buffer; |
else |
if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= {WIDTH{1'b0}}; |
else |
if(shift_cnt <= WIDTH-1 ) shift_buffer <= {ser_in,shift_buffer[WIDTH-1:1]}; |
else shift_buffer <= shift_buffer; |
// |
// |
// calculate parity on the fly |
// seed reg with 0 for odd and 1 for even |
// force reg to 0 or 1 if needed |
// |
always@(posedge clk) |
if(reset) parity_calc <= 1'b0; |
else |
if(!edge_enable) parity_calc <= parity_calc; |
else |
if(parity_force || (shift_cnt == {SIZE{1'b1}})) parity_calc <= parity_type; |
else |
if(shift_cnt <= WIDTH-1 ) parity_calc <= parity_calc ^ ser_in; |
else parity_calc <= parity_calc; |
// |
// sample parity bit and hold it until next start bit |
// |
always@(posedge clk) |
if(reset) parity_samp <= 1'b0; |
else |
if(!edge_enable) parity_samp <= parity_samp; |
else |
if(shift_cnt == {SIZE{1'b1}}) parity_samp <= 1'b0; |
else |
if(shift_cnt == WIDTH ) parity_samp <= ser_in; |
else parity_samp <= parity_samp; |
// |
// check for stop bit error |
// |
always@(posedge clk) |
if(reset) frame_err <= 1'b0; |
else |
if(!edge_enable) frame_err <= frame_err; |
else |
if(shift_cnt == {SIZE{1'b1}}) frame_err <= 1'b0; |
else |
begin |
case( parity_enable ) |
(1'b0): |
begin |
if(shift_cnt == WIDTH ) frame_err <= ser_in ^ STOP_VALUE; |
else frame_err <= frame_err; |
end |
|
(1'b1): |
begin |
if(shift_cnt == WIDTH+1 ) frame_err <= ser_in ^ STOP_VALUE; |
else frame_err <= frame_err; |
end |
endcase // case (parity_enable) |
end |
|
|
|
|
|
|
|
|
|
|
// |
// create break_detect |
// |
always@(posedge clk) |
if(reset) break_detect <= 1'b1; |
else |
if(BREAK) |
begin |
if(!break_detect) break_detect <= last_cnt && (ser_in ^ STOP_VALUE); |
else break_detect <= (ser_in ^ STOP_VALUE); |
end |
else |
begin |
break_detect <= 1'b0; |
end |
|
|
|
|
|
always@(*) |
if( shift_cnt == {SIZE{1'b1}}) stop_cnt = 1'b1; |
else stop_cnt = 1'b0; |
|
|
|
/opencores.org/cde/ip/serial/doc/Geda/html/cde_serial_rcvr.html
104,6 → 104,12
<td style="vertical-align: top;">Description<br> </td> |
</tr> |
<tr> |
<td style="vertical-align: top;">break_detect<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">clk<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_xmit_lint.xml
19,40 → 19,6
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_both_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>both.tb</spirit:value> |
<spirit:value>serial_both_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
155,7 → 148,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/both.tb</spirit:name> |
<spirit:name>../verilog/common/serial_both_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
168,7 → 161,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/both.tb</spirit:name> |
<spirit:name>../verilog/common/serial_both_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_rcvr_lint.xml
16,39 → 16,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
/opencores.org/cde/ip/mult/componentCfg.xml
35,6 → 35,15
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>generic</socgen:version> |
<socgen:version>generic_tb</socgen:version> |
<socgen:version>generic_lint</socgen:version> |
<socgen:version>serial</socgen:version> |
<socgen:version>serial_tb</socgen:version> |
<socgen:version>serial_lint</socgen:version> |
<socgen:version>ord_r4</socgen:version> |
<socgen:version>ord_r4_tb</socgen:version> |
<socgen:version>ord_r4_lint</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>32</socgen:value></socgen:parameter> |
</socgen:parameters> |
/opencores.org/cde/ip/mult/rtl/xml/cde_mult_ord_r4.xml
18,29 → 18,7
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
49,12 → 27,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.ord_r4</spirit:value> |
<spirit:value>mult_ord_r4</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
121,7 → 95,7
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:name>../verilog/common/top.ord_r4</spirit:name> |
<spirit:name>../verilog/common/mult_ord_r4</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
145,7 → 119,7
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:name>../verilog/common/top.ord_r4</spirit:name> |
<spirit:name>../verilog/common/mult_ord_r4</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/mult/rtl/xml/cde_mult_generic.xml
18,25 → 18,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
46,12 → 28,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.generic</spirit:value> |
<spirit:value>mult_generic</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
122,7 → 100,7
|
|
<spirit:file> |
<spirit:name>../verilog/common/top.generic</spirit:name> |
<spirit:name>../verilog/common/mult_generic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
145,7 → 123,7
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:name>../verilog/common/top.generic</spirit:name> |
<spirit:name>../verilog/common/mult_generic</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/mult/rtl/xml/cde_mult_serial.xml
19,26 → 19,6
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>102.1</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
47,12 → 27,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.serial</spirit:value> |
<spirit:value>mult_serial</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
119,7 → 95,7
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:name>../verilog/common/top.serial</spirit:name> |
<spirit:name>../verilog/common/mult_serial</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
135,7 → 111,7
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:name>../verilog/common/top.serial</spirit:name> |
<spirit:name>../verilog/common/mult_serial</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_serial_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.serial_tb</spirit:value> |
<spirit:value>mult_serial_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
148,7 → 141,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.serial_tb</spirit:name> |
<spirit:name>../verilog/common/mult_serial_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
171,7 → 164,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.serial_tb</spirit:name> |
<spirit:name>../verilog/common/mult_serial_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_serial_lint.xml
19,40 → 19,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_ord_r4_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.ord_r4_tb</spirit:value> |
<spirit:value>mult_ord_r4_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
154,7 → 147,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.ord_r4_tb</spirit:name> |
<spirit:name>../verilog/common/mult_ord_r4_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
174,7 → 167,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.ord_r4_tb</spirit:name> |
<spirit:name>../verilog/common/mult_ord_r4_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_ord_r4_lint.xml
19,40 → 19,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_generic_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.generic_tb</spirit:value> |
<spirit:value>mult_generic_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
150,7 → 143,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.generic_tb</spirit:name> |
<spirit:name>../verilog/common/mult_generic_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
171,7 → 164,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.generic_tb</spirit:name> |
<spirit:name>../verilog/common/mult_generic_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_generic_lint.xml
19,40 → 19,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
/opencores.org/cde/ip/reset/rtl/xml/cde_reset_def.design.xml
23,12 → 23,12
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName></spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="sync" spirit:version="with_reset" /> |
<spirit:instanceName>U1</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="sync" spirit:version="with_reset" /> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName></spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="reset" spirit:version="asyncdisable" /> |
<spirit:instanceName>U2</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="reset" spirit:version="asyncdisable" /> |
</spirit:componentInstance> |
|
</spirit:componentInstances> |
/opencores.org/cde/ip/sram/componentCfg.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
40,12 → 40,19
</socgen:version> |
|
<socgen:version> |
<socgen:name>be</socgen:name> |
<socgen:description>Synchronous one-port ram with byte enable</socgen:description> |
<socgen:name>byte</socgen:name> |
<socgen:description>Synchronous one-port byte wide ram with byte enable</socgen:description> |
</socgen:version> |
|
|
<socgen:version> |
<socgen:name>word</socgen:name> |
<socgen:description>Synchronous one-port word wide ram with byte enable</socgen:description> |
</socgen:version> |
|
|
|
|
</socgen:versions> |
|
|
71,13 → 78,8
<socgen:description>If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new</socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>DEFAULT</socgen:name> |
<socgen:description>Output read value if cs and rd are not both active </socgen:description> |
</socgen:parameter> |
|
|
|
</socgen:parameters> |
|
|
148,8 → 150,58
</socgen:doc> |
|
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:version>dp</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>ADDR</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WORDS</socgen:name><socgen:value>256</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WRITETHRU</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
|
</socgen:parameters> |
</socgen:configuration> |
|
|
|
|
<socgen:configuration> |
<socgen:name>byte</socgen:name> |
<socgen:version>byte</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>ADDR</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WORDS</socgen:name><socgen:value>256</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WRITETHRU</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
|
</socgen:parameters> |
</socgen:configuration> |
|
|
<socgen:configuration> |
<socgen:name>word</socgen:name> |
<socgen:version>word</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>ADDR</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WORDS</socgen:name><socgen:value>256</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WRITETHRU</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
|
</socgen:parameters> |
</socgen:configuration> |
|
|
|
|
|
|
|
|
|
</socgen:configurations> |
|
</socgen:componentConfiguration> |
|
/opencores.org/cde/ip/sram/rtl/xml/sram_be.xml
File deleted
/opencores.org/cde/ip/sram/rtl/xml/sram_def.xml
63,9 → 63,57
</spirit:busInterfaces> |
|
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
117,14 → 165,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
168,15 → 208,44
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
188,10 → 257,23
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
207,7 → 289,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/sram/rtl/xml/sram_byte.xml
16,15 → 16,60
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_byte</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
78,14 → 123,6
</spirit:views> |
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{8'bxxxxxxxx}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
146,13 → 183,40
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
162,8 → 226,25
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_byte</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
177,7 → 258,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/sram/rtl/xml/sram_dp.xml
16,15 → 16,54
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_dp</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
71,18 → 110,7
|
|
|
<spirit:modelParameters> |
|
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
|
</spirit:modelParameters> |
|
|
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
144,44 → 172,63
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:name>fs-sim</spirit:name> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_dp</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
190,12 → 237,16
|
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
/opencores.org/cde/ip/sram/rtl/xml/sram_word.xml
108,9 → 108,53
</spirit:busInterfaces> |
|
|
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sram_word</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
162,13 → 206,6
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
181,7 → 218,7
<spirit:port><spirit:name>addr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
<spirit:vector><spirit:left>ADDR</spirit:left><spirit:right>1</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
218,15 → 255,42
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
238,10 → 302,24
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sram_word</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
257,7 → 335,7
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/sram/rtl/verilog/sram_be.v
File deleted
/opencores.org/cde/ip/sram/rtl/verilog/sram_def
0,0 → 1,41
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
$display("SRAM def %m.mem"); |
$display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
|
|
/opencores.org/cde/ip/sram/rtl/verilog/sram_word.v
23,9 → 23,8
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={16'hffff}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
55,12 → 54,6
if( wr && cs && be[1]) memh[addr[ADDR:1]] <= wdata[15:8]; |
|
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR:1] l_raddr; |
reg l_cycle; |
|
70,9 → 63,17
l_cycle <= rd && cs ; |
end |
|
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [15:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:DEFAULT; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:16'hffff; |
always@(*) rdata = tmp_rdata; |
end |
else |
80,7 → 81,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= {memh[{addr[ADDR:1]}],meml[{addr[ADDR:1]}]} ; |
else rdata <= DEFAULT; |
else rdata <= 16'hffff; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/sram_def.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
47,11 → 46,8
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
61,9 → 57,16
l_cycle <= rd && cs ; |
end |
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
71,7 → 74,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/sram_dp
0,0 → 1,50
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
$display("SRAM dp %m.mem"); |
$display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS); |
end |
|
|
|
|
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
|
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= raddr; |
l_cycle <= rd && cs ; |
end |
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
|
|
/opencores.org/cde/ip/sram/rtl/verilog/sram_byte
0,0 → 1,44
// Memory Array |
reg [7:0] mem[0:WORDS-1]; |
|
initial |
begin |
$display("SRAM byte %m.mem"); |
$display(" AddrBits=%d DataBits = 8 Words = %d ",ADDR,WORDS); |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[7:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= 8'hff; |
end |
endgenerate |
|
|
|
/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_word.v
23,9 → 23,8
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={16'hffff}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
38,7 → 37,7
|
always@(posedge clk) |
if( rd && cs ) rdata <= wdata ; |
else rdata <= DEFAULT; |
else rdata <= 16'hffff; |
|
|
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_def.v
4,10 → 4,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
19,5 → 17,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_byte.v
3,11 → 3,9
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}} |
WRITETHRU=0 |
) |
( |
input wire be, |
input wire clk, |
input wire cs, |
input wire be, |
19,5 → 17,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= 8'hff; |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_dp.v
4,10 → 4,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
20,5 → 18,5
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/sram/rtl/verilog/sram_byte.v
23,8 → 23,7
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT=8'bxxxxxxxx |
WRITETHRU=0 |
) |
( |
|
49,11 → 48,7
// Write function |
always@(posedge clk) |
if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[7:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
64,10 → 59,18
end |
|
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff; |
always@(*) rdata = tmp_rdata; |
end |
else |
75,7 → 78,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= 8'hff; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/sram_dp.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
48,11 → 47,7
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
62,9 → 57,16
l_cycle <= rd && cs ; |
end |
|
|
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
72,7 → 74,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/rtl/verilog/sram_word
0,0 → 1,55
// Memory Array |
reg [7:0] meml[0:WORDS-1]; |
reg [7:0] memh[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
$display("SRAM def %m.mem"); |
$display(" AddrBits=%d DataBits = 16 Words = %d ",ADDR,WORDS); |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs && be[0]) meml[addr[ADDR:1]] <= wdata[7:0]; |
|
|
|
always@(posedge clk) |
if( wr && cs && be[1]) memh[addr[ADDR:1]] <= wdata[15:8]; |
|
|
|
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR:1] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
|
|
generate |
if( WRITETHRU) |
begin |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [15:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:16'hffff; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= {memh[{addr[ADDR:1]}],meml[{addr[ADDR:1]}]} ; |
else rdata <= 16'hffff; |
end |
endgenerate |
|
|
|
/opencores.org/cde/ip/sram/doc/Geda/html/cde_sram_byte.html
21,7 → 21,7
<p style="margin-bottom: 0in;"><a href="#cde_sram_byte">cde_sram_byte<br> |
</a></p> |
<br> |
<br> |
<br> Synchronous one-port byte wide ram with byte enable |
<br> |
<li> |
<p><a href="../src/cde_sram_byte.v">SourceCode <br> |
60,30 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{8'bxxxxxxxx}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/cde/ip/sram/doc/Geda/html/cde_sram_dp.html
60,36 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WIDTH<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of data bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/cde/ip/sram/doc/Geda/html/cde_sram_be.html
84,11 → 84,6
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
</tbody> |
</table> |
/opencores.org/cde/ip/sram/doc/Geda/html/cde_sram_word.html
21,7 → 21,7
<p style="margin-bottom: 0in;"><a href="#cde_sram_word">cde_sram_word<br> |
</a></p> |
<br> |
<br> |
<br> Synchronous one-port word wide ram with byte enable |
<br> |
<li> |
<p><a href="../src/cde_sram_word.v">SourceCode <br> |
47,7 → 47,7
</li> |
</ul> |
</div> |
<img style="width: 613px; height: 278px;" alt="" src="../png/cde_sram_word_sym.png"><br> |
<img style="width: 593px; height: 278px;" alt="" src="../png/cde_sram_word_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
60,30 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
110,7 → 86,7
<td style="vertical-align: top;">Description<br> </td> |
</tr> |
<tr> |
<td style="vertical-align: top;">addr[ADDR-1:0 ]<br> </td> |
<td style="vertical-align: top;">addr[ADDR:1 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Memory address bits<br> </td> |
</tr> |
185,7 → 161,7
<br> |
<br> |
<br> |
<img style="width: 613px; height: 278px;" alt="" src="../png/cde_sram_word_sch.png"><br> |
<img style="width: 593px; height: 278px;" alt="" src="../png/cde_sram_word_sch.png"><br> |
<b><br> |
<br> |
<br> |
/opencores.org/cde/ip/sram/doc/Geda/html/cde_sram_def.html
60,36 → 60,6
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WIDTH<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of data bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/cde/ip/sram/doc/Geda/src/cde_sram_def.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
63,7 → 62,8
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
|
always@(*) rdata = tmp_rdata; |
end |
else |
71,7 → 71,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/doc/Geda/src/cde_sram_byte.v
23,8 → 23,7
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT=8'bxxxxxxxx |
WRITETHRU=0 |
) |
( |
|
67,7 → 66,7
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:8'hff; |
always@(*) rdata = tmp_rdata; |
end |
else |
75,7 → 74,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= 8'hff; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/doc/Geda/src/cde_sram_dp.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
64,7 → 63,7
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
72,7 → 71,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}}; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/doc/Geda/src/cde_sram_be.v
24,9 → 24,8
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
|
input wire clk, |
68,7 → 67,7
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}}; |
always@(*) rdata = tmp_rdata; |
end |
else |
76,7 → 75,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
else rdata <= {WIDTH{1'b1}; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/doc/Geda/src/cde_sram_word.v
23,9 → 23,8
#( parameter |
ADDR=10, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={16'hffff}, |
INIT_FILE="NONE") |
WRITETHRU=0 |
) |
( |
input wire clk, |
input wire cs, |
72,7 → 71,7
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [15:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:DEFAULT; |
assign tmp_rdata = (l_cycle )?{memh[{l_raddr[ADDR:1]}],meml[{l_raddr[ADDR:1]}]}:16'hffff; |
always@(*) rdata = tmp_rdata; |
end |
else |
80,7 → 79,7
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= {memh[{addr[ADDR:1]}],meml[{addr[ADDR:1]}]} ; |
else rdata <= DEFAULT; |
else rdata <= 16'hffff; |
end |
endgenerate |
endmodule |
/opencores.org/cde/ip/sram/doc/html/cde_sram_dp.html
37,9 → 37,7
of clk. <BR>Memory may be initialized from a bit file and later |
overwritten by memory writes. <BR>If WRITETHRU is set to 1 then a |
simultaneous read/write to the same address will read the new data. |
<BR>If set to 0 it will return the old. <BR>Setting DEFAULT |
determines the value of rdata when a read is not |
occurring<BR><BR><BR><BR><IMG SRC="../png/sram_timing.png" NAME="graphics1" ALIGN=BOTTOM WIDTH=724 HEIGHT=544 BORDER=0><BR><B><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR></B><BR><BR> |
<BR>If set to 0 it will return the old. <BR><BR><BR><BR><BR><IMG SRC="../png/sram_timing.png" NAME="graphics1" ALIGN=BOTTOM WIDTH=724 HEIGHT=544 BORDER=0><BR><B><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR></B><BR><BR> |
</P> |
</BODY> |
</HTML> |
</HTML> |
/opencores.org/cde/ip/sram/doc/html/cde_sram_be.html
37,9 → 37,9
of clk. <BR>Memory may be initialized from a bit file and later |
overwritten by memory writes. <BR>If WRITETHRU is set to 1 then a |
simultaneous read/write to the same address will read the new data. |
<BR>If set to 0 it will return the old. <BR>Setting DEFAULT |
determines the value of rdata when a read is not |
occurring<BR><BR><BR><BR><IMG SRC="../png/sram_timing.png" NAME="graphics1" ALIGN=BOTTOM WIDTH=724 HEIGHT=544 BORDER=0><BR><B><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR></B><BR><BR> |
<BR>If set to 0 it will return the old. |
|
<BR><BR><BR><IMG SRC="../png/sram_timing.png" NAME="graphics1" ALIGN=BOTTOM WIDTH=724 HEIGHT=544 BORDER=0><BR><B><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR></B><BR><BR> |
</P> |
</BODY> |
</HTML> |
</HTML> |
/opencores.org/cde/ip/sram/doc/html/cde_sram_def.html
37,9 → 37,11
of clk. <BR>Memory may be initialized from a bit file and later |
overwritten by memory writes. <BR>If WRITETHRU is set to 1 then a |
simultaneous read/write to the same address will read the new data. |
<BR>If set to 0 it will return the old. <BR>Setting DEFAULT |
determines the value of rdata when a read is not |
occurring<BR><BR><BR><BR><IMG SRC="../png/sram_timing.png" NAME="graphics1" ALIGN=BOTTOM WIDTH=724 HEIGHT=544 BORDER=0><BR><B><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR></B><BR><BR> |
<BR>If set to 0 it will return the old. |
|
|
|
<BR><BR><BR><IMG SRC="../png/sram_timing.png" NAME="graphics1" ALIGN=BOTTOM WIDTH=724 HEIGHT=544 BORDER=0><BR><B><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR></B><BR><BR> |
</P> |
</BODY> |
</HTML> |
</HTML> |
/opencores.org/cde/ip/fifo/componentCfg.xml
2,8 → 2,8
<!-- |
|
--> |
<socgen:componentConfiguration |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
<socgen:componentConfiguration |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
|
11,7 → 11,6
<socgen:library>cde</socgen:library> |
<socgen:component>fifo</socgen:component> |
|
|
<socgen:ip_name_depth>3</socgen:ip_name_depth> |
<socgen:ip_name_vendor_sep>_</socgen:ip_name_vendor_sep> |
<socgen:ip_name_library_sep>_</socgen:ip_name_library_sep> |
26,9 → 25,121
|
</socgen:doc> |
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:version>def_tb</socgen:version> |
<socgen:version>def_lint</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>2</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WORDS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
</socgen:parameters> |
|
</socgen:configuration> |
|
</socgen:configurations> |
|
|
<socgen:sim> |
|
<socgen:comp_path>fifo/sim</socgen:comp_path> |
|
<socgen:testbenches> |
|
<socgen:testbench> |
<socgen:variant>fifo_def_tb</socgen:variant> |
<socgen:version>def_tb</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>10000</socgen:value></socgen:parameter> |
</socgen:parameters> |
<socgen:code_coverage> |
<socgen:cover> |
<socgen:name>cde_fifo_def</socgen:name><socgen:componentInstance>TB.test.dut</socgen:componentInstance> |
</socgen:cover> |
</socgen:code_coverage> |
<socgen:tools> |
<socgen:tool>icarus</socgen:tool> |
<socgen:tool>coverage</socgen:tool> |
</socgen:tools> |
</socgen:testbench> |
|
|
|
|
|
<socgen:testbench> |
<socgen:variant>fifo_def_lint</socgen:variant> |
<socgen:version>def_lint</socgen:version> |
<socgen:tools> |
<socgen:tool>rtl_check</socgen:tool> |
</socgen:tools> |
</socgen:testbench> |
|
|
|
|
</socgen:testbenches> |
|
|
|
|
|
|
|
<socgen:rtl_check> |
|
|
|
|
|
<socgen:lint> |
<socgen:name>default</socgen:name> |
<socgen:variant>fifo_def_lint</socgen:variant> |
</socgen:lint> |
|
|
|
</socgen:rtl_check> |
|
|
|
|
|
<socgen:icarus> |
|
|
|
|
|
<socgen:test> |
<socgen:name>default</socgen:name> |
<socgen:variant>fifo_def_tb</socgen:variant> |
<socgen:configuration>default</socgen:configuration> |
</socgen:test> |
|
|
|
|
|
|
|
</socgen:icarus> |
|
|
|
|
|
|
</socgen:sim> |
|
|
|
|
</socgen:componentConfiguration> |
|
/opencores.org/cde/ip/fifo/rtl/xml/cde_fifo_def.design.xml
14,6 → 14,76
<spirit:name>fifo</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
<socgen:node><spirit:name>push_pointer</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>SIZE-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
<socgen:node><spirit:name>pop_pointer</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>SIZE-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
</socgen:nodes> |
</spirit:vendorExtensions> |
|
|
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>push</spirit:name> |
<spirit:externalPortReference spirit:portRef="push"/> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="wr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>push_pointer</spirit:name> |
<spirit:externalPortReference spirit:portRef="push_pointer" spirit:left="SIZE-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="waddr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pop_pointer</spirit:name> |
<spirit:externalPortReference spirit:portRef="pop_pointer" spirit:left="SIZE-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="raddr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>din</spirit:name> |
<spirit:externalPortReference spirit:portRef="din" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="wdata"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>dout</spirit:name> |
<spirit:externalPortReference spirit:portRef="dout" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="rdata"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection spirit:tiedValue="1'b1" > |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="cs"/> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="rd"/> |
</spirit:adHocConnection> |
|
</spirit:adHocConnections> |
|
|
|
|
<spirit:componentInstances> |
|
|
26,7 → 96,6
<spirit:configurableElementValue spirit:referenceId="ADDR">SIZE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WRITETHRU">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="DEFAULT">DEFAULT</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
|
</spirit:componentInstance> |
/opencores.org/cde/ip/fifo/rtl/xml/cde_fifo_def.xml
20,64 → 20,32
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>fifo_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
</spirit:componentGenerators> |
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
90,9 → 58,30
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
102,7 → 91,6
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
110,6 → 98,7
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
132,12 → 121,87
</spirit:views> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/fifo_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/fifo_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>8'hff</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
|
174,7 → 238,7
|
|
<spirit:port><spirit:name>dout</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
/opencores.org/cde/ip/fifo/rtl/verilog/fifo_def.v
File deleted
/opencores.org/cde/ip/fifo/rtl/verilog/fifo_def
0,0 → 1,182
reg r; |
reg w; |
reg [SIZE:0] push_1; |
reg [SIZE:0] pop_1; |
|
always@(*) push_1 = (push_pointer + 1'b1); |
always@(*) pop_1 = (pop_pointer + 1'b1); |
|
|
always@(*) r = (pop_pointer == push_1[SIZE-1:0]); |
always@(*) w = (push_pointer == pop_1[SIZE-1:0]); |
|
|
|
|
always@(posedge clk) |
if(reset) |
begin |
full <= 1'b0; |
empty <= 1'b1; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= {SIZE{1'b0}}; |
pop_pointer <= {SIZE{1'b0}}; |
end |
else |
if(empty && !full) |
if( push && ~pop) |
begin |
full <= 1'b0; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer+1; |
pop_pointer <= pop_pointer; |
end |
else |
if(~push && pop) |
begin |
full <= 1'b0; |
empty <= 1'b1; |
over_run <= 1'b0; |
under_run <= 1'b1; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer; |
end |
else |
if( push && pop) |
begin |
full <= 1'b0; |
empty <= 1'b1; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer + 1; |
pop_pointer <= pop_pointer + 1; |
end |
else |
begin |
full <= 1'b0; |
empty <= 1'b1; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer; |
end |
else |
if(!empty && !full) |
if( push && pop) |
begin |
full <= 1'b0; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer + 1; |
pop_pointer <= pop_pointer + 1; |
end |
else |
if( push && !pop && r) |
begin |
full <= 1'b1; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer+1; |
pop_pointer <= pop_pointer; |
end |
else |
if( push && !pop && !r) |
begin |
full <= 1'b0; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer+1; |
pop_pointer <= pop_pointer; |
end |
else |
if(~push && pop && w) |
begin |
full <= 1'b0; |
empty <= 1'b1; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer+1; |
end |
else |
if(~push && pop && !w) |
begin |
full <= 1'b0; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer+1; |
end |
else |
begin |
full <= 1'b0; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer; |
end |
else |
if(!empty && full) |
if( push && ~pop) |
begin |
full <= 1'b1; |
empty <= 1'b0; |
over_run <= 1'b1; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer; |
end |
else |
if(~push && pop) |
begin |
full <= 1'b0; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer+1; |
end |
else |
if( push && pop) |
begin |
full <= 1'b1; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer + 1; |
pop_pointer <= pop_pointer + 1; |
end |
else |
begin |
full <= 1'b1; |
empty <= 1'b0; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= push_pointer; |
pop_pointer <= pop_pointer; |
end |
// full and empty at the same time should never occur |
|
|
else |
begin |
full <= 1'b0; |
empty <= 1'b1; |
over_run <= 1'b0; |
under_run <= 1'b0; |
push_pointer <= {SIZE{1'b0}}; |
pop_pointer <= {SIZE{1'b0}}; |
end |
|
|
|
|
|
/opencores.org/cde/ip/fifo/doc/Geda/html/cde_fifo_def.html
78,12 → 78,6
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">8'hff<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/cde/ip/fifo/sim/icarus/default/test_define
0,0 → 1,37
|
|
initial |
begin |
$display(" "); |
$display(" ==================================================="); |
$display(" Test Start"); |
$display(" ==================================================="); |
$display(" "); |
test.cg.next(20); |
test.write.u_write(8'h00, 8'h01); |
test.cg.next(4); |
test.read.u_cmp(8'h00, 8'h01); |
test.cg.next(4); |
test.write.u_write(8'h00, 8'h02); |
test.cg.next(4); |
test.read.u_cmp(8'h00, 8'h02); |
test.cg.next(4); |
test.write.u_write(8'h00, 8'h03); |
test.cg.next(4); |
test.read.u_cmp(8'h00, 8'h03); |
test.cg.next(4); |
test.write.u_write(8'h00, 8'h04); |
test.cg.next(1); |
test.read.u_cmp(8'h00, 8'h04); |
test.cg.next(4); |
|
test.cg.exit; |
end |
|
|
|
|
|
|
|
|
/opencores.org/cde/ip/fifo/sim/icarus/default/wave.sav
0,0 → 1,42
[*] |
[*] GTKWave Analyzer v3.3.62 (w)1999-2014 BSI |
[*] Fri May 29 00:14:27 2015 |
[*] |
[dumpfile] "/home/johne/Desktop/socgen/work/opencores.org__cde/ip/fifo/sim/icarus/default/TestBench.vcd" |
[dumpfile_mtime] "Fri May 29 00:12:25 2015" |
[dumpfile_size] 5636 |
[savefile] "/home/johne/Desktop/socgen/common/opencores.org/cde/ip/fifo/sim/icarus/default/wave.sav" |
[timestart] 270 |
[size] 1613 999 |
[pos] 211 19 |
*-8.000000 1410 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
[treeopen] TB. |
[treeopen] TB.test. |
[treeopen] TB.test.dut. |
[treeopen] TB.test.read. |
[treeopen] TB.test.write. |
[sst_width] 223 |
[signals_width] 238 |
[sst_expanded] 1 |
[sst_vpaned_height] 300 |
@28 |
TB.test.reset |
TB.test.clk |
TB.test.reset |
TB.test.push |
@22 |
TB.test.din[7:0] |
@28 |
TB.test.pop |
@22 |
TB.test.dout[7:0] |
@28 |
TB.test.dut.push_pointer[1:0] |
TB.test.dut.pop_pointer[1:0] |
TB.test.full |
TB.test.over_run |
TB.test.under_run |
@29 |
TB.test.empty |
[pattern_trace] 1 |
[pattern_trace] 0 |
/opencores.org/cde/ip/fifo/sim/icarus/default/dmp_define
0,0 → 1,7
$dumpfile ("TestBench.vcd"); |
$dumpvars (0, TB.test); |
|
|
|
|
|
/opencores.org/cde/ip/fifo/sim/testbenches/xml/cde_fifo_def_tb.xml
0,0 → 1,172
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>fifo</spirit:name> |
<spirit:version>def_tb</spirit:version> |
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>fifo_def_tb</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:modelParameters> |
</spirit:modelParameters> |
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>Params</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="fifo" |
spirit:version="def_dut.params"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>Bfm</spirit:name> |
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="fifo" |
spirit:version="bfm.design"/> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>icarus</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="icarus"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-lint</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
</spirit:views> |
|
|
|
|
</spirit:model> |
|
|
|
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/fifo_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/fifo_def_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/fifo/sim/testbenches/xml/cde_fifo_def_lint.xml
0,0 → 1,102
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>fifo</spirit:name> |
<spirit:version>def_lint</spirit:version> |
|
|
|
<spirit:componentGenerators> |
|
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>Dut</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="fifo" |
spirit:version="def_dut.params"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>lint</spirit:name> |
<spirit:envIdentifier>:*Lint:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>rtl_check</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="rtl_check"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
</spirit:views> |
|
|
|
</spirit:model> |
|
|
|
|
|
|
|
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/lint/fifo_def_lint</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/fifo/sim/testbenches/xml/cde_fifo_bfm.design.xml
0,0 → 1,105
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>fifo</spirit:name> |
<spirit:version>bfm.design</spirit:version> |
|
|
|
|
|
|
|
|
|
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset"/> |
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="reset"/> |
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="reset"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pop</spirit:name> |
<spirit:externalPortReference spirit:portRef="pop"/> |
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="rd"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>push</spirit:name> |
<spirit:externalPortReference spirit:portRef="push"/> |
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="wr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>din</spirit:name> |
<spirit:externalPortReference spirit:portRef="din" spirit:left="7" spirit:right="0"/> |
<spirit:internalPortReference spirit:componentRef="write" spirit:portRef="wdata" /> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>dout</spirit:name> |
<spirit:externalPortReference spirit:portRef="dout" spirit:left="7" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="read" spirit:portRef="rdata" /> |
</spirit:adHocConnection> |
|
|
|
|
|
</spirit:adHocConnections> |
|
<spirit:componentInstances> |
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>write</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="micro_bus_model" spirit:version="def"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="addr_width">8</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>read</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="micro_bus_model" spirit:version="def"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="addr_width">8</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
|
|
|
</spirit:componentInstances> |
|
|
|
|
</spirit:design> |
/opencores.org/cde/ip/fifo/sim/testbenches/xml/cde_fifo_def_dut.params.xml
0,0 → 1,34
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// // |
// // |
// // |
// // |
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>fifo</spirit:name> |
<spirit:version>def_dut.params</spirit:version> |
<spirit:model> |
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>Dut</spirit:name> |
<spirit:envIdentifier></spirit:envIdentifier> |
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="fifo" |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
|
</spirit:model> |
</spirit:component> |
/opencores.org/cde/ip/fifo/sim/testbenches/xml/fifo_def_duth.design.xml
0,0 → 1,95
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library cde -component fifo -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>fifo</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>din</spirit:name> |
<spirit:externalPortReference spirit:portRef="din" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="din" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>dout</spirit:name> |
<spirit:externalPortReference spirit:portRef="dout" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dout" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>empty</spirit:name> |
<spirit:externalPortReference spirit:portRef="empty" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="empty" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>full</spirit:name> |
<spirit:externalPortReference spirit:portRef="full" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="full" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>over_run</spirit:name> |
<spirit:externalPortReference spirit:portRef="over_run" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="over_run" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pop</spirit:name> |
<spirit:externalPortReference spirit:portRef="pop" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pop" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>push</spirit:name> |
<spirit:externalPortReference spirit:portRef="push" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="push" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>under_run</spirit:name> |
<spirit:externalPortReference spirit:portRef="under_run" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="under_run" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="fifo" spirit:version="def" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="SIZE">SIZE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/opencores.org/cde/ip/fifo/sim/bin/Makefile
0,0 → 1,3
include ../../../../bin/Makefile.root |
|
|
/opencores.org/cde/ip/pad/rtl/xml/cde_pad_tri_dig.xml
51,11 → 51,60
</spirit:busInterfaces> |
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_tri_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
118,19 → 167,54
</spirit:model> |
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_tri_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:fileSets> |
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_tri_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
140,9 → 224,24
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_tri_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
156,7 → 255,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/pad/rtl/xml/cde_pad_od_dig.xml
62,14 → 62,66
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_od_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_syn</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_od_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
138,10 → 190,29
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_od_sim</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/pad_od_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
151,9 → 222,28
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_od_syn</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/pad_od_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
167,7 → 257,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/pad/rtl/xml/cde_pad_in_dig.xml
56,15 → 56,59
</spirit:busInterfaces> |
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_in_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
134,12 → 178,43
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_in_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_in_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
148,9 → 223,25
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_in_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
165,7 → 256,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/pad/rtl/xml/cde_pad_out_dig.xml
57,13 → 57,58
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_out_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
129,13 → 174,40
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_out_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_out_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
145,9 → 217,24
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_out_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
161,7 → 248,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/pad/rtl/xml/cde_pad_se0_dig.xml
61,12 → 61,63
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_se0_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
150,13 → 201,47
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_se0_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_se0_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
166,9 → 251,22
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_se0_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
182,7 → 280,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/pad/rtl/xml/cde_pad_se_dig.xml
61,12 → 61,59
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>pad_se_dig</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
149,13 → 196,47
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/pad_se_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_se_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
165,9 → 246,23
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/pad_se_dig</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
181,7 → 276,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/pad/rtl/verilog/pad_od_syn
0,0 → 1,8
assign pad_in = PAD; |
assign PAD = pad_oe ? 1'b0 : 1'bz; |
|
|
|
|
|
|
/opencores.org/cde/ip/pad/rtl/verilog/pad_tri_dig
0,0 → 1,3
assign PAD = pad_oe ? pad_out : 1'bz; |
|
|
/opencores.org/cde/ip/pad/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/pad/rtl/verilog/pad_in_dig
0,0 → 1,7
|
|
assign pad_in = PAD; |
|
|
|
|
/opencores.org/cde/ip/pad/rtl/verilog/pad_se_dig
0,0 → 1,5
assign pad_in = PAD; |
assign PAD = pad_oe ? pad_out : {WIDTH{1'bz}}; |
|
|
|
/opencores.org/cde/ip/pad/rtl/verilog/pad_out_dig
0,0 → 1,5
|
assign PAD = pad_out; |
|
|
|
/opencores.org/cde/ip/pad/rtl/verilog/pad_od_sim
0,0 → 1,8
assign pad_in = PAD; |
assign PAD = pad_oe ? 1'b0 : 1'bz; |
|
pullup u0(PAD); |
|
|
|
|
/opencores.org/cde/ip/pad/rtl/verilog/pad_se0_dig
0,0 → 1,12
assign pad_in = PAD; |
|
generate |
genvar i; |
for (i=0; i < 40; i=i+1) begin:m |
assign PAD[i] = pad_oe[i] ? pad_out[i] : {1'bz}; |
end |
endgenerate |
|
|
|
|
/opencores.org/cde/ip/jtag/componentCfg.xml
34,6 → 34,8
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>tap</socgen:version> |
<socgen:version>tap_lint</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>INST_LENGTH</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>INST_RETURN</socgen:name><socgen:value>4'b1101</socgen:value></socgen:parameter> |
69,11 → 71,33
|
|
|
<socgen:configuration> |
<socgen:name>reg</socgen:name> |
<socgen:version>classic_rpc_reg</socgen:version> |
<socgen:version>classic_rpc_in_reg</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>BITS</socgen:name><socgen:value>16</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>RESET_VALUE</socgen:name><socgen:value>16'h0000</socgen:value></socgen:parameter> |
</socgen:parameters> |
|
</socgen:configuration> |
|
|
|
</socgen:configurations> |
|
|
|
|
|
|
|
|
|
|
|
|
|
<socgen:sim> |
|
<socgen:comp_path>jtag/sim</socgen:comp_path> |
116,14 → 140,8
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>100000</socgen:value></socgen:parameter> |
</socgen:parameters> |
<socgen:code_coverage> |
<socgen:cover> |
<socgen:name>cde_jtag_tap</socgen:name><socgen:componentInstance>TB.test.dut</socgen:componentInstance> |
</socgen:cover> |
</socgen:code_coverage> |
<socgen:tools> |
<socgen:tool>icarus</socgen:tool> |
<socgen:tool>coverage</socgen:tool> |
</socgen:tools> |
</socgen:testbench> |
|
136,22 → 154,13
<socgen:parameter><socgen:name>PERIOD</socgen:name><socgen:value>40</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>TIMEOUT</socgen:name><socgen:value>100000</socgen:value></socgen:parameter> |
</socgen:parameters> |
<socgen:code_coverage> |
<socgen:cover> |
<socgen:name>cde_jtag_tap</socgen:name><socgen:componentInstance>TB.test.dut</socgen:componentInstance> |
</socgen:cover> |
</socgen:code_coverage> |
<socgen:tools> |
<socgen:tool>icarus</socgen:tool> |
<socgen:tool>coverage</socgen:tool> |
</socgen:tools> |
</socgen:testbench> |
|
|
|
|
|
|
<socgen:testbench> |
<socgen:variant>jtag_tap_lint</socgen:variant> |
<socgen:version>tap_lint</socgen:version> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_rpc_reg.xml
22,66 → 22,60
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_rpc_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
</spirit:componentGenerators> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
181,7 → 175,7
|
|
<spirit:port><spirit:name>update_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
197,9 → 191,96
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
77,60 → 77,62
|
|
|
<spirit:componentGenerators> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_classic_rpc_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
</spirit:componentGenerators> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:model> |
<spirit:views> |
|
</spirit:fileSet> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
</spirit:fileSets> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
170,6 → 172,98
|
|
|
|
|
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
</spirit:fileSets> |
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
188,7 → 282,7
|
|
<spirit:port><spirit:name>update_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
209,4 → 303,9
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_tap.xml
255,44 → 255,22
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_sim</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_tap</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>sim</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilogLib_syn</spirit:name> |
<spirit:phase>105.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>view</spirit:name> |
<spirit:value>syn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
313,11 → 291,33
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="jtag" |
spirit:version="def.design"/> |
spirit:version="tap.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
359,87 → 359,51
</spirit:views> |
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h12345678</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
|
|
</spirit:modelParameters> |
|
|
<spirit:ports> |
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:port><spirit:name>tap_highz_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tap</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:port><spirit:name>bsr_output_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_tdo_i</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>jtag_clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>update_dr_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_select_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
</spirit:fileSet> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
<spirit:fileSets> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_tap</spirit:name> |
<spirit:name>../verilog/common/jtag_tap</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/sim/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
455,12 → 419,17
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_tap</spirit:name> |
<spirit:name>../verilog/common/jtag_tap</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
467,7 → 436,7
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
480,7 → 449,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
489,15 → 458,76
|
|
|
</spirit:fileSets> |
|
|
|
</spirit:fileSets> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h00000000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter> |
|
|
</spirit:modelParameters> |
|
|
<spirit:ports> |
|
|
|
|
<spirit:port><spirit:name>tap_highz_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_output_mode</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_tdo_i</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>jtag_clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>update_dr_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>bsr_select_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
14,59 → 14,59
<spirit:name>jtag</spirit:name> |
<spirit:version>rpc_in_reg</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:busInterfaces> |
|
|
</spirit:componentGenerators> |
<spirit:busInterface><spirit:name>jtag</spirit:name> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/> |
<spirit:slave/> |
<spirit:portMaps> |
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>capture_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>shift_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
</spirit:fileSet> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdi</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdo</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdo</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>select</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>select</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
|
</spirit:fileSet> |
|
|
</spirit:portMaps> |
</spirit:busInterface> |
|
<spirit:fileSet> |
</spirit:busInterfaces> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
73,13 → 73,66
|
|
|
<spirit:componentGenerators> |
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_rpc_in_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
119,6 → 172,99
|
|
|
|
|
<spirit:fileSets> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/jtag_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
126,11 → 272,16
|
<spirit:ports> |
|
|
|
|
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
137,33 → 288,11
</spirit:port> |
|
|
<spirit:port><spirit:name>tdi</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>select</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>capture_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>shift_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>tdo</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>capture_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
175,6 → 304,7
|
|
|
|
</spirit:ports> |
|
</spirit:model> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
14,59 → 14,71
<spirit:name>jtag</spirit:name> |
<spirit:version>classic_rpc_in_reg</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
<spirit:componentGenerators> |
|
|
|
|
|
<spirit:busInterfaces> |
|
</spirit:componentGenerators> |
|
<spirit:busInterface><spirit:name>jtag</spirit:name> |
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/> |
<spirit:slave/> |
<spirit:portMaps> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>test_logic_reset</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>test_logic_reset</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSets> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>capture_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>shift_dr</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>update_dr_clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>update_dr_clk</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
</spirit:fileSet> |
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdi</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>tdo</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>tdo</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
<spirit:portMap> |
<spirit:logicalPort><spirit:name>select</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>select</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
|
<spirit:portMap> |
<spirit:logicalPort><spirit:name>shiftcapture_dr_clk</spirit:name></spirit:logicalPort> |
<spirit:physicalPort><spirit:name>shiftcapture_dr_clk</spirit:name></spirit:physicalPort> |
</spirit:portMap> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
</spirit:portMaps> |
</spirit:busInterface> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
</spirit:busInterfaces> |
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
74,10 → 86,71
|
|
|
|
|
|
|
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_classic_rpc_in_reg</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
118,51 → 191,110
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
<spirit:fileSets> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>shiftcapture_dr_clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>test_logic_reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/classic_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:port><spirit:name>tdi</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>select</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:port><spirit:name>capture_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>shift_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:fileSet> |
|
<spirit:port><spirit:name>tdo</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_rpc_in_reg</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
|
<spirit:port><spirit:name>capture_value</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_sync.xml
122,14 → 122,63
</spirit:busInterfaces> |
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_sync</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
196,7 → 245,29
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_tap.design.xml
0,0 → 1,287
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
|
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>jtag</spirit:name> |
<spirit:version>tap.design</spirit:version> |
|
|
<spirit:vendorExtensions><socgen:nodes> |
|
|
<socgen:node><spirit:name>tclk</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>tclk_n</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>tap_state</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>next_tap_state</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
<socgen:node><spirit:name>shift_ir</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>update_ir</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>capture_ir</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
|
|
<socgen:node><spirit:name>next_tdo</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>bypass_tdo</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>chip_id_tdo</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>chip_id_select</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
<socgen:node><spirit:name>bypass_select</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>extest</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>sample</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>clamp</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
|
</socgen:node> |
|
|
<socgen:node><spirit:name>bsr_output_mode</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>shiftcapture_dr</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>aux_update_dr_o</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>aux_jtag_clk</spirit:name> |
<spirit:typeName>wire</spirit:typeName> |
</socgen:node> |
|
|
|
|
|
</socgen:nodes></spirit:vendorExtensions> |
|
|
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>jtag_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_clk"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>trst_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="trst_pad_in"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="reset"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdi_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="JTAG_INT_JTAG_TDI_PAD_IN"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="tdi"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>chip_id_select</spirit:name> |
<spirit:externalPortReference spirit:portRef="chip_id_select"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="select"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>chip_id_tdo</spirit:name> |
<spirit:externalPortReference spirit:portRef="chip_id_tdo"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="tdo"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>capture_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_capture_dr"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="capture_dr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>shift_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_shift_dr"/> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="shift_dr"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection> |
<spirit:name>tclk</spirit:name> |
<spirit:externalPortReference spirit:portRef="tclk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="clk_in"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="clk_in"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="clk_in"/> |
</spirit:adHocConnection> |
|
|
|
|
|
<spirit:adHocConnection> |
<spirit:name>jtag_shift_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_shift_clk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="clk_out"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>update_dr_clk_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_update_dr_clk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="clk_out"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>jtag_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_clk"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="clk_out"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>shiftcapture_dr</spirit:name> |
<spirit:externalPortReference spirit:portRef="shiftcapture_dr"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="enable"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>update_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="update_dr_o"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="enable"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>chip_id_value</spirit:name> |
<spirit:externalPortReference spirit:portRef="chip_id_value" spirit:left="31" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="chip_id_reg" spirit:portRef="capture_value"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection spirit:tiedValue="1'b1" > |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="enable"/> |
</spirit:adHocConnection> |
|
|
|
<spirit:adHocConnection spirit:tiedValue="1'b0" > |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_shift_clk" spirit:portRef="atg_clk_mode"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_update_clk" spirit:portRef="atg_clk_mode"/> |
<spirit:internalPortReference spirit:componentRef="clk_gater_jtag_clk" spirit:portRef="atg_clk_mode"/> |
</spirit:adHocConnection> |
|
|
|
|
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>clk_gater_jtag_shift_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" /> |
</spirit:componentInstance> |
|
<spirit:componentInstance> |
<spirit:instanceName>clk_gater_jtag_update_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" /> |
</spirit:componentInstance> |
|
<spirit:componentInstance> |
<spirit:instanceName>clk_gater_jtag_clk</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="gater" /> |
</spirit:componentInstance> |
|
|
|
<spirit:componentInstance> |
<spirit:instanceName>chip_id_reg</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_in_reg" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="BITS">32</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RESET_VALUE">CHIP_ID_VAL</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
</spirit:componentInstances> |
|
|
|
|
|
</spirit:design> |
/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_classic_sync.xml
137,12 → 137,62
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>jtag_classic_sync</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
193,6 → 243,39
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_shift_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_capture_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>syn_update_dr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>syn_tdi_o</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>syn_select</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
</spirit:ports> |
|
</spirit:model> |
207,12 → 290,43
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/classic_sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
223,9 → 337,28
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/jtag_classic_sync</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
240,7 → 373,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
/opencores.org/cde/ip/jtag/rtl/verilog/classic_rpc_reg
0,0 → 1,26
|
|
// shift buffer and shadow |
reg [BITS-1:0] buffer; |
|
always @(posedge shiftcapture_dr_clk or posedge test_logic_reset) |
if (test_logic_reset) buffer <= RESET_VALUE; |
else |
if (select && capture_dr) buffer <= capture_value; |
else |
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] }; |
else buffer <= buffer; |
|
|
always @(posedge update_dr_clk or posedge test_logic_reset) |
if (test_logic_reset) update_value <= RESET_VALUE; |
else |
if (select) update_value <= buffer; |
else update_value <= update_value; |
|
|
|
|
assign tdo = buffer[0]; |
|
|
/opencores.org/cde/ip/jtag/rtl/verilog/tap
0,0 → 1,286
//******************************************************************** |
//*** assignments for 2nd channel |
//******************************************************************** |
|
|
assign aux_jtag_clk = jtag_clk; |
assign aux_update_dr_clk_o = update_dr_clk_o; |
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o; |
assign aux_test_logic_reset_o = test_logic_reset_o; |
assign aux_tdi_o = tdi_o; |
assign aux_capture_dr_o = capture_dr_o; |
assign aux_shift_dr_o = shift_dr_o; |
assign aux_update_dr_o = update_dr_o; |
|
assign chip_id_value = CHIP_ID_VAL ; |
|
//******************************************************************** |
//*** TAP Controller State Machine |
//******************************************************************** |
|
|
// TAP state parameters |
localparam TEST_LOGIC_RESET = 4'b1111, |
RUN_TEST_IDLE = 4'b1100, |
SELECT_DR_SCAN = 4'b0111, |
CAPTURE_DR = 4'b0110, |
SHIFT_DR = 4'b0010, |
EXIT1_DR = 4'b0001, |
PAUSE_DR = 4'b0011, |
EXIT2_DR = 4'b0000, |
UPDATE_DR = 4'b0101, |
SELECT_IR_SCAN = 4'b0100, |
CAPTURE_IR = 4'b1110, |
SHIFT_IR = 4'b1010, |
EXIT1_IR = 4'b1001, |
PAUSE_IR = 4'b1011, |
EXIT2_IR = 4'b1000, |
UPDATE_IR = 4'b1101; |
|
|
|
// next state decode for tap controller |
always @(*) |
case (tap_state) // synopsys parallel_case |
TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE; |
RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE; |
SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR; |
CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR; |
SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR; |
EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR; |
PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR; |
EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR; |
UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE; |
SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR; |
CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR; |
SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR; |
EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR; |
PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR; |
EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR; |
UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE; |
endcase |
|
|
//******************************************************************** |
//*** TAP Controller State Machine Register |
//******************************************************************** |
|
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET; |
else tap_state <= next_tap_state; |
|
|
// Decode tap_state to get Shift, Update, and Capture signals |
|
|
|
always @(*) |
begin |
shift_ir = (tap_state == SHIFT_IR); |
shift_dr_o = (tap_state == SHIFT_DR); |
update_ir = (tap_state == UPDATE_IR); |
update_dr_o = (tap_state == UPDATE_DR); |
capture_dr_o = (tap_state == CAPTURE_DR); |
capture_ir = (tap_state == CAPTURE_IR); |
end |
|
|
// Decode tap_state to get test_logic_reset signal |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) test_logic_reset_o <= 1'b1; |
else |
if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1; |
else test_logic_reset_o <= 1'b0; |
|
|
//****************************************************** |
//*** Instruction Register |
//****************************************************** |
|
reg [INST_LENGTH-1:0] instruction_buffer; |
reg [INST_LENGTH-1:0] instruction; |
|
// buffer the instruction register while shifting |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) instruction_buffer <= INST_RESET; |
else |
if (capture_ir) instruction_buffer <= INST_RETURN; |
else |
if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]}; |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) instruction <= INST_RESET; |
else |
if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET; |
else |
if (update_ir) instruction <= instruction_buffer; |
|
|
|
|
|
|
assign tclk = tclk_pad_in; |
assign tclk_n = !tclk_pad_in; |
assign shiftcapture_dr = shift_dr_o || capture_dr_o; |
assign tdi_o = tdi_pad_in; |
assign trst_pad_in = !trst_n_pad_in; |
|
// Instruction Decoder |
assign extest = ( instruction == EXTEST ); |
assign sample = ( instruction == SAMPLE ); |
assign clamp = ( instruction == CLAMP ); |
assign chip_id_select = ( instruction == CHIP_ID_ACCESS ); |
|
|
// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode |
|
assign bypass_select = ( instruction == CLAMP ) || ( instruction == BYPASS ); |
|
assign shiftcapture_dr_clk_o = jtag_shift_clk; |
assign select_o = ( instruction == RPC_ADD ); |
assign aux_select_o = ( instruction == RPC_DATA ); |
assign bsr_select_o = ( instruction == EXTEST ) || ( instruction == SAMPLE ) ; |
|
|
|
|
//********************************************************** |
//** Boundary scan control signals |
//********************************************************** |
|
|
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) bsr_output_mode <= 1'b0; |
else |
if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0; |
else |
if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST) |
|| (instruction_buffer == CLAMP); |
|
|
// Control chip pads when we are in highz_mode |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) tap_highz_mode <= 1'b0; |
else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0; |
else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE); |
|
|
|
|
|
|
//********************************************************** |
//*** Bypass register |
//********************************************************** |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) bypass_tdo <= 1'b0; |
else |
if (capture_dr_o) bypass_tdo <= 1'b0; |
else |
if (shift_dr_o) bypass_tdo <= tdi_pad_in; |
else bypass_tdo <= bypass_tdo; |
|
|
//**************************************************************** |
//*** Choose what goes out on the TDO pin |
//**************************************************************** |
|
|
// output the instruction register when tap_state[3] is 1, else |
// put out the appropriate data register. |
|
|
|
always@(*) |
begin |
if( tap_state[3] ) next_tdo = instruction_buffer[0]; |
else |
if(bypass_select) next_tdo = bypass_tdo; |
else |
if(chip_id_select) next_tdo = chip_id_tdo; |
else |
if(select_o) next_tdo = tdo_i; |
else |
if(aux_select_o) next_tdo = aux_tdo_i; |
else next_tdo = 1'b0; |
end |
|
|
reg tdo_pad_out_reg; |
reg tdo_pad_oe_reg; |
|
always @(posedge tclk_n or negedge trst_n_pad_in) |
if (!trst_n_pad_in) tdo_pad_out_reg <= 1'b0; |
else tdo_pad_out_reg <= next_tdo; |
|
|
|
// output enable for TDO pad |
|
always @(posedge tclk_n or negedge trst_n_pad_in) |
if ( !trst_n_pad_in ) tdo_pad_oe_reg <= 1'b0; |
else tdo_pad_oe_reg <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) ); |
|
|
|
assign tdo_pad_out = tdo_pad_out_reg; |
assign tdo_pad_oe = tdo_pad_oe_reg; |
|
`ifndef SYNTHESYS |
|
reg [8*16-1:0] tap_string; |
|
always @(tap_state) begin |
case (tap_state) |
TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET"; |
RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE"; |
SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN"; |
CAPTURE_DR: tap_string = "CAPTURE_DR"; |
SHIFT_DR: tap_string = "SHIFT_DR"; |
EXIT1_DR: tap_string = "EXIT1_DR"; |
PAUSE_DR: tap_string = "PAUSE_DR"; |
EXIT2_DR: tap_string = "EXIT2_DR"; |
UPDATE_DR: tap_string = "UPDATE_DR"; |
SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN"; |
CAPTURE_IR: tap_string = "CAPTURE_IR"; |
SHIFT_IR: tap_string = "SHIFT_IR"; |
EXIT1_IR: tap_string = "EXIT1_IR"; |
PAUSE_IR: tap_string = "PAUSE_IR"; |
EXIT2_IR: tap_string = "EXIT2_IR"; |
UPDATE_IR: tap_string = "UPDATE_IR"; |
default: tap_string = "-XXXXXX-"; |
endcase |
|
$display("%t %m Tap State = %s",$realtime, tap_string); |
end |
|
|
|
|
reg [8*16-1:0] inst_string; |
|
always @(instruction) begin |
case (instruction) |
EXTEST: inst_string = "EXTEST"; |
SAMPLE: inst_string = "SAMPLE"; |
HIGHZ_MODE: inst_string = "HIGHZ_MODE"; |
CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS"; |
CLAMP: inst_string = "CLAMP"; |
RPC_DATA: inst_string = "RPC_DATA"; |
RPC_ADD: inst_string = "RPC_ADD"; |
BYPASS: inst_string = "BYPASS"; |
default: inst_string = "-XXXXXX-"; |
endcase |
|
$display("%t %m Instruction = %s",$realtime, inst_string); |
end |
|
`endif |
|
/opencores.org/cde/ip/jtag/rtl/verilog/jtag_rpc_reg
0,0 → 1,25
|
|
// shift buffer and shadow |
reg [BITS-1:0] buffer; |
|
always @(posedge clk or posedge reset) |
if (reset) buffer <= RESET_VALUE; |
else |
if (select && capture_dr) buffer <= capture_value; |
else |
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] }; |
else buffer <= buffer; |
|
|
always @(posedge update_dr or posedge reset) |
if (reset) update_value <= RESET_VALUE; |
else |
if (select) update_value <= buffer; |
else update_value <= update_value; |
|
|
|
|
assign tdo = buffer[0]; |
|
/opencores.org/cde/ip/jtag/rtl/verilog/jtag_tap
24,76 → 24,56
|
cde_jtag_tap |
#( parameter |
BYPASS=4'b1111, |
CHIP_ID_ACCESS=4'b0011, |
CHIP_ID_VAL=32'h12345678, |
CLAMP=4'b1000, |
EXTEST=4'b0000, |
HIGHZ_MODE=4'b0010, |
INST_LENGTH=4, |
INST_RESET=4'b1111, |
INST_RETURN=4'b1101, |
INST_RESET=4'b1111, |
NUM_USER=2, |
USER=8'b1010_1001, |
EXTEST=4'b0000, |
RPC_ADD=4'b1001, |
RPC_DATA=4'b1010, |
SAMPLE=4'b0001, |
HIGHZ_MODE=4'b0010, |
CHIP_ID_ACCESS=4'b0011, |
CLAMP=4'b1000, |
RPC_DATA=4'b1010, |
RPC_ADD=4'b1001, |
BYPASS=4'b1111, |
CHIP_ID_VAL=32'h12345678) |
USER=8'b1010_1001) |
|
( |
input wire aux_tdo_i, |
input wire bsr_tdo_i, |
input wire tclk_pad_in, |
input wire tdi_pad_in, |
input wire tdo_i, |
input wire tms_pad_in, |
input wire trst_n_pad_in, |
output wire tdo_pad_oe, |
output wire tdo_pad_out, |
|
|
output wire jtag_clk, |
output wire update_dr_clk_o, |
output wire shiftcapture_dr_clk_o, |
|
|
output wire aux_jtag_clk, |
output wire aux_update_dr_clk_o, |
output wire aux_shiftcapture_dr_clk_o, |
|
|
|
|
output reg test_logic_reset_o, |
|
output wire aux_test_logic_reset_o, |
|
|
output wire tdi_o, |
|
output wire aux_tdi_o, |
|
|
|
input wire tdo_i, |
input wire aux_tdo_i, |
input wire bsr_tdo_i, |
|
|
|
output reg bsr_output_mode, |
output reg capture_dr_o, |
output reg shift_dr_o, |
output reg tap_highz_mode, |
output reg test_logic_reset_o, |
output reg update_dr_o, |
|
|
|
output wire aux_capture_dr_o, |
output wire aux_select_o, |
output wire aux_shift_dr_o, |
output wire aux_update_dr_o, |
|
|
output reg tap_highz_mode, |
output reg bsr_output_mode, |
|
output wire aux_shiftcapture_dr_clk_o, |
output wire aux_tdi_o, |
output wire aux_test_logic_reset_o, |
output wire aux_update_dr_clk_o, |
|
output wire tdi_o, |
output wire select_o, |
output wire aux_select_o, |
|
output wire bsr_select_o |
output wire tdo_pad_oe, |
output wire tdo_pad_out, |
output wire jtag_clk, |
output wire update_dr_clk_o, |
output wire shiftcapture_dr_clk_o, |
output wire bsr_select_o |
); |
|
|
113,21 → 93,14
wire clamp; |
wire extest; |
wire sample; |
wire shift_capture_dr; |
wire tclk; |
wire tclk_n; |
wire trst_pad_in; |
wire jtag_shift_clk; |
wire aux_update_dr_o; |
wire aux_jtag_clk; |
|
|
assign aux_jtag_clk = jtag_clk; |
assign aux_update_dr_clk_o = update_dr_clk_o; |
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o; |
assign aux_test_logic_reset_o = test_logic_reset_o; |
assign aux_tdi_o = tdi_o; |
assign aux_capture_dr_o = capture_dr_o; |
assign aux_shift_dr_o = shift_dr_o; |
assign aux_update_dr_o = update_dr_o; |
|
//////////////////////////////////////////////////////////////// |
cde_clock_gater |
136,7 → 109,7
.atg_clk_mode (1'b0), |
.clk_in (tclk), |
.clk_out (jtag_shift_clk), |
.enable (shift_capture_dr)); |
.enable (shiftcapture_dr)); |
|
cde_clock_gater |
clk_gater_jtag_update_clk |
173,7 → 146,30
.tdi (tdi_pad_in), |
.tdo (chip_id_tdo)); |
|
|
|
|
|
|
|
|
//******************************************************************** |
//*** assignments for 2nd channel |
//******************************************************************** |
|
|
assign aux_jtag_clk = jtag_clk; |
assign aux_update_dr_clk_o = update_dr_clk_o; |
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o; |
assign aux_test_logic_reset_o = test_logic_reset_o; |
assign aux_tdi_o = tdi_o; |
assign aux_capture_dr_o = capture_dr_o; |
assign aux_shift_dr_o = shift_dr_o; |
assign aux_update_dr_o = update_dr_o; |
|
|
|
//******************************************************************** |
//*** TAP Controller State Machine |
//******************************************************************** |
|
284,7 → 280,7
|
assign tclk = tclk_pad_in; |
assign tclk_n = !tclk_pad_in; |
assign shift_capture_dr = shift_dr_o || capture_dr_o; |
assign shiftcapture_dr = shift_dr_o || capture_dr_o; |
assign tdi_o = tdi_pad_in; |
assign trst_pad_in = !trst_n_pad_in; |
|
/opencores.org/cde/ip/jtag/rtl/verilog/top
0,0 → 1,286
//******************************************************************** |
//*** assignments for 2nd channel |
//******************************************************************** |
|
|
assign aux_jtag_clk = jtag_clk; |
assign aux_update_dr_clk_o = update_dr_clk_o; |
assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o; |
assign aux_test_logic_reset_o = test_logic_reset_o; |
assign aux_tdi_o = tdi_o; |
assign aux_capture_dr_o = capture_dr_o; |
assign aux_shift_dr_o = shift_dr_o; |
assign aux_update_dr_o = update_dr_o; |
|
|
|
//******************************************************************** |
//*** TAP Controller State Machine |
//******************************************************************** |
|
|
// TAP state parameters |
localparam TEST_LOGIC_RESET = 4'b1111, |
RUN_TEST_IDLE = 4'b1100, |
SELECT_DR_SCAN = 4'b0111, |
CAPTURE_DR = 4'b0110, |
SHIFT_DR = 4'b0010, |
EXIT1_DR = 4'b0001, |
PAUSE_DR = 4'b0011, |
EXIT2_DR = 4'b0000, |
UPDATE_DR = 4'b0101, |
SELECT_IR_SCAN = 4'b0100, |
CAPTURE_IR = 4'b1110, |
SHIFT_IR = 4'b1010, |
EXIT1_IR = 4'b1001, |
PAUSE_IR = 4'b1011, |
EXIT2_IR = 4'b1000, |
UPDATE_IR = 4'b1101; |
|
|
|
// next state decode for tap controller |
always @(*) |
case (tap_state) // synopsys parallel_case |
TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE; |
RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE; |
SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR; |
CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR; |
SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR; |
EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR; |
PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR; |
EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR; |
UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE; |
SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR; |
CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR; |
SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR; |
EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR; |
PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR; |
EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR; |
UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE; |
endcase |
|
|
//******************************************************************** |
//*** TAP Controller State Machine Register |
//******************************************************************** |
|
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET; |
else tap_state <= next_tap_state; |
|
|
// Decode tap_state to get Shift, Update, and Capture signals |
|
|
|
always @(*) |
begin |
shift_ir = (tap_state == SHIFT_IR); |
shift_dr_o = (tap_state == SHIFT_DR); |
update_ir = (tap_state == UPDATE_IR); |
update_dr_o = (tap_state == UPDATE_DR); |
capture_dr_o = (tap_state == CAPTURE_DR); |
capture_ir = (tap_state == CAPTURE_IR); |
end |
|
|
// Decode tap_state to get test_logic_reset signal |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) test_logic_reset_o <= 1'b1; |
else |
if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1; |
else test_logic_reset_o <= 1'b0; |
|
|
//****************************************************** |
//*** Instruction Register |
//****************************************************** |
|
reg [INST_LENGTH-1:0] instruction_buffer; |
reg [INST_LENGTH-1:0] instruction; |
|
// buffer the instruction register while shifting |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) instruction_buffer <= INST_RESET; |
else |
if (capture_ir) instruction_buffer <= INST_RETURN; |
else |
if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]}; |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) instruction <= INST_RESET; |
else |
if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET; |
else |
if (update_ir) instruction <= instruction_buffer; |
|
|
|
|
|
|
assign tclk = tclk_pad_in; |
assign tclk_n = !tclk_pad_in; |
assign shift_capture_dr = shift_dr_o || capture_dr_o; |
assign tdi_o = tdi_pad_in; |
assign trst_pad_in = !trst_n_pad_in; |
|
// Instruction Decoder |
assign extest = ( instruction == EXTEST ); |
assign sample = ( instruction == SAMPLE ); |
assign clamp = ( instruction == CLAMP ); |
assign chip_id_select = ( instruction == CHIP_ID_ACCESS ); |
|
|
// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode |
|
assign bypass_select = ( instruction == CLAMP ) || ( instruction == BYPASS ); |
|
assign shiftcapture_dr_clk_o = jtag_shift_clk; |
assign select_o = ( instruction == RPC_ADD ); |
assign aux_select_o = ( instruction == RPC_DATA ); |
assign bsr_select_o = ( instruction == EXTEST ) || ( instruction == SAMPLE ) ; |
|
|
|
|
//********************************************************** |
//** Boundary scan control signals |
//********************************************************** |
|
|
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) bsr_output_mode <= 1'b0; |
else |
if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0; |
else |
if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST) |
|| (instruction_buffer == CLAMP); |
|
|
// Control chip pads when we are in highz_mode |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) tap_highz_mode <= 1'b0; |
else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0; |
else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE); |
|
|
|
|
|
|
//********************************************************** |
//*** Bypass register |
//********************************************************** |
|
always @(posedge jtag_clk or negedge trst_n_pad_in) |
if (!trst_n_pad_in) bypass_tdo <= 1'b0; |
else |
if (capture_dr_o) bypass_tdo <= 1'b0; |
else |
if (shift_dr_o) bypass_tdo <= tdi_pad_in; |
else bypass_tdo <= bypass_tdo; |
|
|
//**************************************************************** |
//*** Choose what goes out on the TDO pin |
//**************************************************************** |
|
|
// output the instruction register when tap_state[3] is 1, else |
// put out the appropriate data register. |
|
|
|
always@(*) |
begin |
if( tap_state[3] ) next_tdo = instruction_buffer[0]; |
else |
if(bypass_select) next_tdo = bypass_tdo; |
else |
if(chip_id_select) next_tdo = chip_id_tdo; |
else |
if(select_o) next_tdo = tdo_i; |
else |
if(aux_select_o) next_tdo = aux_tdo_i; |
else next_tdo = 1'b0; |
end |
|
|
reg tdo_pad_out_reg; |
reg tdo_pad_oe_reg; |
|
always @(posedge tclk_n or negedge trst_n_pad_in) |
if (!trst_n_pad_in) tdo_pad_out_reg <= 1'b0; |
else tdo_pad_out_reg <= next_tdo; |
|
|
|
// output enable for TDO pad |
|
always @(posedge tclk_n or negedge trst_n_pad_in) |
if ( !trst_n_pad_in ) tdo_pad_oe_reg <= 1'b0; |
else tdo_pad_oe_reg <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) ); |
|
|
|
assign tdo_pad_out = tdo_pad_out_reg; |
assign tdo_pad_oe = tdo_pad_oe_reg; |
|
`ifndef SYNTHESYS |
|
reg [8*16-1:0] tap_string; |
|
always @(tap_state) begin |
case (tap_state) |
TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET"; |
RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE"; |
SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN"; |
CAPTURE_DR: tap_string = "CAPTURE_DR"; |
SHIFT_DR: tap_string = "SHIFT_DR"; |
EXIT1_DR: tap_string = "EXIT1_DR"; |
PAUSE_DR: tap_string = "PAUSE_DR"; |
EXIT2_DR: tap_string = "EXIT2_DR"; |
UPDATE_DR: tap_string = "UPDATE_DR"; |
SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN"; |
CAPTURE_IR: tap_string = "CAPTURE_IR"; |
SHIFT_IR: tap_string = "SHIFT_IR"; |
EXIT1_IR: tap_string = "EXIT1_IR"; |
PAUSE_IR: tap_string = "PAUSE_IR"; |
EXIT2_IR: tap_string = "EXIT2_IR"; |
UPDATE_IR: tap_string = "UPDATE_IR"; |
default: tap_string = "-XXXXXX-"; |
endcase |
|
$display("%t %m Tap State = %s",$realtime, tap_string); |
end |
|
|
|
|
reg [8*16-1:0] inst_string; |
|
always @(instruction) begin |
case (instruction) |
EXTEST: inst_string = "EXTEST"; |
SAMPLE: inst_string = "SAMPLE"; |
HIGHZ_MODE: inst_string = "HIGHZ_MODE"; |
CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS"; |
CLAMP: inst_string = "CLAMP"; |
RPC_DATA: inst_string = "RPC_DATA"; |
RPC_ADD: inst_string = "RPC_ADD"; |
BYPASS: inst_string = "BYPASS"; |
default: inst_string = "-XXXXXX-"; |
endcase |
|
$display("%t %m Instruction = %s",$realtime, inst_string); |
end |
|
`endif |
|
/opencores.org/cde/ip/jtag/rtl/verilog/copyright
0,0 → 1,21
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012-2015 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
|
/opencores.org/cde/ip/jtag/rtl/verilog/classic_rpc_in_reg
0,0 → 1,17
// shift buffer and shadow |
reg [BITS-1:0] buffer; |
|
always @(posedge shiftcapture_dr_clk or posedge test_logic_reset) |
if (test_logic_reset) buffer <= RESET_VALUE; |
else |
if (select && capture_dr) buffer <= capture_value; |
else |
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] }; |
else buffer <= buffer; |
|
|
|
|
assign tdo = buffer[0]; |
|
|
/opencores.org/cde/ip/jtag/rtl/verilog/sync
0,0 → 1,7
assign syn_clk = clk; |
assign syn_select = select; |
assign syn_tdo = tdi; |
assign tdo = syn_tdi; |
assign syn_capture_dr = capture_dr; |
assign syn_shift_dr = shift_dr ; |
assign syn_update_dr = update_dr; |
/opencores.org/cde/ip/jtag/rtl/verilog/jtag_rpc_in_reg
0,0 → 1,19
|
|
// shift buffer and shadow |
reg [BITS-1:0] buffer; |
|
always @(posedge clk or posedge reset) |
if (reset) buffer <= RESET_VALUE; |
else |
if (select && capture_dr) buffer <= capture_value; |
else |
if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] }; |
else buffer <= buffer; |
|
|
|
|
assign tdo = buffer[0]; |
|
|
/opencores.org/cde/ip/jtag/rtl/verilog/classic_sync
0,0 → 1,122
reg synced_reset; |
|
always@(posedge clk or posedge test_logic_reset ) |
if(test_logic_reset) |
begin |
synced_reset <= 1'b1; |
syn_reset <= 1'b1; |
end |
else |
begin |
synced_reset <= test_logic_reset; |
syn_reset <= synced_reset; |
end |
|
|
reg synced_shift_dr; |
reg synced_capture_dr; |
|
|
|
|
always@(posedge clk) |
if(!shiftcapture_dr_clk) |
begin |
synced_shift_dr <= shift_dr ; |
synced_capture_dr <= capture_dr ; |
end |
|
else |
begin |
synced_shift_dr <= synced_shift_dr ; |
synced_capture_dr <= synced_capture_dr ; |
end |
|
|
reg [1:0] synced_shiftcapture_dr_clk; |
|
|
always@(posedge clk) |
synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk}; |
|
|
reg [1:0] synced_update_dr_clk; |
|
|
always@(posedge clk) |
synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk}; |
|
|
|
always@(posedge clk) |
if(synced_shiftcapture_dr_clk == 2'b01) |
begin |
syn_shift_dr <= synced_shift_dr ; |
syn_capture_dr <= synced_capture_dr ; |
end |
else |
begin |
syn_shift_dr <= 1'b0 ; |
syn_capture_dr <= 1'b0 ; |
end |
|
|
|
always@(posedge clk) |
if(synced_update_dr_clk == 2'b01) |
begin |
syn_update_dr <= 1'b1 ; |
end |
else |
begin |
syn_update_dr <= 1'b0 ; |
end |
|
|
|
always@(posedge clk) |
if(!shiftcapture_dr_clk && (shift_dr || capture_dr )) |
begin |
syn_tdi_o <= tdi ; |
end |
|
else |
begin |
syn_tdi_o <= syn_tdi_o ; |
end |
|
|
|
|
|
|
|
|
|
|
always@(posedge clk) |
if(synced_update_dr_clk == 2'b01) |
begin |
syn_select <= select; |
end |
else if(synced_shiftcapture_dr_clk == 2'b01) |
begin |
syn_select <= select; |
end |
|
else |
begin |
syn_select <= syn_select; |
end |
|
|
|
|
|
|
|
|
assign syn_clk = clk; |
assign tdo = syn_tdo_i; |
|
|
/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_tap.html
80,7 → 80,7
|
<tr> |
<td style="vertical-align: top;">CHIP_ID_VAL<br> </td> |
<td style="vertical-align: top;">32'h12345678<br> </td> |
<td style="vertical-align: top;">32'h00000000<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_classic_rpc_in_reg.html
47,7 → 47,7
</li> |
</ul> |
</div> |
<img style="width: 613px; height: 278px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sym.png"><br> |
<img style="width: 613px; height: 302px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
145,6 → 145,12
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">update_dr_clk<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;"><br> </td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
173,7 → 179,7
<br> |
<br> |
<br> |
<img style="width: 613px; height: 278px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sch.png"><br> |
<img style="width: 613px; height: 302px;" alt="" src="../png/cde_jtag_classic_rpc_in_reg_sch.png"><br> |
<b><br> |
<br> |
<br> |
/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_classic_sync_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.classic_sync</spirit:value> |
<spirit:value>jtag_classic_sync_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
167,7 → 160,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.classic_sync</spirit:name> |
<spirit:name>../verilog/common/jtag_classic_sync_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
179,7 → 172,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.classic_sync</spirit:name> |
<spirit:name>../verilog/common/jtag_classic_sync_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_tap_duth.design.xml
0,0 → 1,214
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library cde -component jtag -version tap // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>jtag</spirit:name> |
<spirit:version>tap_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>aux_capture_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_capture_dr_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_capture_dr_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_select_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_select_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_select_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_shift_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_shift_dr_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_shift_dr_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_shiftcapture_dr_clk_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_shiftcapture_dr_clk_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_shiftcapture_dr_clk_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_tdi_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_tdi_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_tdi_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_tdo_i</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_tdo_i" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_tdo_i" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_test_logic_reset_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_test_logic_reset_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_test_logic_reset_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>aux_update_dr_clk_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="aux_update_dr_clk_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="aux_update_dr_clk_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>bsr_output_mode</spirit:name> |
<spirit:externalPortReference spirit:portRef="bsr_output_mode" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bsr_output_mode" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>bsr_select_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="bsr_select_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bsr_select_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>bsr_tdo_i</spirit:name> |
<spirit:externalPortReference spirit:portRef="bsr_tdo_i" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="bsr_tdo_i" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>capture_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="capture_dr_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="capture_dr_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>jtag_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="jtag_clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="jtag_clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>select_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="select_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="select_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>shift_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="shift_dr_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="shift_dr_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>shiftcapture_dr_clk_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="shiftcapture_dr_clk_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="shiftcapture_dr_clk_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tap_highz_mode</spirit:name> |
<spirit:externalPortReference spirit:portRef="tap_highz_mode" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tap_highz_mode" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tclk_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="tclk_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tclk_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdi_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="tdi_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdi_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdi_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="tdi_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdi_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdo_i</spirit:name> |
<spirit:externalPortReference spirit:portRef="tdo_i" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdo_i" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdo_pad_oe</spirit:name> |
<spirit:externalPortReference spirit:portRef="tdo_pad_oe" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdo_pad_oe" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tdo_pad_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="tdo_pad_out" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tdo_pad_out" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>test_logic_reset_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="test_logic_reset_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="test_logic_reset_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>tms_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="tms_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="tms_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>trst_n_pad_in</spirit:name> |
<spirit:externalPortReference spirit:portRef="trst_n_pad_in" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="trst_n_pad_in" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>update_dr_clk_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="update_dr_clk_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="update_dr_clk_o" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>update_dr_o</spirit:name> |
<spirit:externalPortReference spirit:portRef="update_dr_o" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="update_dr_o" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="tap" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="BYPASS">BYPASS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CHIP_ID_ACCESS">CHIP_ID_ACCESS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CHIP_ID_VAL">CHIP_ID_VAL</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="CLAMP">CLAMP</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="EXTEST">EXTEST</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="HIGHZ_MODE">HIGHZ_MODE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="INST_LENGTH">INST_LENGTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="INST_RESET">INST_RESET</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="INST_RETURN">INST_RETURN</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="NUM_USER">NUM_USER</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RPC_ADD">RPC_ADD</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RPC_DATA">RPC_DATA</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="SAMPLE">SAMPLE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="USER">USER</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_classic_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb.classic</spirit:value> |
<spirit:value>jtag_classic_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
144,9 → 137,6
<spirit:name>fs-common</spirit:name> |
|
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/tb.rpc_2</spirit:name> |
167,7 → 157,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.classic</spirit:name> |
<spirit:name>../verilog/common/jtag_classic_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
179,7 → 169,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb.classic</spirit:name> |
<spirit:name>../verilog/common/jtag_classic_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_tap_tb.xml
30,15 → 30,8
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>top.tb</spirit:value> |
<spirit:value>jtag_tap_tb</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>../verilog</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>top</spirit:name> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
167,7 → 160,7
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/jtag_tap_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
179,7 → 172,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/top.tb</spirit:name> |
<spirit:name>../verilog/common/jtag_tap_tb</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_tap_lint.xml
18,40 → 18,7
|
<spirit:componentGenerators> |
|
<spirit:componentGenerator> |
<spirit:name>elab_verilog</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>configuration</spirit:name> |
<spirit:value>default</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
<spirit:componentGenerator> |
<spirit:name>gen_design</spirit:name> |
<spirit:phase>103.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions |
> |
<spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>dest_dir</spirit:name> |
<spirit:value>io_ports</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
/opencores.org/cde/ip/divider/rtl/xml/cde_divider_def.xml
22,68 → 22,55
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>divider_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
</spirit:componentGenerators> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
170,8 → 157,92
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/divider_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/divider_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/divider_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/divider/rtl/verilog/copyright.v
File deleted
\ No newline at end of file
/opencores.org/cde/ip/divider/rtl/verilog/divider_def
0,0 → 1,19
reg [SIZE-1:0] divide_cnt; |
|
always@(posedge clk) |
if(reset) divider_out <= RESET; |
else |
if(!enable) divider_out <= 1'b0; |
else divider_out <= ( divide_cnt == SAMPLE ); |
|
always@(posedge clk) |
if(reset) divide_cnt <= divider_in; |
else |
if(!enable) divide_cnt <= divide_cnt; |
else |
if(!(|divide_cnt)) divide_cnt <= divider_in; |
else divide_cnt <= divide_cnt - 'b1; |
|
|
|
|
/opencores.org/cde/ip/divider/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/lifo/componentCfg.xml
25,8 → 25,82
|
</socgen:doc> |
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:version>def_lint</socgen:version> |
|
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>8</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>SIZE</socgen:name><socgen:value>2</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WORDS</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>WRITETHRU</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
</socgen:parameters> |
|
</socgen:configuration> |
|
</socgen:configurations> |
|
|
<socgen:sim> |
|
<socgen:comp_path>lifo/sim</socgen:comp_path> |
|
<socgen:testbenches> |
|
|
|
<socgen:testbench> |
<socgen:variant>lifo_def_lint</socgen:variant> |
<socgen:version>def_lint</socgen:version> |
<socgen:tools> |
<socgen:tool>rtl_check</socgen:tool> |
</socgen:tools> |
</socgen:testbench> |
|
|
|
|
</socgen:testbenches> |
|
|
|
|
|
|
|
<socgen:rtl_check> |
|
|
|
|
|
<socgen:lint> |
<socgen:name>default</socgen:name> |
<socgen:variant>lifo_def_lint</socgen:variant> |
</socgen:lint> |
|
|
|
</socgen:rtl_check> |
|
|
|
|
|
|
|
|
|
|
</socgen:sim> |
|
|
|
|
</socgen:componentConfiguration> |
|
/opencores.org/cde/ip/lifo/rtl/xml/cde_lifo_def.xml
19,6 → 19,19
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>lifo_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
26,57 → 39,9
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
89,9 → 54,33
spirit:version="def.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
130,13 → 119,100
|
|
|
|
<spirit:fileSets> |
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/lifo_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/lifo_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>8'hff</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter> |
|
|
</spirit:modelParameters> |
|
<spirit:ports> |
172,7 → 248,7
|
|
<spirit:port><spirit:name>dout</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
/opencores.org/cde/ip/lifo/rtl/xml/cde_lifo_def.design.xml
14,11 → 14,74
<spirit:name>lifo</spirit:name> |
<spirit:version>def.design</spirit:version> |
|
<spirit:vendorExtensions> |
|
<socgen:nodes> |
|
|
|
<socgen:node><spirit:name>push_pointer</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>SIZE-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
<socgen:node><spirit:name>pop_pointer</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
<spirit:wire><spirit:vector><spirit:left>SIZE-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</socgen:node> |
|
|
</socgen:nodes> |
</spirit:vendorExtensions> |
|
|
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk"/> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>push</spirit:name> |
<spirit:externalPortReference spirit:portRef="push"/> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="wr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>push_pointer</spirit:name> |
<spirit:externalPortReference spirit:portRef="push_pointer" spirit:left="SIZE-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="waddr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pop_pointer</spirit:name> |
<spirit:externalPortReference spirit:portRef="pop_pointer" spirit:left="SIZE-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="raddr"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>din</spirit:name> |
<spirit:externalPortReference spirit:portRef="din" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="wdata"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>dout</spirit:name> |
<spirit:externalPortReference spirit:portRef="dout" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="rdata"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection spirit:tiedValue="1'b1" > |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="cs"/> |
<spirit:internalPortReference spirit:componentRef="fifo" spirit:portRef="rd"/> |
</spirit:adHocConnection> |
|
</spirit:adHocConnections> |
|
|
<spirit:componentInstances> |
|
<spirit:componentInstance> |
29,7 → 92,6
<spirit:configurableElementValue spirit:referenceId="ADDR">SIZE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WRITETHRU">WRITETHRU</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="DEFAULT">DEFAULT</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
|
</spirit:componentInstance> |
/opencores.org/cde/ip/lifo/rtl/verilog/lifo_def.v
File deleted
/opencores.org/cde/ip/lifo/rtl/verilog/copyright.v
File deleted
\ No newline at end of file
/opencores.org/cde/ip/lifo/rtl/verilog/lifo_def
0,0 → 1,19
always@(posedge clk) |
if(reset) push_pointer <= {SIZE{1'b0}}; |
else |
if( push && ~pop) push_pointer <= push_pointer + 1; |
else |
if(~push && pop) push_pointer <= push_pointer - 1; |
else |
push_pointer <= push_pointer; |
|
|
always@(posedge clk) |
if(reset) pop_pointer <= {SIZE{1'b1}}; |
else |
if( push && ~pop) pop_pointer <= pop_pointer + 1; |
else |
if(~push && pop) pop_pointer <= pop_pointer - 1; |
else |
pop_pointer <= pop_pointer; |
|
/opencores.org/cde/ip/lifo/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012-2015 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/lifo/doc/Geda/html/cde_lifo_def.html
80,16 → 80,10
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">1<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">8'hff<br> </td> |
<td style="vertical-align: top;"><br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
/opencores.org/cde/ip/lifo/sim/testbenches/xml/cde_lifo_def_dut.params.xml
0,0 → 1,40
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// // |
// // |
// // |
// // |
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>lifo</spirit:name> |
<spirit:version>def_dut.params</spirit:version> |
<spirit:model> |
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>Dut</spirit:name> |
<spirit:envIdentifier></spirit:envIdentifier> |
<spirit:hierarchyRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="lifo" |
spirit:version="def_duth.design"/> |
</spirit:view> |
</spirit:views> |
<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>SIZE</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
</spirit:model> |
</spirit:component> |
/opencores.org/cde/ip/lifo/sim/testbenches/xml/lifo_def_duth.design.xml
0,0 → 1,72
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
// // |
// Generated File Do Not EDIT // |
// // |
// ./tools/verilog/gen_tb -vendor opencores.org -library cde -component lifo -version def // |
// // |
--> |
<spirit:design |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>lifo</spirit:name> |
<spirit:version>def_duth.design</spirit:version> |
<spirit:adHocConnections> |
|
<spirit:adHocConnection> |
<spirit:name>clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="clk" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="clk" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>din</spirit:name> |
<spirit:externalPortReference spirit:portRef="din" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="din" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>dout</spirit:name> |
<spirit:externalPortReference spirit:portRef="dout" spirit:left="WIDTH-1" spirit:right="0" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="dout" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pop</spirit:name> |
<spirit:externalPortReference spirit:portRef="pop" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="pop" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>push</spirit:name> |
<spirit:externalPortReference spirit:portRef="push" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="push" /> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset" /> |
<spirit:internalPortReference spirit:componentRef="dut" spirit:portRef="reset" /> |
</spirit:adHocConnection> |
|
|
</spirit:adHocConnections> |
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName>dut</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="lifo" spirit:version="def" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="SIZE">SIZE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">WIDTH</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WORDS">WORDS</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="WRITETHRU">WRITETHRU</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/opencores.org/cde/ip/lifo/sim/testbenches/xml/cde_lifo_def_lint.xml
0,0 → 1,102
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>lifo</spirit:name> |
<spirit:version>def_lint</spirit:version> |
|
|
|
<spirit:componentGenerators> |
|
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>Dut</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="cde" |
spirit:name="lifo" |
spirit:version="def_dut.params"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>lint</spirit:name> |
<spirit:envIdentifier>:*Lint:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>rtl_check</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="rtl_check"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
</spirit:views> |
|
|
|
</spirit:model> |
|
|
|
|
|
|
|
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/lint/lifo_def_lint</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
|
</spirit:fileSets> |
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/lifo/sim/bin/Makefile
0,0 → 1,3
include ../../../../bin/Makefile.root |
|
|
/opencores.org/cde/ip/clock/rtl/xml/cde_clock_dll.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?> |
<?xml version="1.0" encoding="utf-8"?> |
<!-- |
|
--> |
22,68 → 22,68
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_dll</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog_sim</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_dll</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
</spirit:componentGenerators> |
|
|
|
<spirit:fileSets> |
</spirit:componentGenerators> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:model> |
<spirit:views> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
<spirit:view> |
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
135,20 → 135,16
</spirit:port> |
|
|
<spirit:port><spirit:name>dll_clk_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>reset</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>dll_clk_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
|
<spirit:port><spirit:name>div_clk_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
162,4 → 158,106
|
|
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/timescale</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/dll</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sim/clock_dll</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/dll</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/syn/clock_dll</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/clock/rtl/xml/cde_clock_sys.xml
16,18 → 16,7
|
|
|
<spirit:componentGenerators> |
|
|
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
<spirit:busInterfaces> |
|
<spirit:busInterface><spirit:name>clock</spirit:name> |
58,8 → 47,34
</spirit:busInterfaces> |
|
|
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_sys</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
<spirit:model> |
<spirit:views> |
|
72,7 → 87,31
spirit:version="sys.design"/> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
138,7 → 177,7
</spirit:port> |
|
<spirit:port><spirit:name>div_clk_out</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire> |
</spirit:port> |
|
164,13 → 203,42
|
<spirit:fileSets> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_sys</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/clock_sys</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
181,9 → 249,24
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/clock_sys</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
197,7 → 280,7
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
</spirit:fileSet> |
/opencores.org/cde/ip/clock/rtl/xml/cde_clock_gater.xml
20,68 → 20,56
<spirit:componentGenerators> |
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>clock_gater</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
</spirit:componentGenerators> |
|
|
<spirit:fileSets> |
</spirit:componentGenerators> |
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
<spirit:model> |
<spirit:views> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
</spirit:fileSet> |
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
<spirit:model> |
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
|
158,12 → 146,93
|
|
|
<spirit:fileSets> |
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/clock_gater</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/clock_gater</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/clock_gater</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
|
<spirit:name>fs-lint</spirit:name> |
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
|
|
|
</spirit:fileSets> |
|
|
|
|
|
|
|
|
|
|
|
|
|
</spirit:component> |
/opencores.org/cde/ip/clock/rtl/xml/cde_clock_sys.design.xml
16,25 → 16,131
|
|
|
<spirit:vendorExtensions><socgen:nodes> |
|
|
|
|
<socgen:node><spirit:name>ref_reset</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
<socgen:node><spirit:name>pwron_reset_n</spirit:name> |
<spirit:typeName>reg</spirit:typeName> |
</socgen:node> |
|
|
|
|
</socgen:nodes> |
|
</spirit:vendorExtensions> |
|
|
<spirit:adHocConnections> |
|
|
<spirit:adHocConnection> |
<spirit:name>ckIn</spirit:name> |
<spirit:externalPortReference spirit:portRef="ckIn"/> |
<spirit:internalPortReference spirit:componentRef="dll" spirit:portRef="ref_clk"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>pwron_reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="pwron_reset"/> |
<spirit:internalPortReference spirit:componentRef="dll" spirit:portRef="reset"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>pwron_reset_n</spirit:name> |
<spirit:externalPortReference spirit:portRef="pwron_reset_n"/> |
<spirit:internalPortReference spirit:componentRef="dll_rsync" spirit:portRef="reset_n"/> |
<spirit:internalPortReference spirit:componentRef="ref_rsync" spirit:portRef="reset_n"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>ref_reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="ref_reset"/> |
<spirit:internalPortReference spirit:componentRef="dll_rsync" spirit:portRef="data_in"/> |
<spirit:internalPortReference spirit:componentRef="ref_rsync" spirit:portRef="data_in"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset"/> |
<spirit:internalPortReference spirit:componentRef="ref_rsync" spirit:portRef="data_out"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>dll_reset</spirit:name> |
<spirit:externalPortReference spirit:portRef="dll_reset"/> |
<spirit:internalPortReference spirit:componentRef="dll_rsync" spirit:portRef="data_out"/> |
</spirit:adHocConnection> |
|
<spirit:adHocConnection> |
<spirit:name>dll_clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="dll_clk"/> |
<spirit:internalPortReference spirit:componentRef="dll" spirit:portRef="dll_clk_out"/> |
<spirit:internalPortReference spirit:componentRef="dll_rsync" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
<spirit:adHocConnection> |
<spirit:name>div_clk_out</spirit:name> |
<spirit:externalPortReference spirit:portRef="div_clk_out"/> |
<spirit:internalPortReference spirit:componentRef="dll" spirit:portRef="div_clk_out"/> |
<spirit:internalPortReference spirit:componentRef="ref_rsync" spirit:portRef="clk"/> |
</spirit:adHocConnection> |
|
|
|
|
|
</spirit:adHocConnections> |
|
|
|
<spirit:componentInstances> |
|
<spirit:componentInstance> |
<spirit:instanceName></spirit:instanceName> |
<spirit:instanceName>dll</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="dll" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="MULT">PLL_MULT</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="DIV">PLL_DIV</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="SIZE">PLL_SIZE</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName>ref_rsync</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="sync" spirit:version="with_reset" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="DEPTH">2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RST_VAL">1'b1</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
<spirit:componentInstance> |
<spirit:instanceName></spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="clock" spirit:version="dll" /> |
<spirit:instanceName>dll_rsync</spirit:instanceName> |
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="sync" spirit:version="with_reset" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="DEPTH">2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RST_VAL">1'b1</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
|
|
|
|
</spirit:componentInstances> |
|
|
/opencores.org/cde/ip/clock/rtl/verilog/timescale
0,0 → 1,131
`timescale 1 ns / 10ps |
/opencores.org/cde/ip/clock/rtl/verilog/sim/dll
0,0 → 1,65
localparam MIN_CLK_DELAY = 0.01; |
|
|
//**************************************************************************** |
// Measure the clock in period. Use the and the multiplication |
// factor to determine the period for the output clock |
//**************************************************************************** |
real last_edge_time; |
real this_edge_time; // $realtime when the input clock edges occur |
real ref_clk_period; // input clock period |
real dll_clk_out_period; // output clock period |
real clk_delay; |
|
|
initial last_edge_time = 0; |
initial dll_clk_out_period = 1; |
|
always @(posedge ref_clk) |
begin |
this_edge_time = $realtime; |
ref_clk_period = this_edge_time - last_edge_time; |
dll_clk_out_period = (ref_clk_period) / MULT; |
last_edge_time = this_edge_time; |
end |
|
|
|
|
|
//***************************************************************************** |
// Create a new clock |
//***************************************************************************** |
|
|
reg [SIZE-1:0] divider; |
|
|
initial |
begin |
dll_clk_out = 1'b0; |
forever |
begin |
clk_delay = (dll_clk_out_period/2); |
if (clk_delay < MIN_CLK_DELAY) |
clk_delay = MIN_CLK_DELAY; |
#(clk_delay) dll_clk_out = ~dll_clk_out; |
end |
end |
|
|
always@(posedge dll_clk_out or posedge reset ) |
if ( reset) divider <= DIV/2; |
else if ( divider == 'b1) divider <= DIV/2; |
else divider <= divider - 'b1; |
|
always@(posedge dll_clk_out or posedge reset ) |
if(reset) div_clk_out <= 1'b0; |
else if (divider == 'b1) div_clk_out <= !div_clk_out; |
else div_clk_out <= div_clk_out; |
|
|
|
|
|
|
/opencores.org/cde/ip/clock/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/clock/rtl/verilog/syn/dll
0,0 → 1,12
|
always@(*) |
begin |
dll_clk_out = ref_clk; |
end |
|
|
always@(posedge ref_clk or posedge reset) |
if(reset) div_clk_out <= 1'b0; |
else div_clk_out <= !div_clk_out; |
|
|
/opencores.org/cde/ip/clock/rtl/verilog/clock_sys
0,0 → 1,78
|
reg [6:0] counter; |
reg [3:0] reset_cnt; |
|
|
|
always@(posedge ckIn or posedge pwron_reset) |
if(pwron_reset) pwron_reset_n <= 1'b0; |
else pwron_reset_n <= 1'b1; |
|
|
generate |
|
if( CLOCK_SRC) |
|
begin |
assign ckIn = b_clk_pad_in; |
end |
else |
begin |
assign ckIn = a_clk_pad_in; |
end |
|
endgenerate |
|
|
generate |
|
if( RESET_SENSE) |
|
begin |
assign pwron_reset = !pwron_pad_in; |
end |
else |
begin |
assign pwron_reset = pwron_pad_in; |
end |
|
endgenerate |
|
|
|
|
|
|
|
|
|
always@(posedge ckIn or posedge pwron_reset) |
if( pwron_reset) reset_cnt <= 4'b1111; |
else |
if(|reset_cnt) reset_cnt <= reset_cnt-4'b0001; |
else reset_cnt <= 4'b0000; |
|
|
|
always@(posedge ckIn or posedge pwron_reset) |
if( pwron_reset) ref_reset <= 1'b1; |
else ref_reset <= |reset_cnt; |
|
|
always@(posedge dll_clk) |
if(dll_reset) |
begin |
one_usec <= 1'b0; |
counter <= FREQ*PLL_MULT/2; |
end |
else if(counter == 7'b0000001) |
begin |
one_usec <= !one_usec; |
counter <= FREQ*PLL_MULT/2; |
end |
else |
begin |
one_usec <= one_usec; |
counter <= counter -7'b0000001; |
end |
|
/opencores.org/cde/ip/clock/rtl/verilog/clock_sys.v
33,27 → 33,27
input wire a_clk_pad_in, |
input wire b_clk_pad_in, |
input wire pwron_pad_in, |
|
|
output wire div_clk_out, |
|
output reg one_usec, |
output wire reset |
output wire reset |
|
); |
|
wire ckIn; |
wire dll_clk; |
|
reg ref_reset; |
reg ref_reset; |
|
reg [6:0] counter; |
reg [3:0] reset_cnt; |
|
wire pwron_reset; |
wire pwron_reset_n; |
wire dll_reset; |
|
assign pwron_reset_n = !pwron_reset; |
|
|
|
generate |
|
if( CLOCK_SRC) |
144,7 → 144,7
) |
ref_rsync( |
.clk (div_clk_out), |
.reset_n (!pwron_reset), |
.reset_n (pwron_reset_n), |
.data_in (ref_reset), |
.data_out (reset) |
); |
157,7 → 157,7
) |
dll_rsync( |
.clk (dll_clk), |
.reset_n (!pwron_reset), |
.reset_n (pwron_reset_n), |
.data_in (ref_reset), |
.data_out (dll_reset) |
); |
/opencores.org/cde/ip/clock/rtl/verilog/clock_gater
0,0 → 1,19
|
|
wire latch_enable; |
reg latch_output; |
|
assign latch_enable = enable | atg_clk_mode; |
|
always @(latch_enable or clk_in) |
begin |
if (~clk_in) |
latch_output = latch_enable; |
else |
latch_output = latch_output; |
end |
|
assign clk_out = latch_output && clk_in; |
|
|
|
/opencores.org/cde/ip/clock/doc/Geda/html/cde_clock_sys.html
174,18 → 174,25
<td style="vertical-align: top;">Version<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">dll<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">cde<br></td> |
<td style="vertical-align: top;">clock<br></td> |
<td style="vertical-align: top;">dll<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ref_rsync<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">cde<br></td> |
<td style="vertical-align: top;">sync<br></td> |
<td style="vertical-align: top;">with_reset<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;"><br> </td> |
<td style="vertical-align: top;">dll_rsync<br> </td> |
<td style="vertical-align: top;">opencores.org<br> </td> |
<td style="vertical-align: top;">cde<br></td> |
<td style="vertical-align: top;">clock<br></td> |
<td style="vertical-align: top;">dll<br></td> |
<td style="vertical-align: top;">sync<br></td> |
<td style="vertical-align: top;">with_reset<br></td> |
</tr> |
</tbody> |
</table> |
/opencores.org/cde/ip/sync/componentCfg.xml
109,6 → 109,64
|
|
|
<socgen:configurations> |
|
|
|
<socgen:configuration> |
<socgen:name>default</socgen:name> |
<socgen:version>def</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>DEPTH</socgen:name><socgen:value>2</socgen:value></socgen:parameter> |
</socgen:parameters> |
</socgen:configuration> |
|
|
|
|
<socgen:configuration> |
<socgen:name>with_reset</socgen:name> |
<socgen:version>with_reset</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>DEPTH</socgen:name><socgen:value>2</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>RST_VAL</socgen:name><socgen:value>1'b0</socgen:value></socgen:parameter> |
|
</socgen:parameters> |
</socgen:configuration> |
|
|
|
<socgen:configuration> |
<socgen:name>with_hysteresis</socgen:name> |
<socgen:version>with_hysteresis</socgen:version> |
<socgen:parameters> |
<socgen:parameter><socgen:name>WIDTH</socgen:name><socgen:value>1</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>DEBOUNCE_SIZE</socgen:name><socgen:value>4</socgen:value></socgen:parameter> |
<socgen:parameter><socgen:name>DEBOUNCE_DELAY</socgen:name><socgen:value>4'b1111</socgen:value></socgen:parameter> |
|
|
</socgen:parameters> |
</socgen:configuration> |
|
|
|
</socgen:configurations> |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</socgen:componentConfiguration> |
|
/opencores.org/cde/ip/sync/rtl/xml/cde_sync_with_hysteresis.xml
17,12 → 17,62
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sync_with_hysteresis</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
<spirit:model> |
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
41,7 → 91,6
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
114,13 → 163,43
|
<spirit:fileSets> |
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sync_with_hysteresis</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sync_with_hysteresis</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
130,9 → 209,23
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sync_with_hysteresis</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
139,12 → 232,14
</spirit:fileSet> |
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/sync/rtl/xml/cde_sync_with_reset.xml
14,11 → 14,90
<spirit:name>sync</spirit:name> |
<spirit:version>with_reset</spirit:version> <spirit:configuration>default</spirit:configuration> |
|
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sync_with_reset</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
<spirit:model> |
|
<spirit:views> |
|
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
78,13 → 157,45
|
<spirit:fileSets> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sync_with_reset</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sync_with_reset</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
96,8 → 207,22
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sync_with_reset</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
112,7 → 237,7
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
/opencores.org/cde/ip/sync/rtl/xml/cde_sync_def.xml
18,15 → 18,87
|
|
|
<spirit:componentGenerators> |
|
|
|
|
<spirit:componentGenerator> |
<spirit:name>gen_verilog</spirit:name> |
<spirit:phase>104.0</spirit:phase> |
<spirit:apiType>none</spirit:apiType> |
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions> |
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>destination</spirit:name> |
<spirit:value>sync_def</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:componentGenerator> |
|
|
|
|
</spirit:componentGenerators> |
|
|
|
|
|
|
|
<spirit:model> |
|
|
<spirit:views> |
|
<spirit:view> |
<spirit:name>verilog</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="verilog"/> |
</spirit:vendorExtensions> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-common</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
|
|
|
|
<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
86,13 → 158,53
|
<spirit:fileSets> |
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-common</spirit:name> |
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/sync_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType> |
</spirit:file> |
|
|
|
|
|
</spirit:fileSet> |
|
|
|
|
|
|
<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sync_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/sim/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
102,9 → 214,25
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/copyright</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType> |
</spirit:file> |
|
|
<spirit:file> |
<spirit:logicalName></spirit:logicalName> |
<spirit:name>../verilog/common/sync_def</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType> |
</spirit:file> |
|
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
118,7 → 246,7
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName> |
<spirit:name>../verilog/</spirit:name> |
<spirit:name>../views/syn/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
/opencores.org/cde/ip/sync/rtl/verilog/sync_def.v
File deleted
/opencores.org/cde/ip/sync/rtl/verilog/copyright
0,0 → 1,20
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
/opencores.org/cde/ip/sync/rtl/verilog/sync_with_reset
0,0 → 1,24
reg [WIDTH - 1:0] sync_data [DEPTH:0]; |
|
|
always @(*) |
begin |
sync_data[0] = data_in; |
end |
|
|
|
integer i; |
always @(posedge clk or negedge reset_n) |
if (~reset_n) |
begin |
for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= RST_VAL; |
end |
|
else |
begin |
for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= sync_data[i-1]; |
end |
|
assign data_out = sync_data[DEPTH]; |
|
/opencores.org/cde/ip/sync/rtl/verilog/sync_with_hysteresis
0,0 → 1,61
reg [WIDTH - 1:0] hysteresis_data; |
reg [WIDTH - 1:0] clean_data; |
reg [DEBOUNCE_SIZE-1:0] debounce_counter; |
|
always@(posedge clk ) |
if(reset) |
begin |
data_out <= data_in; |
data_rise <= {WIDTH{1'b0}}; |
data_fall <= {WIDTH{1'b0}}; |
end |
else |
begin |
data_out <= clean_data; |
data_rise <= clean_data &( data_out ^ clean_data); |
data_fall <= data_out &( data_out ^ clean_data); |
end |
|
|
|
|
|
|
|
|
always@(posedge clk ) |
if(reset) |
begin |
clean_data <= data_in; |
hysteresis_data <= data_in; |
debounce_counter <= {DEBOUNCE_SIZE{1'b0}}; |
end |
else |
begin |
// if the current input data differs from hysteresis |
// then reset counter and update hysteresie |
|
if(data_in != hysteresis_data ) |
begin |
clean_data <= clean_data; |
hysteresis_data <= data_in; |
debounce_counter <= {DEBOUNCE_SIZE{1'b0}}; |
end |
// if counter reaches DEBOUNCE_DELAY then the signal is clean |
else |
if(debounce_counter == DEBOUNCE_DELAY) |
begin |
clean_data <= hysteresis_data; |
hysteresis_data <= hysteresis_data; |
debounce_counter <= debounce_counter; |
end |
// data_in did not change but counter did not reach limit. Increment counter |
else |
begin |
clean_data <= clean_data; |
hysteresis_data <= hysteresis_data; |
debounce_counter <= debounce_counter+1; |
end |
end |
|
|
/opencores.org/cde/ip/sync/rtl/verilog/sync_def
0,0 → 1,22
|
|
reg [WIDTH - 1:0] sync_data [DEPTH:0]; |
|
|
always @(*) |
begin |
sync_data[0] = data_in; |
end |
|
|
|
integer i; |
|
always @(posedge clk) |
begin |
for (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= sync_data[i-1]; |
end |
|
|
assign data_out = sync_data[DEPTH]; |
|