OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

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Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/doc/src/drawing/sch
    from Rev 99 to Rev 120
    ↔ Reverse comparison
  •

Rev 99 → Rev 120

/Busdef_guide_1.sch
0,0 → 1,48
v 20110115 2
C 4500 6100 1 0 0 frame_800x600.sym
T 5600 9700 9 10 1 0 0 0 1
.FOO_1_PHY(FOO_1_LOG)
B 4500 6100 3400 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 4500 6100 6100 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 4500 6100 8600 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 4600 10600 9 10 1 0 0 0 2
CMP_2
U1
T 4600 12000 9 10 1 0 0 0 1
CMP_1
T 4600 9700 9 10 1 0 0 0 2
CMP_3
U2
T 4800 7500 9 10 1 0 0 0 6
busInterface
name FOO_1
abstractor VLNV
Port
logical LOG
physical FOO_1_PHY
L 6700 9900 6700 10600 3 0 0 0 -1 -1
L 6700 10600 6600 10400 3 0 0 0 -1 -1
L 6700 10600 6800 10400 3 0 0 0 -1 -1
T 5600 10700 9 10 1 0 0 0 1
.FOO_1_LOG(FOO_1_LOG)
T 5600 12000 9 10 1 0 0 0 1
.FOO_1_LOG()
L 6700 10900 6700 11900 3 0 0 0 -1 -1
L 6700 11900 6600 11700 3 0 0 0 -1 -1
L 6700 11900 6800 11700 3 0 0 0 -1 -1
T 8300 7600 9 10 1 0 0 0 4
hierConnection
name FOO_1
compinstance U2
busRef FOO_1
T 11000 7600 9 10 1 0 0 0 4
hierConnection
name FOO_1
compinstance U1
busRef FOO_1
T 4700 6200 9 10 1 0 0 0 1
LEAF CELL
T 8200 6200 9 10 1 0 0 0 1
HIER LEVEL
T 10900 6200 9 10 1 0 0 0 1
HIER LEVEL
/Busdef_guide_2.sch
0,0 → 1,48
v 20110115 2
C 4500 6100 1 0 0 frame_800x600.sym
T 5600 9700 9 10 1 0 0 0 1
.FOO_1_PHY(U2_FOO_1_LOG)
B 4500 6100 3400 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 4500 6100 6100 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 4500 6100 8600 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 4600 10700 9 10 1 0 0 0 2
CMP_2
U1
T 4600 12000 9 10 1 0 0 0 1
CMP_1
T 4600 9700 9 10 1 0 0 0 2
CMP_3
U2
T 4800 7500 9 10 1 0 0 0 6
busInterface
name FOO_1
abstractor VLNV
Port
logical LOG
physical FOO_1_PHY
L 6700 9900 6700 10600 3 0 0 0 -1 -1
L 6700 10600 6600 10400 3 0 0 0 -1 -1
L 6700 10600 6800 10400 3 0 0 0 -1 -1
T 5600 10700 9 10 1 0 0 0 1
.U2_FOO_1_LOG(U1_U2_FOO_1_LOG)
T 5600 12000 9 10 1 0 0 0 1
.U1_U2_FOO_1_LOG()
L 6700 10900 6700 11900 3 0 0 0 -1 -1
L 6700 11900 6600 11700 3 0 0 0 -1 -1
L 6700 11900 6800 11700 3 0 0 0 -1 -1
T 8300 7600 9 10 1 0 0 0 4
hierConnection
name U2_FOO_1
compinstance U2
busRef FOO_1
T 10700 7600 9 10 1 0 0 0 4
hierConnection
name U1_U2_FOO_1
compinstance U1
busRef U2_FOO_1
T 4700 6200 9 10 1 0 0 0 1
LEAF CELL
T 8200 6200 9 10 1 0 0 0 1
HIER LEVEL
T 10900 6200 9 10 1 0 0 0 1
HIER LEVEL
/Busdef_guide_3.sch
0,0 → 1,68
v 20110115 2
C 4500 6100 1 0 0 frame_800x600.sym
T 5600 9700 9 10 1 0 0 0 1
.FOO_1_PHY(FOO_1_PHY)
B 4500 6100 3400 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 4500 6100 6100 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 4500 6100 8600 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 4600 10600 9 10 1 0 0 0 2
CMP_2
U1
T 4600 12000 9 10 1 0 0 0 1
CMP_1
T 4600 9700 9 10 1 0 0 0 2
CMP_3
U2
T 4800 8300 9 10 1 0 0 0 6
busInterface
name FOO_1
abstractor VLNV
Port
logical LOG
physical FOO_1_PHY
L 6700 9900 6700 10600 3 0 0 0 -1 -1
L 6700 10600 6600 10400 3 0 0 0 -1 -1
L 6700 10600 6800 10400 3 0 0 0 -1 -1
L 6700 10900 6700 11900 3 0 0 0 -1 -1
L 6700 11900 6600 11700 3 0 0 0 -1 -1
L 6700 11900 6800 11700 3 0 0 0 -1 -1
T 8300 7300 9 10 1 0 0 0 8
interconnection
name FOO_1
compinstance U2
busRef FOO_1
portmap
logical LOG
physical FOO_1_PHY
 
T 4700 6200 9 10 1 0 0 0 1
LEAF CELL
T 8200 6200 9 10 1 0 0 0 1
HIER LEVEL
T 10900 6200 9 10 1 0 0 0 1
HIER LEVEL
T 8300 9300 9 10 1 0 0 0 5
busInterface
name FOO_1
abstractor VLNV
Port logical LOG
physical FOO_1_PHY
T 10800 9400 9 10 1 0 0 0 5
busInterface
name FOO_1
abstractor VLNV
Port logical LOG
physical FOO_1_PHY
T 5700 10700 9 10 1 0 0 0 1
.FOO_1_PHY(FOO_1_PHY)
T 5700 12000 9 10 1 0 0 0 1
.FOO_1_PHY()
T 10800 7300 9 10 1 0 0 0 8
interconnection
name FOO_1
compinstance U1
busRef FOO_1
portmap
logical LOG
physical FOO_1_PHY
 
/um-100_cde_sram_be_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 49300 44400 1 0 0 cde_sram_be.sym
{
T 49700 46250 5 10 1 1 0 0 1
device=cde_sram_be
T 49700 46450 5 10 1 1 0 0 1
refdes=U?
}
/um-100_cde_sram_def_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 49200 44500 1 0 0 cde_sram_def.sym
{
T 49600 46350 5 10 1 1 0 0 1
device=cde_sram_def
T 49600 46550 5 10 1 1 0 0 1
refdes=U?
}
/um-100_cde_sram_dp_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 49300 44300 1 0 0 cde_sram_dp.sym
{
T 49700 46150 5 10 1 1 0 0 1
device=cde_sram_dp
T 49700 46350 5 10 1 1 0 0 1
refdes=U?
}
/um-150_cde_reset_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 48400 44900 1 0 0 cde_reset_def.sym
{
T 48800 46150 5 10 1 1 0 0 1
device=cde_reset_def
T 48800 46350 5 10 1 1 0 0 1
refdes=U?
}
/cde_pad_out_dig.sch
0,0 → 1,21
v 20110115 2
C 4100 2600 1 0 0 in_port.sym
{
T 4100 2600 5 10 1 1 0 6 1
refdes=pad_out
}
C 7900 2600 1 0 1 io_port_v.sym
{
T 7900 2600 5 10 1 1 0 0 1
refdes=PAD
}
N 5300 2700 5000 2700 4
U 6900 2700 6400 2700 10 0
B 2800 600 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 5300 2100 1 0 0 cde_pad_out_dig.sym
{
T 6202 2218 5 10 1 1 0 0 1
device=cde_pad_out_dig
T 6400 3000 5 10 1 1 0 6 1
refdes=P?
}
/um-150_cde_jtag_rpc_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 48200 44600 1 0 0 cde_jtag_rpc_reg.sym
{
T 48600 46650 5 10 1 1 0 0 1
device=cde_jtag_rpc_reg
T 48600 46850 5 10 1 1 0 0 1
refdes=U?
}
/fund_reset_fig1.sch
0,0 → 1,275
v 20110115 2
C 56000 51800 1 0 0 reg_rst.sym
{
T 57800 53600 5 10 0 0 0 0 1
device=REGISTER_RST
T 57300 53800 5 10 1 1 0 6 1
refdes=U?
}
B 56000 48800 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 62400 49000 9 10 1 0 0 0 2
ACTIVE LOW
RESET
B 53200 41500 21200 13100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54600 45600 1 0 0 high-1.sym
{
T 54900 45900 5 10 0 1 0 0 1
device=HIGH
T 54800 45800 5 10 1 1 0 0 1
refdes=H?
}
C 56100 43400 1 0 0 low-1.sym
{
T 56500 43400 5 10 0 1 0 0 1
device=LOW
T 56400 43600 5 10 1 1 0 0 1
refdes=G?
}
C 53800 49900 1 0 0 pullup-1.sym
{
T 54000 50000 5 10 1 1 0 0 1
refdes=H?
}
C 53800 50700 1 0 0 pulldown-1.sym
{
T 54000 50800 5 10 1 1 0 0 1
refdes=G?
}
C 54400 51500 1 0 0 ipad-1.sym
{
T 54484 51721 5 10 0 1 0 0 1
device=IPAD
T 54400 51800 5 10 1 1 0 0 1
refdes=TRST_n
}
N 53900 51000 53900 51600 4
N 53900 51600 54400 51600 4
N 55300 51600 56800 51600 4
N 56800 51600 56800 51800 4
C 54500 49500 1 0 0 ipad-1.sym
{
T 54584 49721 5 10 0 1 0 0 1
device=IPAD
T 54500 49800 5 10 1 1 0 0 1
refdes=CLK_RST_n
}
N 55400 49600 56000 49600 4
N 53900 49200 53900 49900 4
N 53900 49600 54500 49600 4
T 56100 49300 9 10 1 0 0 0 3
Metastable
filter
inv
C 56500 43700 1 90 0 asic-cap-2.sym
{
T 56100 44700 5 8 0 0 90 0 1
device=CAPACITOR
T 56100 43800 5 10 1 1 90 0 1
refdes=C?
T 56100 44300 5 10 1 1 90 0 1
value=1n
}
C 54100 48300 1 90 0 asic-cap-2.sym
{
T 53700 49300 5 8 0 0 90 0 1
device=CAPACITOR
T 53700 48400 5 10 1 1 90 0 1
refdes=C?
T 53700 48900 5 10 1 1 90 0 1
value=1n
}
C 53700 48000 1 0 0 low-1.sym
{
T 54100 48000 5 10 0 1 0 0 1
device=LOW
T 54000 48200 5 10 1 1 0 0 1
refdes=G?
}
C 56200 45300 1 0 0 pullup-1.sym
{
T 56400 45400 5 10 1 1 0 0 1
refdes=H?
}
N 56300 44600 56300 45300 4
N 56300 45000 57200 45000 4
C 57200 44900 1 0 0 ipad-1.sym
{
T 57284 45121 5 10 0 1 0 0 1
device=IPAD
T 57200 45200 5 10 1 1 0 0 1
refdes=PWR_ON
}
C 58200 49600 1 0 0 or2-1.sym
{
T 58600 49500 5 10 1 1 0 2 1
refdes=U?
T 58600 49700 5 8 0 0 0 0 1
device=or
}
N 58200 49700 57300 49700 4
N 57600 53400 58200 53400 4
N 58200 53400 58200 50100 4
C 54500 43700 1 0 0 low-1.sym
{
T 54900 43700 5 10 0 1 0 0 1
device=LOW
T 54800 43900 5 10 1 1 0 0 1
refdes=G?
}
B 54100 44000 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 54400 44800 9 10 1 0 0 0 2
Power
Monitor
N 56300 45000 55400 45000 4
B 58400 44200 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58500 44700 9 10 1 0 0 0 3
Metastable
filter
inv
N 60300 49900 59500 49900 4
N 60300 49500 59900 49500 4
N 59900 49500 59900 45000 4
N 59900 45000 59700 45000 4
N 59900 49900 59900 53600 4
N 59900 53600 62200 53600 4
T 60800 53700 9 20 1 0 0 0 1
clkdiv_reset
C 60300 49400 1 0 0 nor2-1.sym
{
T 60700 49300 5 10 1 1 0 2 1
refdes=U?
T 60700 49500 5 8 0 0 0 0 1
device=nor
}
C 62800 49800 1 0 0 reg_rst.sym
{
T 64600 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 64100 51800 5 10 1 1 0 6 1
refdes=U?
}
C 64800 49800 1 0 0 reg_rst.sym
{
T 66600 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 66100 51800 5 10 1 1 0 6 1
refdes=U?
}
C 66700 49800 1 0 0 reg_rst.sym
{
T 68500 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 68000 51800 5 10 1 1 0 6 1
refdes=U?
}
C 68500 49800 1 0 0 reg_rst.sym
{
T 70300 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 69800 51800 5 10 1 1 0 6 1
refdes=U?
}
C 70400 48900 1 0 0 and2-1.sym
{
T 70800 48800 5 10 1 1 0 2 1
refdes=U?
T 70800 49000 5 8 0 0 0 0 1
device=and
}
C 71700 47600 1 0 0 reg_rst.sym
{
T 73500 49400 5 10 0 0 0 0 1
device=REGISTER_RST
T 73000 49600 5 10 1 1 0 6 1
refdes=U?
}
C 70400 46700 1 0 0 and2-1.sym
{
T 70800 46600 5 10 1 1 0 2 1
refdes=U?
T 70800 46800 5 8 0 0 0 0 1
device=and
}
C 71700 45400 1 0 0 reg_rst.sym
{
T 73500 47200 5 10 0 0 0 0 1
device=REGISTER_RST
T 73000 47400 5 10 1 1 0 6 1
refdes=U?
}
V 62000 49700 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 61800 49600 9 10 1 0 0 0 1
DFT
N 69300 49800 69300 49700 4
N 69300 49700 62400 49700 4
N 63600 49800 63600 49700 4
N 65600 49800 65600 49700 4
N 64800 51400 64400 51400 4
N 66700 51400 66400 51400 4
N 68500 51400 68300 51400 4
N 70100 47200 70100 51400 4
N 70100 49400 70400 49400 4
N 70400 47200 70100 47200 4
N 70400 49000 69200 49000 4
N 70400 46800 69200 46800 4
N 72500 47600 63600 47600 4
N 63600 45400 63600 49700 4
N 72500 45400 63600 45400 4
C 62700 51400 1 0 0 high-1.sym
{
T 63000 51700 5 10 0 1 0 0 1
device=HIGH
T 62700 51900 5 10 1 1 0 0 1
refdes=H?
}
C 67600 47400 1 0 0 reg.sym
{
T 69400 49200 5 10 0 0 0 0 1
device=REGISTER
T 68900 49400 5 10 1 1 0 6 1
refdes=U?
}
C 67600 45200 1 0 0 reg.sym
{
T 69400 47000 5 10 0 0 0 0 1
device=REGISTER
T 68900 47200 5 10 1 1 0 6 1
refdes=U?
}
N 67500 49800 67500 49700 4
T 72800 44900 9 10 1 0 0 0 3
ACTIVE LOW
RESETS TO
COMPONENTS
N 73300 49200 74100 49200 4
N 73300 47000 74100 47000 4
T 62900 52300 9 25 1 0 0 0 1
Synchronous Reset Distribution Tree
T 67400 44300 9 25 1 0 0 0 2
Soft Reset
Sources
T 53400 52600 9 25 1 0 0 0 2
JTAG RPC
CONTROL
T 54900 47800 9 25 1 0 0 0 2
SIM/TEST
RESET
T 64500 42100 9 40 1 0 0 0 1
Modern ASIC Reset System
C 58100 42900 1 0 1 out_port.sym
{
T 57798 43118 5 10 0 1 0 6 1
device=OPAD
T 57200 43200 5 10 1 1 0 0 1
refdes=PWR_ON
}
N 57000 45000 57000 43000 4
N 57000 43000 57200 43000 4
B 58400 42400 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
N 58100 43000 58400 43000 4
T 58600 43100 9 10 1 0 0 0 1
WatchDog
N 58100 45000 58400 45000 4
T 53600 42000 9 25 1 0 0 0 2
PCA PWR
RESET
/um-100_cde_jtag_def_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 48500 43800 1 0 0 cde_jtag_def.sym
{
T 48900 46650 5 10 1 1 0 0 1
device=cde_jtag_def
T 48900 46850 5 10 1 1 0 0 1
refdes=U?
}
/fund_reset_fig2.sch
0,0 → 1,33
v 20110115 2
B 53200 41500 11500 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54300 42300 1 0 0 reg_rst.sym
{
T 56100 44100 5 10 0 0 0 0 1
device=REGISTER_RST
T 55600 44300 5 10 1 1 0 6 1
refdes=U?
}
V 57100 43900 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 56900 43800 9 10 1 0 0 0 1
DFT
T 54400 44700 9 10 1 0 0 0 3
ACTIVE LOW
RESET TO
COMPONENT
N 55900 43900 56700 43900 4
T 53900 45400 9 25 1 0 0 0 1
Soft Reset
C 57800 46000 1 0 0 reg_rst.sym
{
T 59600 47800 5 10 0 0 0 0 1
device=REGISTER_RST
T 59100 48000 5 10 1 1 0 6 1
refdes=U?
}
N 55100 42300 55100 41900 4
N 55100 41900 53700 41900 4
N 58600 46000 58600 43900 4
N 58600 43900 57500 43900 4
T 61100 43200 9 25 1 0 0 0 2
Reset Style #1
Asynchronous
/fund_reset_fig3.sch
0,0 → 1,40
v 20110115 2
B 53200 41500 11500 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54300 42300 1 0 0 reg_rst.sym
{
T 56100 44100 5 10 0 0 0 0 1
device=REGISTER_RST
T 55600 44300 5 10 1 1 0 6 1
refdes=U?
}
T 54400 44700 9 10 1 0 0 0 3
ACTIVE LOW
RESET TO
COMPONENT
N 55900 43900 57700 43900 4
T 53900 45400 9 25 1 0 0 0 1
Soft Reset
N 55100 42300 55100 41900 4
N 55100 41900 53700 41900 4
T 61100 43200 9 25 1 0 0 0 2
Reset Style #2
Synchronous
C 59800 45100 1 0 0 reg.sym
{
T 61600 46900 5 10 0 0 0 0 1
device=REGISTER
T 61100 47100 5 10 1 1 0 6 1
refdes=U?
}
C 58300 46400 1 0 0 and2-1.sym
{
T 58700 46300 5 10 1 1 0 2 1
refdes=U?
T 58700 46500 5 8 0 0 0 0 1
device=and
}
N 58300 46500 57700 46500 4
N 57700 46500 57700 43900 4
N 59600 46700 59800 46700 4
N 61400 46700 62300 46700 4
N 58300 46900 56300 46900 4
/fund_reset_fig4.sch
0,0 → 1,38
v 20110115 2
B 53200 41500 11500 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54300 42300 1 0 0 reg_rst.sym
{
T 56100 44100 5 10 0 0 0 0 1
device=REGISTER_RST
T 55600 44300 5 10 1 1 0 6 1
refdes=U?
}
T 54400 44700 9 10 1 0 0 0 3
ACTIVE LOW
RESET TO
COMPONENT
N 55900 43900 56300 43900 4
T 53900 45400 9 25 1 0 0 0 1
Soft Reset
C 57800 46000 1 0 0 reg_rst.sym
{
T 59600 47800 5 10 0 0 0 0 1
device=REGISTER_RST
T 59100 48000 5 10 1 1 0 6 1
refdes=U?
}
N 55100 42300 55100 41900 4
N 53700 41900 58600 41900 4
N 58600 46000 58600 41900 4
T 61100 43200 9 25 1 0 0 0 2
Reset Style #3
Both
C 56300 47300 1 0 0 and2-1.sym
{
T 56700 47200 5 10 1 1 0 2 1
refdes=U?
T 56700 47400 5 8 0 0 0 0 1
device=and
}
N 57800 47600 57600 47600 4
N 56300 47400 56300 43900 4
/fund_reset_fig5.sch
0,0 → 1,47
v 20110115 2
B 53200 41500 11500 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54300 42300 1 0 0 reg_rst.sym
{
T 56100 44100 5 10 0 0 0 0 1
device=REGISTER_RST
T 55600 44300 5 10 1 1 0 6 1
refdes=U?
}
T 54400 44700 9 10 1 0 0 0 3
ACTIVE LOW
RESET TO
COMPONENT
N 55900 43900 61400 43900 4
T 53900 45400 9 25 1 0 0 0 1
Soft Reset
N 55100 42300 55100 41900 4
N 55100 41900 53700 41900 4
T 60900 42100 9 25 1 0 0 0 2
Reset Style #4
Sync with Backup
C 59200 46200 1 0 0 reg.sym
{
T 61000 48000 5 10 0 0 0 0 1
device=REGISTER
T 60500 48200 5 10 1 1 0 6 1
refdes=U?
}
C 57200 47500 1 0 0 and2-1.sym
{
T 57600 47400 5 10 1 1 0 2 1
refdes=U?
T 57600 47600 5 8 0 0 0 0 1
device=and
}
C 61400 47300 1 0 0 and2-1.sym
{
T 61800 47200 5 10 1 1 0 2 1
refdes=U?
T 61800 47400 5 8 0 0 0 0 1
device=and
}
N 60800 47800 61400 47800 4
N 59200 47800 58500 47800 4
N 57200 47600 57100 47600 4
N 57100 43900 57100 47600 4
N 61400 47400 61400 43900 4
/fund_reset_fig6.sch
0,0 → 1,27
v 20110115 2
B 53200 41500 11500 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54300 42300 1 0 0 reg_rst.sym
{
T 56100 44100 5 10 0 0 0 0 1
device=REGISTER_RST
T 55600 44300 5 10 1 1 0 6 1
refdes=U?
}
T 54400 44700 9 10 1 0 0 0 3
ACTIVE LOW
RESET TO
COMPONENT
T 53900 45400 9 25 1 0 0 0 1
Soft Reset
N 55100 42300 55100 41900 4
N 55100 41900 53700 41900 4
T 61100 43200 9 25 1 0 0 0 2
Reset Style #5
None
C 58300 45600 1 0 0 reg.sym
{
T 60100 47400 5 10 0 0 0 0 1
device=REGISTER
T 59600 47600 5 10 1 1 0 6 1
refdes=U?
}
/cde_pad_tri_dig.sch
0,0 → 1,27
v 20110115 2
C 4100 3000 1 0 0 in_port.sym
{
T 4100 3000 5 10 1 1 0 6 1
refdes=pad_oe
}
C 4100 2600 1 0 0 in_port.sym
{
T 4100 2600 5 10 1 1 0 6 1
refdes=pad_out
}
C 7900 2600 1 0 1 io_port_v.sym
{
T 7900 2600 5 10 1 1 0 0 1
refdes=PAD
}
N 5300 3100 5000 3100 4
N 5300 2700 5000 2700 4
U 6900 2700 6400 2700 10 0
B 2800 600 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 5200 2100 1 0 0 cde_pad_tri_dig.sym
{
T 5302 2318 5 10 1 1 0 0 1
device=cde_pad_tri_dig
T 6400 3000 5 10 1 1 0 6 1
refdes=P?
}
/um-150_cde_sync_sym.sch
0,0 → 1,23
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 48600 46200 1 0 0 cde_sync_def.sym
{
T 49000 47050 5 10 1 1 0 0 1
device=cde_sync_def
T 49000 47250 5 10 1 1 0 0 1
refdes=U?
}
C 48600 44700 1 0 0 cde_sync_with_reset.sym
{
T 49000 45750 5 10 1 1 0 0 1
device=cde_sync_with_reset
T 49000 45950 5 10 1 1 0 0 1
refdes=U?
}
C 48600 43100 1 0 0 cde_sync_with_hysteresis.sym
{
T 49000 44150 5 10 1 1 0 0 1
device=cde_sync_with_hysteresis
T 49000 44350 5 10 1 1 0 0 1
refdes=U?
}
/cde_pad_od_dig.sch
0,0 → 1,27
v 20110115 2
C 4300 2900 1 0 0 in_port.sym
{
T 4300 2900 5 10 1 1 0 6 1
refdes=pad_oe
}
C 8100 2500 1 0 1 io_port_v.sym
{
T 8100 2500 5 10 1 1 0 0 1
refdes=PAD
}
C 5200 2100 1 0 1 out_port.sym
{
T 4200 2100 5 10 1 1 0 6 1
refdes=pad_in
}
N 5500 3000 5200 3000 4
N 5500 2200 5200 2200 4
U 7100 2600 6600 2600 10 0
B 3000 500 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 5400 2000 1 0 0 cde_pad_od_dig.sym
{
T 6402 2118 5 10 1 1 0 0 1
device=cde_pad_od_dig
T 6600 2900 5 10 1 1 0 6 1
refdes=P?
}
/cde_pad_in_dig.sch
0,0 → 1,21
v 20110115 2
C 7000 2500 1 0 1 io_port_v.sym
{
T 7000 2500 5 10 1 1 0 0 1
refdes=PAD
}
C 4100 2500 1 0 1 out_port.sym
{
T 3100 2500 5 10 1 1 0 6 1
refdes=pad_in
}
N 4400 2600 4100 2600 4
U 6000 2600 5500 2600 10 0
B 1900 500 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 4300 2100 1 0 0 cde_pad_in_dig.sym
{
T 5302 2118 5 10 1 1 0 0 1
device=cde_pad_in_dig
T 5500 2900 5 10 1 1 0 6 1
refdes=P?
}
/cde_pad_se_dig.sch
0,0 → 1,33
v 20110115 2
C 4100 3000 1 0 0 in_port.sym
{
T 4100 3000 5 10 1 1 0 6 1
refdes=pad_oe
}
C 4100 2600 1 0 0 in_port.sym
{
T 4100 2600 5 10 1 1 0 6 1
refdes=pad_out
}
C 7900 2600 1 0 1 io_port_v.sym
{
T 7900 2600 5 10 1 1 0 0 1
refdes=PAD
}
C 5000 2200 1 0 1 out_port.sym
{
T 4000 2200 5 10 1 1 0 6 1
refdes=pad_in
}
C 5300 2100 1 0 0 cde_pad_se_dig.sym
{
T 6202 2218 5 10 1 1 0 0 1
device=cde_pad_se_dig
T 6400 3000 5 10 1 1 0 6 1
refdes=P?
}
N 5300 3100 5000 3100 4
N 5300 2700 5000 2700 4
N 5300 2300 5000 2300 4
U 6900 2700 6400 2700 10 0
B 2800 600 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
/um-100_cde_clock_sys_sym.sch
0,0 → 1,9
v 20110115 2
B 48000 43000 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 49300 44500 1 0 0 cde_clock_sys.sym
{
T 49700 46150 5 10 1 1 0 0 1
device=cde_clock_sys
T 49700 46350 5 10 1 1 0 0 1
refdes=U?
}

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