URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/doc/src/drawing/sch
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/doc_fig1.sch
0,0 → 1,55
v 20100214 2 |
C 57800 32800 1 0 0 frame_800x600.sym |
T 59100 38300 9 10 1 0 0 0 1 |
DataBase RTL Code |
T 64500 38100 9 10 1 0 0 0 2 |
sym/component.sym |
sch/component.sch |
T 64900 36400 9 10 1 0 0 0 1 |
GSCHEM |
T 61600 36500 9 10 1 0 0 0 2 |
png/component.png |
png/figures.png |
T 61600 35200 9 10 1 0 0 0 1 |
html/component.html |
T 59100 36400 9 10 1 0 0 0 1 |
SEAMONKEY |
T 59100 33400 9 10 1 0 0 0 3 |
OPENOFFICE |
WORD |
PROCESSOR |
T 61600 33700 9 10 1 0 0 0 1 |
pdf/component.pdf |
T 61800 38100 9 10 1 0 0 0 2 |
VER2GEDASYM |
VER2GEDASCH |
V 59700 36500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
V 59600 33700 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
V 65300 36500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
V 62500 38300 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 58900 38100 2100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 64300 37900 2000 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 61500 36100 2000 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 61500 35000 2000 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 61500 33500 2000 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
L 61000 38300 61700 38300 3 0 0 0 -1 -1 |
L 63300 38300 64300 38300 3 0 0 0 -1 -1 |
L 65300 37000 65300 37900 3 0 0 0 -1 -1 |
L 64800 36500 63500 36500 3 0 0 0 -1 -1 |
L 62500 36100 62500 35500 3 0 0 0 -1 -1 |
L 60400 33700 61500 33700 3 0 0 0 -1 -1 |
L 60300 34100 61500 35000 3 0 0 0 -1 -1 |
L 60300 36100 61500 35500 3 0 0 0 -1 -1 |
L 61700 38300 61600 38400 3 0 0 0 -1 -1 |
L 61700 38300 61600 38200 3 0 0 0 -1 -1 |
L 64300 38300 64200 38400 3 0 0 0 -1 -1 |
L 64300 38300 64200 38200 3 0 0 0 -1 -1 |
L 63500 36500 63600 36600 3 0 0 0 -1 -1 |
L 63500 36500 63600 36400 3 0 0 0 -1 -1 |
L 62500 35500 62400 35600 3 0 0 0 -1 -1 |
L 62500 35500 62600 35600 3 0 0 0 -1 -1 |
L 61500 33700 61400 33800 3 0 0 0 -1 -1 |
L 61500 33700 61400 33600 3 0 0 0 -1 -1 |
V 60900 35800 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
V 60700 34400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
V 65300 37400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
/data_fig1.sch
0,0 → 1,72
v 20100214 2 |
C 42600 22000 1 0 0 frame_800x600.sym |
B 49500 27200 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 22200 6000 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 49500 27300 9 10 1 0 0 0 1 |
Serial Uart |
T 49500 26700 9 10 1 0 0 0 1 |
VGA Display |
T 49600 26200 9 10 1 0 0 0 1 |
PS2 Mouse |
T 49600 25600 9 10 1 0 0 0 1 |
Switches |
T 49700 25100 9 10 1 0 0 0 1 |
Leds |
T 49500 24500 9 10 1 0 0 0 1 |
Push Buttons |
T 49500 23900 9 10 1 0 0 0 1 |
7 Seg display |
T 49500 23100 9 10 1 0 0 0 1 |
I/O connectors |
B 49500 25500 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 25000 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 26600 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 26100 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 24400 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 23800 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 23000 1200 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43000 28400 9 10 1 0 0 0 1 |
System |
T 43100 27600 9 10 1 0 0 0 1 |
PCA (Nexys2) |
T 43400 26900 9 10 1 0 0 0 1 |
Targeted Component (Xilinx Spartan 3E-500 FG320) |
B 43200 22600 5400 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 43500 23100 4800 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43800 26200 9 10 1 0 0 0 1 |
Padring |
T 44100 25700 9 10 1 0 0 0 1 |
Core |
T 44300 25200 9 10 1 0 0 0 1 |
Component |
B 43800 23500 4200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44100 23800 3600 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 45500 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 46600 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44500 24800 9 10 1 0 0 0 1 |
comp |
T 45600 24800 9 10 1 0 0 0 1 |
comp |
T 46700 24800 9 10 1 0 0 0 1 |
comp |
B 44500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 45500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 46500 27400 600 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 47500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44600 27600 9 10 1 0 0 0 1 |
IC |
T 45600 27600 9 10 1 0 0 0 1 |
IC |
T 46600 27600 9 10 1 0 0 0 1 |
IC |
T 47600 27600 9 10 1 0 0 0 1 |
IC |
L 48900 27400 49500 27400 3 0 0 0 -1 -1 |
L 48900 26800 49500 26800 3 0 0 0 -1 -1 |
L 48900 26300 49500 26300 3 0 0 0 -1 -1 |
L 48900 25700 49500 25700 3 0 0 0 -1 -1 |
L 48900 25200 49500 25200 3 0 0 0 -1 -1 |
L 48900 24600 49500 24600 3 0 0 0 -1 -1 |
L 48900 24000 49500 24000 3 0 0 0 -1 -1 |
L 48900 23200 49500 23200 3 0 0 0 -1 -1 |