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URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/doc/src/drawing/sch
    from Rev 20 to Rev 27
    ↔ Reverse comparison
  •

Rev 20 → Rev 27

/ver_fig2.sch
0,0 → 1,68
v 20100214 2
C 50500 14600 1 0 0 frame_800x600.sym
B 53500 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 52300 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 50600 16900 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 53600 18800 9 10 1 0 0 0 1
DUT
T 52400 17300 9 10 1 0 0 0 3
BFM
MODEL
 
T 50600 17400 9 10 1 0 0 0 2
TEST_DEFINE
 
L 51900 17700 52300 17700 3 0 0 0 -1 -1
L 51900 17600 52300 17600 3 0 0 0 -1 -1
L 52300 17600 52200 17500 3 0 0 0 -1 -1
L 52300 17700 52200 17800 3 0 0 0 -1 -1
L 51900 17700 52000 17800 3 0 0 0 -1 -1
L 51900 17600 52000 17500 3 0 0 0 -1 -1
L 53100 17700 53400 17700 3 0 0 0 -1 -1
L 53100 17600 53400 17600 3 0 0 0 -1 -1
L 53100 17700 53200 17800 3 0 0 0 -1 -1
L 53100 17600 53200 17500 3 0 0 0 -1 -1
L 53400 17700 53300 17800 3 0 0 0 -1 -1
L 53400 17600 53300 17500 3 0 0 0 -1 -1
T 50700 18300 9 10 1 0 0 0 1
CMP_A
T 53600 18100 9 10 1 0 0 0 1
CMP_A
B 55700 16900 700 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 56800 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 58000 16900 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 57600 17700 58000 17700 3 0 0 0 -1 -1
L 57600 17600 58000 17600 3 0 0 0 -1 -1
L 58000 17600 57900 17500 3 0 0 0 -1 -1
L 58000 17700 57900 17800 3 0 0 0 -1 -1
L 57600 17700 57700 17800 3 0 0 0 -1 -1
L 57600 17600 57700 17500 3 0 0 0 -1 -1
L 56500 17700 56800 17700 3 0 0 0 -1 -1
L 56500 17600 56800 17600 3 0 0 0 -1 -1
L 56500 17700 56600 17800 3 0 0 0 -1 -1
L 56500 17600 56600 17500 3 0 0 0 -1 -1
L 56800 17700 56700 17800 3 0 0 0 -1 -1
L 56800 17600 56700 17500 3 0 0 0 -1 -1
T 56900 17300 9 10 1 0 0 0 3
BFM
MODEL
 
T 58000 17400 9 10 1 0 0 0 2
TEST_DEFINE
 
T 58600 18200 9 10 1 0 0 0 1
CMP_C
T 55700 18100 9 10 1 0 0 0 1
CMP_C
B 53400 16400 3100 2800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51100 19500 9 10 1 0 0 0 1
TEST_CASE
B 54600 16900 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 54700 18100 9 10 1 0 0 0 1
CMP_B
L 54300 18000 54600 18000 3 0 0 0 -1 -1
L 55400 18000 55700 18000 3 0 0 0 -1 -1
L 54300 17700 54600 17700 3 0 0 0 -1 -1
L 55400 17700 55700 17700 3 0 0 0 -1 -1
L 54300 17400 54600 17400 3 0 0 0 -1 -1
L 55400 17400 55700 17400 3 0 0 0 -1 -1
/ver_fig3.sch
0,0 → 1,110
v 20100214 2
C 57800 33600 1 0 0 frame_800x600.sym
B 64000 33700 2000 5500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 61000 36400 2000 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 61200 36500 700 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 62100 37700 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 62100 37700 9 10 1 0 0 0 1
REG
B 62100 37300 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 62100 37300 9 10 1 0 0 0 1
REG
B 62100 36900 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 62100 36900 9 10 1 0 0 0 1
REG
B 62100 36500 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 62100 36500 9 10 1 0 0 0 1
REG
T 61200 37900 9 10 1 0 0 0 1
TASKS
T 61100 38200 9 10 1 0 0 0 1
INTERFACE_MODEL
L 61900 38000 64000 38000 3 0 0 0 -1 -1
L 61900 37600 64000 37600 3 0 0 0 -1 -1
L 61900 37200 64000 37200 3 0 0 0 -1 -1
L 61900 36800 64000 36800 3 0 0 0 -1 -1
L 62500 36600 62700 36600 3 0 0 0 -1 -1
L 62700 36800 62700 36600 3 0 0 0 -1 -1
L 62500 37000 62700 37000 3 0 0 0 -1 -1
L 62700 37200 62700 37000 3 0 0 0 -1 -1
L 62500 37400 62700 37400 3 0 0 0 -1 -1
L 62700 37600 62700 37400 3 0 0 0 -1 -1
L 62500 37800 62700 37800 3 0 0 0 -1 -1
L 62700 38000 62700 37800 3 0 0 0 -1 -1
L 62100 37800 61900 37800 3 0 0 0 -1 -1
L 62100 37400 61900 37400 3 0 0 0 -1 -1
L 62100 37000 61900 37000 3 0 0 0 -1 -1
L 62100 36600 61900 36600 3 0 0 0 -1 -1
T 64100 39200 9 10 1 0 0 0 2
COMP
DUT
B 61000 33800 2000 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 61200 33900 700 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 62100 35100 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 62100 34700 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 62100 34300 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 62100 33900 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 61900 35400 64000 35400 3 0 0 0 -1 -1
L 61900 35000 64000 35000 3 0 0 0 -1 -1
L 61900 34600 64000 34600 3 0 0 0 -1 -1
L 61900 34200 64000 34200 3 0 0 0 -1 -1
L 62500 34000 62700 34000 3 0 0 0 -1 -1
L 62700 34200 62700 34000 3 0 0 0 -1 -1
L 62500 34400 62700 34400 3 0 0 0 -1 -1
L 62700 34600 62700 34400 3 0 0 0 -1 -1
L 62500 34800 62700 34800 3 0 0 0 -1 -1
L 62700 35000 62700 34800 3 0 0 0 -1 -1
L 62500 35200 62700 35200 3 0 0 0 -1 -1
L 62700 35400 62700 35200 3 0 0 0 -1 -1
L 62100 35200 61900 35200 3 0 0 0 -1 -1
L 62100 34800 61900 34800 3 0 0 0 -1 -1
L 62100 34400 61900 34400 3 0 0 0 -1 -1
L 62100 34000 61900 34000 3 0 0 0 -1 -1
T 62100 35100 9 10 1 0 0 0 1
REG
T 62100 34700 9 10 1 0 0 0 1
REG
T 62100 34300 9 10 1 0 0 0 1
REG
T 62100 33900 9 10 1 0 0 0 1
REG
T 61200 35300 9 10 1 0 0 0 1
TASKS
T 61100 35600 9 10 1 0 0 0 1
INTERFACE_MODEL
B 58800 33800 1800 6000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58700 39900 9 10 1 0 0 0 1
TEST_DEFINE
B 61000 38600 2000 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 61400 39300 9 10 1 0 0 0 1
CLOCK_GEN
L 63000 39500 63500 39500 3 0 0 0 -1 -1
L 63000 38900 63500 38900 3 0 0 0 -1 -1
T 63400 39600 9 10 1 0 0 0 1
CLK
T 63200 39000 9 10 1 0 0 0 1
RESET
T 58900 38700 9 10 1 0 0 0 5
INITIAL
BEGIN
CG.NEXT(20);
CG.RESET_OFF
FORK
T 59000 33900 9 10 1 0 0 0 3
JOIN
CG.EXIT
END
T 59000 36800 9 10 1 0 0 0 6
BEGIN
TASK CALL
TASK CALL
CG.NEXT(23)
TASK CALL
END
T 59000 34600 9 10 1 0 0 0 6
BEGIN
TASK CALL
TASK CALL
CG.NEXT(45)
TASK CALL
END
/reset_fig1.sch
0,0 → 1,75
v 20100214 2
C 58400 44700 1 0 0 frame_800x600.sym
C 64300 48500 1 0 0 reg.sym
{
T 66100 50300 5 10 0 0 0 0 1
device=REGISTER
T 65600 50500 5 10 1 1 0 6 1
refdes=U?
}
C 60400 45600 1 0 0 reg_rst.sym
{
T 62200 47400 5 10 0 0 0 0 1
device=REGISTER_RST
T 61700 47600 5 10 1 1 0 6 1
refdes=U?
}
C 63000 49800 1 0 0 and2-1.sym
{
T 63400 49700 5 10 1 1 0 2 1
refdes=U?
T 63400 49900 5 8 0 0 0 0 1
device=and
}
C 65900 49600 1 0 0 and2-1.sym
{
T 66300 49500 5 10 1 1 0 2 1
refdes=U?
T 66300 49700 5 8 0 0 0 0 1
device=and
}
C 60400 48500 1 0 0 reg.sym
{
T 62200 50300 5 10 0 0 0 0 1
device=REGISTER
T 61700 50500 5 10 1 1 0 6 1
refdes=U?
}
C 59100 49800 1 0 0 and2-1.sym
{
T 59500 49700 5 10 1 1 0 2 1
refdes=U?
T 59500 49900 5 8 0 0 0 0 1
device=and
}
C 64300 45600 1 0 0 reg_rst.sym
{
T 66100 47400 5 10 0 0 0 0 1
device=REGISTER_RST
T 65600 47600 5 10 1 1 0 6 1
refdes=U?
}
C 63000 46900 1 0 0 and2-1.sym
{
T 63400 46800 5 10 1 1 0 2 1
refdes=U?
T 63400 47000 5 8 0 0 0 0 1
device=and
}
N 59100 49900 59100 48200 4
N 58500 48200 65900 48200 4
N 63000 48200 63000 49900 4
N 65900 49700 65900 48200 4
N 61200 45500 61200 45600 4
N 58500 45500 65100 45500 4
N 63000 45500 63000 47000 4
N 65100 45600 65100 45500 4
T 60300 45100 9 10 1 0 0 0 1
ASYNCHRONOUS
T 64900 45100 9 10 1 0 0 0 1
BOTH
T 60500 51000 9 10 1 0 0 0 1
SYNCHRONOUS
T 64400 50800 9 10 1 0 0 0 2
SYNCHRONOUS
with OVERRIDE
/reset_fig2.sch
0,0 → 1,51
v 20100214 2
C 58200 44800 1 0 0 frame_800x600.sym
C 59100 46000 1 0 0 reg_rst.sym
{
T 60900 47800 5 10 0 0 0 0 1
device=REGISTER_RST
T 60400 48000 5 10 1 1 0 6 1
refdes=U?
}
C 64900 49100 1 0 0 reg_rst.sym
{
T 66700 50900 5 10 0 0 0 0 1
device=REGISTER_RST
T 66200 51100 5 10 1 1 0 6 1
refdes=U?
}
C 63600 47300 1 0 0 and2-1.sym
{
T 64000 47200 5 10 1 1 0 2 1
refdes=U?
T 64000 47400 5 8 0 0 0 0 1
device=and
}
T 63700 46300 9 10 1 0 0 0 3
ASYNCHRONOUS
DFT CONTROL
LOGIC
C 62300 47500 1 0 0 or2-1.sym
{
T 62700 47400 5 10 1 1 0 2 1
refdes=U?
T 62700 47600 5 8 0 0 0 0 1
device=or
}
N 60700 47600 62300 47600 4
N 63600 47400 63400 47400 4
N 63400 47400 63400 45700 4
N 58700 45700 63400 45700 4
N 59900 45700 59900 46000 4
N 64900 47600 65700 47600 4
N 65700 47600 65700 49100 4
N 62300 48000 62300 49000 4
N 62300 49000 58700 49000 4
T 58800 49100 9 10 1 0 0 0 1
ATG_ASYNCDISABLE
T 58700 45800 9 10 1 0 0 0 1
RESET_N
B 62000 46900 3200 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60600 47800 9 10 1 0 0 0 2
ACTIVE LOW
RESET
/supply_chain.sch
0,0 → 1,42
v 20100214 2
C 57500 35300 1 0 0 frame_800x600.sym
V 58300 41100 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 58100 40100 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 58100 39200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 58100 38300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 58200 36900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 58800 36400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 59700 36100 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 59200 41300 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 64900 40500 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 64900 39400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 64900 38400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 64900 37300 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 59600 37900 1400 1400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 62200 37900 1400 1400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 59700 38500 9 10 1 0 0 0 1
Manufacturing
T 62500 38600 9 10 1 0 0 0 1
Distribution
T 57900 35800 9 10 1 0 0 0 1
Suppliers
T 64700 36300 9 10 1 0 0 0 1
End Users
L 59300 41100 59800 39300 3 0 0 0 -1 -1
L 58400 40900 59600 39300 3 0 0 0 -1 -1
L 58300 40000 59600 39000 3 0 0 0 -1 -1
L 58300 39100 59600 38700 3 0 0 0 -1 -1
L 58400 38300 59600 38400 3 0 0 0 -1 -1
L 58400 37100 59600 38100 3 0 0 0 -1 -1
L 59000 36600 59800 37900 3 0 0 0 -1 -1
L 59800 36300 60000 37900 3 0 0 0 -1 -1
L 64700 40400 63600 39200 3 0 0 0 -1 -1
L 64700 39300 63600 38800 3 0 0 0 -1 -1
L 64700 38400 63600 38500 3 0 0 0 -1 -1
L 64700 37400 63600 38200 3 0 0 0 -1 -1
L 61000 38800 62200 38800 3 0 0 0 -1 -1
L 61000 38500 62200 38500 3 0 0 0 -1 -1
L 62200 38800 62000 39000 3 0 0 0 -1 -1
L 62200 38500 62000 38300 3 0 0 0 -1 -1
T 60500 36900 9 20 1 0 0 0 1
SUPPLY CHAIN
/ver_fig1.sch
0,0 → 1,90
v 20100214 2
C 50500 14600 1 0 0 frame_800x600.sym
B 54300 15300 1200 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 52800 15300 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51000 15300 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 54700 16100 9 10 1 0 0 0 1
DUT
T 52900 15700 9 10 1 0 0 0 3
BFM
MODEL
 
T 51000 15800 9 10 1 0 0 0 2
TEST_DEFINE
 
B 56300 15300 800 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 57500 15300 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 56400 15700 9 10 1 0 0 0 3
BFM
MODEL
 
T 57500 15800 9 10 1 0 0 0 2
TEST_DEFINE
 
L 52400 16100 52800 16100 3 0 0 0 -1 -1
L 52400 16000 52800 16000 3 0 0 0 -1 -1
L 52800 16000 52700 15900 3 0 0 0 -1 -1
L 52800 16100 52700 16200 3 0 0 0 -1 -1
L 52400 16100 52500 16200 3 0 0 0 -1 -1
L 52400 16000 52500 15900 3 0 0 0 -1 -1
L 57100 16100 57500 16100 3 0 0 0 -1 -1
L 57100 16000 57500 16000 3 0 0 0 -1 -1
L 57500 16000 57400 15900 3 0 0 0 -1 -1
L 57500 16100 57400 16200 3 0 0 0 -1 -1
L 57100 16100 57200 16200 3 0 0 0 -1 -1
L 57100 16000 57200 15900 3 0 0 0 -1 -1
L 53600 16100 54300 16100 3 0 0 0 -1 -1
L 53600 16000 54300 16000 3 0 0 0 -1 -1
L 55500 16100 56300 16100 3 0 0 0 -1 -1
L 55500 16000 56300 16000 3 0 0 0 -1 -1
L 53600 16100 53700 16200 3 0 0 0 -1 -1
L 53600 16000 53700 15900 3 0 0 0 -1 -1
L 54300 16100 54200 16200 3 0 0 0 -1 -1
L 54300 16000 54200 15900 3 0 0 0 -1 -1
L 55500 16100 55600 16200 3 0 0 0 -1 -1
L 55500 16000 55600 15900 3 0 0 0 -1 -1
L 56300 16100 56200 16200 3 0 0 0 -1 -1
L 56300 16000 56200 15900 3 0 0 0 -1 -1
B 50700 14800 8500 2600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51200 17100 9 10 1 0 0 0 1
TEST_CASE
V 54700 19700 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 56400 20100 2200 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 56900 20300 9 10 1 0 0 0 1
LOG FILE
B 56400 19100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 56500 19300 9 10 1 0 0 0 1
VALUE CHANGE DUMP FILE
L 55565 20197 56400 20300 3 0 0 0 -1 -1
L 55700 19400 56400 19300 3 0 0 0 -1 -1
L 54700 18700 54700 17400 3 0 0 0 -1 -1
L 54700 18700 54600 18600 3 0 0 0 -1 -1
L 54700 18700 54800 18600 3 0 0 0 -1 -1
T 54200 19600 9 10 1 0 0 0 2
VERILOG
SIMULATOR
L 56400 20300 56283 20335 3 0 0 0 -1 -1
L 56400 20300 56301 20223 3 0 0 0 -1 -1
L 56400 19300 56300 19400 3 0 0 0 -1 -1
L 56400 19300 56300 19200 3 0 0 0 -1 -1
T 51500 20100 9 10 1 0 0 0 2
COMMAND
LINE OPTIONS
T 51600 19100 9 10 1 0 0 0 2
FIRMWARE
BIT IMAGE
T 51600 18200 9 10 1 0 0 0 2
FIRMWARE
BIT IMAGE
B 51400 19900 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51400 18900 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51400 18000 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 52900 20300 53800 20100 3 0 0 0 -1 -1
L 52900 19200 53700 19500 3 0 0 0 -1 -1
L 52900 18300 54000 19000 3 0 0 0 -1 -1
L 54000 19000 53839 18974 3 0 0 0 -1 -1
L 54000 19000 53910 18837 3 0 0 0 -1 -1
L 53800 20100 53700 20200 3 0 0 0 -1 -1
L 53800 20100 53682 20051 3 0 0 0 -1 -1
L 53700 19500 53521 19519 3 0 0 0 -1 -1
L 53700 19500 53587 19345 3 0 0 0 -1 -1

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