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<h1><a name="socgen_project"></a><big>SOCGEN Project</big></h1>
<h2><br>
</h2>
<h2><a name="manifesto"></a>Verification Guidelines</h2>
<p><br>
<br>
</p>
<p>Verification is the art of stimulating&nbsp; a component&nbsp;
module and checking that it produces the correct outputs. Stimulations
are designed to
ensure that all of the components functions are exercised and any
deviation from the expected value is reported as an error. Every
component must have at least one test case but may have as many as
needed to fully verify the design.<br>
</p>
<p>A complete test suite is required for every component module.&nbsp;
Each test_case is simulated and the log file will indicate whether the
test passed or failed. Other output files such as dump files may also
be produced duging the simulation.<br>
</p>
<p><br>
</p>
<p></p>
<br>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig1.png"><br>
</p>
<p><br>
</p>
<p>A test suite is needed for every piece of IP in the design and
creating this suite can be a very labor intensive operation. It usually
takes four hours to create the test_cases for each hour that was spent
creating the rtl code.&nbsp; A full test must be run on every leaf cell
component and some of these are repeated as the components are used as
children of other components.&nbsp; It is essential that all test_cases
are written so that they may be reused when testing the component when
it it part of a parent component.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig2.png"><br>
</p>
<p>In this case a new component is created by combining&nbsp; two leaf
cell components and its test_case is created by combining blocks from
those two components test_cases.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig3.png"><br>
</p>
<p><br>
</p>
<p>Every interface on the component is connected to it's own bfm model
that contains all the tasks needed to test the interface. The calling
sequences needed to preform a particular test are all loaded from a
sperate file. It is important that each interface has its task calls in
a seperate code block. The goal is to develope these models and task
calls on&nbsp; the component simulation and then reuse them as the
component is used in larger designs.&nbsp; Interleaving task calls for
different models makes that difficult.<br>
</p>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>guidelines for creating reusable test_cases<br>
</h2>
<br>
&nbsp; All test_cases will have a master clock and reset signal.&nbsp;
The DUT and all models will respond to the reset signal. Anything in
test_define will only change state on the rising edge of clock.<br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;">&nbsp; All test_cases will be
self-checking.&nbsp; Test suites are usually run by scripts and robots
that need a simple method to determine wether a test_case finished and
passed. </span><br style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;">&nbsp; All models, tasks and protocal
checkers will use a common method to report&nbsp; if there is a failure.</span><br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;">&nbsp; All test sequences will use a
common method to signal the successful completion of the test</span><br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;">&nbsp; All messages in the log file
must use the following format:</span><br>
<br style="font-family: serif;">
<ul style="font-family: monospace;">
<li><big>Time stamp&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; This is the
$realtime&nbsp; formated by %t</big></li>
<li><big>Instance Name&nbsp;&nbsp;&nbsp;&nbsp; This is obtained with
%m</big></li>
<li><big>Message Type&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; This is either
ERROR&nbsp; or WARNING. No type indicates informational message</big></li>
<li><big>Message&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 
 
</big><br>
</li>
</ul>
<br style="font-family: serif;">
<br style="font-family: serif;">
<p style="font-family: serif;">&nbsp;&nbsp; All test cases MUST have a
finite run time.&nbsp; Use a TIMEOUT counter to stop the sim if it
exceeds the expected number of clocks<br style="font-family: serif;">
</p>
<span style="font-family: serif;">&nbsp;&nbsp;
<code><span style="font-family: serif;">All test_cases must be
deterministic. If any pseudorandom delays are used they must be
"seeded" and repeatable from run to run.</span></code></span><code
style="font-family: serif;"><br>
<br>
<br>
&nbsp;<span style="font-family: serif;"> </span></code><span
style="font-family: serif;"><code><span style="font-family: serif;">Do
not interweave threads in the test_define blocks. Each block should
only access a single BFM.</span><br style="font-family: serif;">
<br style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;">&nbsp; Plan on designs where you will
need to test multiple instances of a component</span><br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;">&nbsp; Only test a single
configuration or mode in any test_case. If you need to test 3 different
modes then create 3 different test_cases. The exception to this is when
there is a mission mode requirement to switch modes and you are testing
that switch.&nbsp; </span><br style="font-family: serif;">
</code></span>
<p style="font-family: serif;"><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>simulation directory (sim)<br>
</h2>
<p><br>
</p>
<big><code>
./sim<br>
&nbsp; +/bin<br>
&nbsp;&nbsp; &nbsp;&nbsp; Makefile<br>
&nbsp; +/bench<br>
&nbsp;&nbsp; &nbsp;&nbsp; +verilog<br>
&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; TestBench<br>
&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; +models<br>
&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; model1<br>
&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; model2<br>
&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; .<br>
&nbsp; +/lib<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +lib_part1<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; lib_part(s).v<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +lib_part2<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
</code><code>&nbsp; +/run</code><br>
<code>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +test_case1<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; filelist<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; dmp_define<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; modellist<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; dut<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_define<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; liblist<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TB.defs<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +test_case2<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp; +/log<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case1.log<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case2.log<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp; +/out<br>
&nbsp;</code><code>&nbsp;&nbsp;&nbsp;&nbsp; test_case1.vcd<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case2.vcd<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .</code><br>
</big>
<code><ouabache design="" works=""><big><br>
<br>
<br>
</big>
<br>
</ouabache></code>
<p>Each component will have a ./sim directory for the test suite.
Typing:<br>
</p>
<p><big><big><br>
<small><span style="font-family: monospace;">
&lt;&gt;:~$&gt;cd ./sim/bin</span><br style="font-family: monospace;">
</small><span style="font-family: monospace;"><small>
&lt;&gt;:~$&gt;make run_sims</small><br>
</span></big></big></p>
<p><big><big><span style="font-family: monospace;"><br>
</span></big></big>
</p>
will run the entire test suite. After that has been done then
individual test_cases may be rerun by changing into their test_case
directory and typing:<br>
<code><ouabache design="" works=""><br>
<br>
</ouabache></code>
<p><big><big><span style="font-family: monospace;"><small>&lt;&gt;:~$&gt;make
sim</small></span></big></big>
</p>
<p><br>
</p>
<p>Each test_case will produce a log file that may be parsed for the
string "PASSED" to indicate that the sim finished. If so then the log
file should be parsed for the strings "ERROR" and "WARNING" to see if
there were and errors or warnings. <br>
</p>
<p>Simulating a test_case requires involking a verilog simulator and
passing it command line arguments and a TestBench file. Icarus verilog
is the default simulator for the socgen project. Socgen uses a minumal
command line and instead puts most needed information in the TestBench
file.&nbsp; The only command line option is to set the VCD flag if a
value change dump file is needed.<br>
</p>
<p><br>
</p>
<p><br>
<br>
<br>
<br>
<br>
</p>
<h2><a name="manifesto"></a>TestBench file<br>
</h2>
<code>
<ouabache design="" works="">--------------------------------------------------------------------------------------------------------------------------------------<br>
<br>
`include&nbsp; "./TB.defs"<br>
<br>
`ifndef&nbsp;&nbsp;&nbsp;&nbsp; TIMESCALE<br>
`define&nbsp;&nbsp;&nbsp;&nbsp; TIMESCALE&nbsp;&nbsp; 1ns/1ns<br>
`endif<br>
<br>
<br>
`ifndef&nbsp;&nbsp;&nbsp;&nbsp; TIMEFORMAT<br>
`define&nbsp;&nbsp;&nbsp;&nbsp; TIMEFORMAT&nbsp; $timeformat(-6, 2, "
us", 14);<br>
`endif<br>
<br>
<br>
`ifndef&nbsp;&nbsp;&nbsp;&nbsp; PERIOD<br>
`define&nbsp;&nbsp;&nbsp;&nbsp; PERIOD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
40.00000 <br>
`endif<br>
<br>
`ifndef&nbsp;&nbsp;&nbsp;&nbsp; TIMEOUT<br>
`define&nbsp;&nbsp;&nbsp;&nbsp; TIMEOUT&nbsp;&nbsp;&nbsp;&nbsp; 200000<br>
`endif<br>
<br>
<br>
`timescale `TIMESCALE<br>
<br>
<br>
`include&nbsp; "./filelist"<br>
`include&nbsp; "./liblist"<br>
`include&nbsp; "./modellist"<br>
<br>
<br>
<br>
<br>
module TB();<br>
<br>
wire clk;<br>
wire reset;<br>
<br>
`include "./dut"<br>
`include "./test_define"<br>
<br>
<br>
`ifdef VCD<br>
initial<br>
begin<br>
`include "./dmp_define"<br>
end<br>
`endif<br>
<br>
clock_gen<br>
#(.PERIOD(`PERIOD),<br>
&nbsp; .TIMEOUT(`TIMEOUT))<br>
cg <br>
( .clk&nbsp;&nbsp; ( clk&nbsp;&nbsp; ),<br>
&nbsp;
.reset ( reset )<br>
);<br>
<br>
<br>
<br>
<br>
endmodule<br>
</ouabache></code><span style="font-family: monospace;"><br>
--------------------------------------------------------------------------------------------------------------------------------------<br>
</span>
<p><span style="font-family: monospace;"><br>
</span></p>
<p><br>
<span style="font-family: monospace;"></span></p>
<p>A single&nbsp; TestBench file provides the infrastructure for all
test cases. The actual testing is determined by the data contained in
six files in the ./sim/run/test_case directory. The TestBench file
creates a top level module named TB and instantiates a clock_reset
generator module to provide each test_case with a clock and a reset
signal. It also provides a vcd dump&nbsp; and timeout&nbsp; functions
for each test_case.<span style="font-family: monospace;"><br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<h2><a name="manifesto"></a>TB.defs <br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
<code>
`define&nbsp;&nbsp;&nbsp;&nbsp; TIMESCALE&nbsp;&nbsp; 1ns/1ns<br>
`define&nbsp;&nbsp;&nbsp;&nbsp; TIMEFORMAT&nbsp; $timeformat(-6, 2, "
us", 14);<br>
`define&nbsp;&nbsp;&nbsp;&nbsp; PERIOD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
40.0000 <br>
`define&nbsp;&nbsp;&nbsp;&nbsp; TIMEOUT&nbsp;&nbsp;&nbsp;&nbsp; 200000<br>
</code>
<p></p>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------<br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<p>The TB.defs file may be used to set up the timescale and master
clock period for the simulation.&nbsp; Any model or lib part that needs
to reset the timescale back to the system default must use:<br>
</p>
<p><code>`timescale `TIMESCALE<br>
</code></p>
<p><code><br>
<span style="font-family: serif;">Do NOT use</span><br>
</code></p>
<p><code>`include "./timescale.v"<br>
</code></p>
<p><code><br>
<span style="font-family: serif;">The socgen project does not contain
any timescale.v file.&nbsp; All socgen rtl code is preprocessed before
it is passed to simulation and the value of the timescale may change
depending on the simulation. All ip components must only contain
synthesisable code and should not have any need for timescale.<br>
</span></code></p>
<p><code><span style="font-family: serif;">TIMEFORMAT will set the
format that is used when time is displayed using the %t format . All
$display statements must start by displaying $realtime using the %t
format so every line in the log has a time stamp. Any display statement
from an instantiated module must also have %m to print out it's
instance name. If the message is an error or a warning then the strings
ERROR or WARNING must be used so that this information may be parsed
from the log file.<br>
<br style="font-family: serif;">
</span></code></p>
<p><span style="font-family: monospace;"><br>
</span>The TB.defs file may also
be used to pass the size and location&nbsp; of an embedded&nbsp; bit
file to the device_under_test<span style="font-family: monospace;"> <br>
</span></p>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
<p><span style="font-family: monospace;">`define&nbsp; ROM_WORDS 2048 <br>
`define&nbsp; ROM_ADDR&nbsp;&nbsp; 11&nbsp; <br>
`define&nbsp; ROM_WIDTH&nbsp; 12&nbsp; <br>
`define&nbsp; ROM_FILE "../../../../../sw/mouse/mouse.abs12"<br>
</span><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p>The path is the relative path from the test_case run directory.<span
style="font-family: monospace;"><br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<h2><a name="manifesto"></a>filelist </h2>
<p style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------<br>
</p>
<p style="font-family: monospace;">`include
"../../../rtl/gen/sim/soc_mouse.v"<br>
`include "../../../../pic16c5x/rtl/gen/sim/pic16c5x.v"<br>
`include
"../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module_mouse.v"<br>
`include
"../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"<br>
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"<br>
</p>
<code style="font-family: monospace;"></code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
<p><br>
</p>
<p>The filelist uses `include statements to load all the rtl files into
the simulation.The paths are&nbsp; relative from the test_case run
directory. Note that all the verilog files have been post-processed and
search directories or include directories are not needed.
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>liblist</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
<code>
<br>
`include "../../lib/cde_sram/cde_sram.v"<br>
`include "../../lib/cde_lifo/cde_lifo.v"<br>
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"<br>
<br>
</code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
<p>The liblist uses `include statements to load all the generic lib
models&nbsp; into
the simulation.The paths are&nbsp; relative from the test_case run
directory. Note that these libs may be replaced&nbsp; by vendor
specific instances when the design is&nbsp; synthesised into gates.<br>
</p>
<p><br>
</p>
<p></p>
<p><br>
</p>
<h2><a name="manifesto"></a>modellist</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
<code><br>
`include "../../bench/verilog/models/clock_gen.v"<br>
`include "../../bench/verilog/models/ps2_model.v"&nbsp;&nbsp;&nbsp; <br>
`include "../../bench/verilog/models/iobuftri.v"&nbsp;&nbsp;&nbsp; <br>
</code><span style="font-family: monospace;"></span><code><br>
</code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
<br>
This list loads all of the simulation models used in the simulation.<br>
<br>
<p><br>
<br>
</p>
<h2><a name="manifesto"></a>dut<br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
<p><code>reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
device_write;<br>
reg&nbsp; [7:0]&nbsp;&nbsp; device_tx_data;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_parity;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_ack;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_stop;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_rx_read;<br>
wire [7:0]&nbsp;&nbsp; device_rx_data;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_rx_parity;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_data_pad_oe;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_data_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_data;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_clk_pad_oe;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_clk_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_clk;<br>
<br>
<br>
<br>
wire [7:0]&nbsp;&nbsp;&nbsp;&nbsp; portaout;<br>
wire [7:0]&nbsp;&nbsp;&nbsp;&nbsp; portbout;<br>
wire [7:0]&nbsp;&nbsp;&nbsp;&nbsp; portcout;<br>
<br>
<br>
wire [9:0]&nbsp;&nbsp;&nbsp;&nbsp; y_pos;<br>
wire [9:0]&nbsp;&nbsp;&nbsp;&nbsp; x_pos;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
new_packet;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ms_mid; <br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ms_right;&nbsp; <br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ms_left;&nbsp; <br>
<br>
<br>
<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
txd_pad_out;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
rxd_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
cts_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
rts_pad_out;&nbsp; <br>
<br>
<br>
// Instantiate one CPU to be tested.<br>
soc_mouse<br>
#(<br>
.ROM_WORDS ( `ROM_WORDS ), <br>
.ROM_ADDR&nbsp; ( `ROM_ADDR&nbsp; ),&nbsp; <br>
.ROM_WIDTH ( `ROM_WIDTH ), <br>
.ROM_FILE&nbsp; ( `ROM_FILE&nbsp; )<br>
)<br>
dut(<br>
&nbsp;&nbsp; .clk&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; (
clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .reset&nbsp;&nbsp;&nbsp; (
reset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
<br>
&nbsp;&nbsp; .ps2_data_pad_in ( ps2_data_pad_in ),<br>
&nbsp;&nbsp; .ps2_clk_pad_in&nbsp; ( ps2_clk_pad_in&nbsp; ),<br>
<br>
&nbsp;&nbsp; .ps2_data_pad_oe ( ps2_data_pad_oe ),<br>
&nbsp;&nbsp; .ps2_clk_pad_oe&nbsp; ( ps2_clk_pad_oe&nbsp; ),<br>
<br>
<br>
&nbsp;&nbsp; .portaout&nbsp;&nbsp;&nbsp; ( portaout&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .portbout&nbsp;&nbsp;&nbsp; ( portbout&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .portcout&nbsp;&nbsp;&nbsp; ( portcout&nbsp;&nbsp;&nbsp; ),<br>
<br>
<br>
&nbsp;&nbsp; .y_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
y_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .x_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
x_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .new_packet&nbsp; ( new_packet&nbsp; ),<br>
&nbsp;&nbsp; .ms_mid&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
ms_mid&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ), <br>
&nbsp;&nbsp; .ms_right&nbsp;&nbsp;&nbsp; ( ms_right&nbsp;&nbsp;&nbsp;
),&nbsp; <br>
&nbsp;&nbsp; .ms_left&nbsp;&nbsp;&nbsp;&nbsp; (
ms_left&nbsp;&nbsp;&nbsp;&nbsp; ),&nbsp; <br>
<br>
<br>
<br>
&nbsp;&nbsp; .txd_pad_out ( loop1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .rxd_pad_in&nbsp; (
loop1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .cts_pad_in&nbsp; (
loop2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .rts_pad_out ( loop2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
)&nbsp; <br>
<br>
&nbsp;&nbsp; );<br>
<br>
<br>
iobuftri<br>
data_tri_buf<br>
&nbsp; (<br>
&nbsp;&nbsp; .i&nbsp;&nbsp; (
1'b0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .oe&nbsp; ( ps2_data_pad_oe ),<br>
&nbsp;&nbsp; .o&nbsp;&nbsp; ( ps2_data_pad_in ),<br>
&nbsp;&nbsp; .pad ( ps2_data&nbsp;&nbsp;&nbsp; )<br>
&nbsp;&nbsp; );<br>
<br>
<br>
iobuftri<br>
clk_tri_buf<br>
&nbsp; (<br>
&nbsp;&nbsp; .i&nbsp;&nbsp; ( 1'b0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp; .oe&nbsp; ( ps2_clk_pad_oe ),<br>
&nbsp;&nbsp; .o&nbsp;&nbsp; ( ps2_clk_pad_in ),<br>
&nbsp;&nbsp; .pad ( ps2_clk&nbsp;&nbsp;&nbsp; )<br>
&nbsp;&nbsp; );<br>
<br>
<br>
<br>
pullup ua0(ps2_clk);<br>
pullup ua1(ps2_data);<br>
<br>
<br>
ps2_model <br>
#(.CLKCNT(10'h177))<br>
ps2<br>
(<br>
&nbsp;&nbsp;
.clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.reset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
reset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),
<br>
&nbsp;&nbsp;
.send&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_write&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.send_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_tx_data&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.device_parity&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_parity&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp;
.device_ack&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_ack&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.device_stop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_stop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.device_rx_read&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_rx_read&nbsp;&nbsp; ),<br>
&nbsp;&nbsp;
.device_rx_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_rx_data&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .device_rx_parity&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_rx_parity ),<br>
<br>
&nbsp;&nbsp;
.ps2_clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
ps2_clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.ps2_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
ps2_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
)<br>
<br>
);<br>
</code><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p>This file is a verilog code segment that declares all the wires and
regs needed in the sim (except for clk and reset). It then&nbsp;
instantiates the component and all needed models for the simulation.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>test_define<br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
<p><br>
</p>
<p><span style="font-family: monospace;">initial</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">begin</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">&nbsp;`TIMEFORMAT</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
");</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
===================================================");</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Test
Start");</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
===================================================");</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
");</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h00;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_ack&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_stop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">cg.reset_off;</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'haa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h00;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h03;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h12;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h34;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h56;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h78;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'h9a;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity&nbsp;&nbsp;&nbsp;
=&nbsp; 1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data&nbsp;&nbsp;
=&nbsp; 8'hbc;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write&nbsp;&nbsp;&nbsp;&nbsp;
=&nbsp;
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">$display("%t&nbsp;&nbsp;&nbsp;
Test&nbsp; PASSED",$realtime);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$finish;</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">end</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<br>
</p>
<p><br>
</p>
<p><br>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>dmp_define<br>
</h2>
<p style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------<br>
</p>
<p style="font-family: monospace;">$dumpfile ("TestBench.vcd");<br>
$dumpvars (0, TB);<br>
--------------------------------------------------------------------------------------------------------------------------------------<br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p>This is a test<br>
</p>
<p><br>
&nbsp;<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
</body>
</html>
/guide_database.html
2,7 → 2,7
<html>
<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=UTF-8">
<title>start</title>
<title>Design Database Management</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
<meta name="CHANGED" content="20100309;9302100">
/guide_documentation.html
2,7 → 2,7
<html>
<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=UTF-8">
<title>start</title>
<title>Documentation Guidelines</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
<meta name="CHANGED" content="20100309;9322200">
/reset_sys_design.html
1,8 → 1,8
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
<title>start</title>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=UTF-8">
<title>Reset System Design</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
<meta name="CHANGED" content="20100309;9305300">
79,7 → 79,7
<p>You do not need a power on reset system for your logic to work. You
need it&nbsp; in order to verify that your logic works.&nbsp; It takes
longer to verify a design than it does to create it and not providing a
100% known startup condition will make the verification effort that
100% known start up condition will make the verification effort that
much harder. All storage elements must be on a reset if only for test
and verification purposes. If you have logic that must function during
a power up reset then put it on a special reset that is only active in
89,7 → 89,7
<h3 class="western">All components must come out of reset on exactly
the same clock<br>
</h3>
Thats true, or at least it was back in the 60's.&nbsp; Back then every
That's true, or at least it was back in the 60's.&nbsp; Back then every
component would come out of reset and start "componenting". The reset
system acted like a conductor&nbsp; so that everybody started on the
same beat. Those types of systems are rare today. Most major chips have
128,7 → 128,7
<h3 class="western">You must design your logic using synchronous design
methods<br>
</h3>
Absolutely. Todays chips are huge. The only way that you can close
Absolutely. Today's chips are huge. The only way that you can close
timing on a large design is if everyone follows strict synchronous
design rules.&nbsp; The mistake that many of todays designers make is
that they think that because they have to design an asynchronous reset
152,7 → 152,7
signals crossing between&nbsp; the async reset port on a flipflop and
either a D or a Q port then it flags it as a violation. So you can
either send it back to the customer and wait a week for them to find
it, fix it, and resynthesizes or you can eco in a test mux at the flop
it, fix it, and re-synthesizes or you can eco in a test mux at the flop
and have it fixed in 5 minutes. Everyone took the easy way out.<br>
<br>
But then along came Logic equivalence checking (LEC).&nbsp; The final
220,7 → 220,8
value&nbsp; and it can't. There are also times when it will resolve an
X to a known value when it shouldn't. The only way to use verilog is to
start with everything in a known state and stop it when anything goes
X.&nbsp; That means theres a problem and nothing downstream from that X
X.&nbsp; That means there's a problem and nothing downstream from that
X
can be trusted.<br>
<br>
<br>
227,7 → 228,7
You do not prove your reset system design in gates sims. You prove the
design in rtl sims and use LEC to prove that gates matches the design
that works.&nbsp; Then you use initial statements to force all flops to
a known state at startup and use gates sims to prove that everything
a known state at start up and use gates sims to prove that everything
else works. Verilog gates is the wrong tool to use to verify the reset
system.<br>
<br>
275,7 → 276,7
system clock that is measured in the nanoseconds. Performing a reset in
one clock cycle&nbsp; requires adding logic to every single flipflop<br>
for no good reason. A designer should only add reset logic as a last
resort. The prefered method is to use the existing mission mode logic
resort. The preferred method is to use the existing mission mode logic
to perform the reset. If you have a computational block with a fifty
stage deep pipeline then reset should force it's inputs to 0 and open
all the gates so that every flipflop will be flushed out in 50 clocks.
334,7 → 335,7
enough period of time</li>
</ul>
<ul>
<li>The design has a soft reset block that can reset any subblock if
<li>The design has a soft reset block that can reset any sub block if
its reset flop is set to 1.</li>
</ul>
<ul>
350,7 → 351,7
</li>
</ul>
The last is important because some designers will forget that the
filtered output is actually it's own seperate reset domain<br>
filtered output is actually it's own separate reset domain<br>
<br>
<br>
<br>
385,7 → 386,8
<li>an active low on the output of the metastable filter</li>
</ul>
<br>
The jtag reset is not included because it doesnt reset the timer.&nbsp;
The jtag reset is not included because it doesn't reset the
timer.&nbsp;
Once this step is complete it will provide a map for the reset
distribution tree that you will need. The best way to distribute the
reset over a large design is to use what is called a "synchronous reset
411,14 → 413,28
<br>
<br>
<br>
<h3 class="western">6) Select reset style for each flip/flop<br>
</h3>
We now need to select a reset "Style" for each flip/flop from the four
possible reset styles.<br>
<br>
<br>
<ul>
<li>Synchronous</li>
<li>Synchronous with output override</li>
<li>Asynchronous</li>
<li>Both Synchronous and Asynchronous</li>
</ul>
<br>
If the reset system is synchronous then you may choose any of the four
styles. If it is asynchronous then you cannot use the synchronous style.<br>
<br>
<br>
<br>
<br>
<br>
<img style="width: 800px; height: 600px;" alt=""
src="../png/reset_fig1.png"><br>
<br>
<br>
<br>
427,8 → 443,32
<br>
<br>
<br>
<h3 class="western">7) Apply DFT fixes to all asynchronous ports<br>
</h3>
All paths from the Q output of a flip/flop to the asynchronous
reset/preset port of a flip/flop must be disabled during scan testing.
The use of a test mux to do this is not recommended because anytime you
use a test mux you are not testing the circuit as it is used in mission
mode. There will always be at least one point of failure inside the
test mux where scan tests will pass but the IC will not function.<br>
<br>
The recommended method is to gate off the synchronous path with a atg
test signal and then recombine it with an asynchronous reset so that
the async reset it self is still testable. The lib module
cde_asyncdisable is available for this purpose. DO NOT CREATE YOUR OWN
TEST LOGIC.&nbsp; Checking the rtl code to ensure that all asynchronous
resets are testable requires a fairly sophisticated and expensive tool.
Checking the rtl to ensure that all asynchronous resets are properly
connected to a cde_asyncdisable module takes a simple perl script.<br>
<br>
<br>
<br>
<br>
<br>
<br>
<img style="width: 800px; height: 600px;" alt=""
src="../png/reset_fig2.png"><br>
<br>
<p><br>
<br>
</p>

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