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URL https://opencores.org/ocsvn/socgen/socgen/trunk

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  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/doc/src
    from Rev 85 to Rev 94
    ↔ Reverse comparison
  •

Rev 85 → Rev 94

/guides/guide_verification.html
20,7 → 20,7
<p><br>
<br>
</p>
<p>Verification is the art of stimulating&nbsp; a component&nbsp;
<p>Verification is the process of stimulating&nbsp; a component&nbsp;
module and checking that it produces the correct outputs. Stimulations
are designed to
ensure that all of the components functions are exercised and any
166,6 → 166,7
 
 
 
 
</big><br>
</li>
</ul>
184,7 → 185,8
<br>
&nbsp;<span style="font-family: serif;"> </span></code><span
style="font-family: serif;"><code><span style="font-family: serif;">Do
not interweave threads in the test_define blocks. Each block should
not interweave threads in the test_define blocks. Each fork/join block
should
only access a single BFM.</span><br style="font-family: serif;">
<br style="font-family: serif;">
<br style="font-family: serif;">
249,15 → 251,6
./sim<br>
&nbsp; +/bin<br>
&nbsp;&nbsp; &nbsp;&nbsp; Makefile<br>
&nbsp; +/bench<br>
&nbsp;&nbsp; &nbsp;&nbsp; +verilog<br>
&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; TestBench<br>
&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; +models<br>
&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; model1<br>
&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; model2<br>
&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; .<br>
&nbsp; +/lib<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +lib_part1<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; lib_part(s).v<br>
266,36 → 259,20
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
</code><code>&nbsp; +/run</code><br>
<code>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +test_case1<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; filelist<br>
<code>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +/test_case1<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; dmp_define<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; modellist<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; dut<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_define<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; liblist<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TB.defs<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +test_case2<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; +/test_case2<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp; +/log<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case1.log<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case2.log<br>
&nbsp; +/xml<br>
&nbsp;</code><code>&nbsp;&nbsp;&nbsp;&nbsp; test_case1.xml<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case2.xml<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp; +/out<br>
&nbsp;</code><code>&nbsp;&nbsp;&nbsp;&nbsp; test_case1.vcd<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; test_case2.vcd<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .</code><br>
</big>
<code><ouabache design="" works=""><big><br>
<br>
<br>
</big>
<br>
<code><ouabache design="" works=""><br>
</ouabache></code>
<p>Each component will have a ./sim directory for the test suite.
Typing:<br>
501,16 → 478,10
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"<br>
</p>
<code style="font-family: monospace;"></code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
<span style="font-family: monospace;">-------------------------------------------------------------------------------------------------------------------------------------</span>
<p></p>
<p><br>
</p>
<p>The filelist uses `include statements to load all the rtl files into
the simulation.The paths are&nbsp; relative from the test_case run
directory. Note that all the verilog files have been post-processed and
search directories or include directories are not needed.
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>liblist</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
1306,21 → 1277,9
<p><br>
<br>
</p>
<p></p>
<p></p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p>This is a test<br>
</p>
<p><br>
&nbsp;<br>
</p>
<p><br>

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